Fix dynamic array assignment to make a copy of the rvalue.

IEEE Std 1800-2017 Section 7.6 Array assignments Assignment of a dynamic array creates a duplicate of the source, so that assignments to the copy don't impact the original. Handle all sorts of dynamic array base types.
Merge pull request #394 from steveicarus/super-new-handling
2026-08-24 23:06:56 +02:00 · 2020-11-26 12:52:06 -08:00 · 2020-11-22 16:48:45 -08:00 · 2020-11-22 16:13:01 -08:00 · 2020-11-22 15:31:40 -08:00 · 2020-11-20 21:42:39 -08:00
566 changed files with 62182 additions and 27898 deletions
@@ -0,0 +1,2 @@
+# gperf in MSYS chokes on DOS line endings
+*.gperf text eol=lf
@@ -0,0 +1,71 @@
+language: cpp
+sudo: required
+dist: xenial
+
+addons:
+  apt:
+    packages:
+    - gperf
+
+sudo: false
+
+notifications:
+  email: false
+
+jobs:
+  include:
+  
+    - stage: Test
+      os: linux
+      dist: xenial
+      before_install:
+        - git clone https://github.com/steveicarus/ivtest.git
+        - export PATH=$HOME/bin:$PATH
+      script:
+        - autoconf
+        - ./configure --prefix=$HOME
+        - make install
+        - make check
+        - cd ivtest
+        - perl vvp_reg.pl
+        - diff regression_report-devel.txt regression_report.txt
+        - perl vpi_reg.pl
+
+    - stage: Test
+      os: linux
+      dist: bionic
+      before_install:
+        - git clone https://github.com/steveicarus/ivtest.git
+        - export PATH=$HOME/bin:$PATH
+      script:
+        - autoconf
+        - ./configure --prefix=$HOME
+        - make install
+        - make check
+        - cd ivtest
+        - perl vvp_reg.pl
+        - diff regression_report-devel.txt regression_report.txt
+        - perl vpi_reg.pl
+
+    - stage: Test
+      os: windows
+      before_install:
+        - git clone https://github.com/steveicarus/ivtest.git
+        - choco uninstall -y mingw
+        - choco upgrade --no-progress -y msys2
+        - export msys2='cmd //C RefreshEnv.cmd '
+        - export msys2+='& set MSYS=winsymlinks:nativestrict '
+        - export msys2+='& C:\\tools\\msys64\\msys2_shell.cmd -defterm -no-start'
+        - export mingw64="$msys2 -mingw64 -full-path -here -c "\"\$@"\" --"
+        - export msys2+=" -msys2 -c "\"\$@"\" --"
+        - $msys2 pacman --sync --noconfirm --needed base-devel mingw-w64-x86_64-toolchain
+      script:
+        - $mingw64 ./autoconf.sh
+        - $mingw64 ./configure
+        - $mingw64 make install
+        - $mingw64 make check
+        - cd ivtest
+        - $mingw64 perl update_msys2_report.pl
+        - $mingw64 perl vvp_reg.pl
+        - diff --strip-trailing-cr regression_report-msys2.txt regression_report.txt
+        - $mingw64 perl vpi_reg.pl
@@ -1,7 +1,7 @@
-#ifndef __AStatement_H
-#define __AStatement_H
+#ifndef IVL_AStatement_H
+#define IVL_AStatement_H
 /*
- * Copyright (c) 2008 Stephen Williams ([email protected])
+ * Copyright (c) 2008-2014 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -82,4 +82,4 @@ class AProcess : public LineInfo {
      AProcess& operator= (const AProcess&);
 };

-#endif
+#endif /* IVL_AStatement_H */
@@ -1,7 +1,7 @@
-#ifndef __Attrib_H
-#define __Attrib_H
+#ifndef IVL_Attrib_H
+#define IVL_Attrib_H
 /*
- * Copyright (c) 2000-2009 Stephen Williams ([email protected])
+ * Copyright (c) 2000-2014 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -57,4 +57,4 @@ class Attrib {
      Attrib& operator= (const Attrib&);
 };

-#endif
+#endif /* IVL_Attrib_H */
@@ -116,13 +116,17 @@ programs.

 RESEARCHING EXISTING/PAST BUGS, AND FILING REPORTS

-The URL <http://sourceforge.net/tracker/?group_id=149850> is the main
-bug tracking system. Once you believe you have found a bug, you may
-browse the bugs database for existing bugs that may be related to
-yours. You might find that your bug has already been fixed in a later
-release or snapshot. If that's the case, then you are set. Also,
-consider if you are reporting a bug or really asking for a new
-feature, and use the appropriate tracker.
+The URL <https://sourceforge.net/p/iverilog/bugs/> is the main
+bug tracking system, although some users have reported bugs at
+<https://github.com/steveicarus/iverilog/issues/>. Once you believe
+you have found a bug, you may browse the bugs database for existing
+bugs that may be related to yours. You might find that your bug has
+already been fixed in a later release or snapshot. If that's the case,
+then you are set. Also, consider if you are reporting a bug or really
+asking for a new feature, and use the appropriate tracker.
+
+ system (although you will also find bug rep
+

 The bug database supports basic keyword searches, and you can
 optionally limit your search to active bugs, or fixed bugs. You may
@@ -145,7 +149,7 @@ version from git. Please see the developer documentation for more
 detailed instructions -- <http://iverilog.wikia.com/wiki/>.

 When you make a patch, submit it to the "Patches" tracker at
-<http://sourceforge.net/tracker/?group_id=149850>. Patches added to
+<https://sourceforge.net/p/iverilog/patches/>. Patches added to
 the "Patches" tracker enter the developer workflow, are checked,
 applied to the appropriate git branch, and are pushed. Then the
 tracker item is closed.
@@ -158,7 +162,7 @@ clarification before applying it.)

 COPYRIGHT ISSUES

-Icarus Verilog is Copyright (c) 1998-2008 Stephen Williams except
+Icarus Verilog is Copyright (c) 1998-2018 Stephen Williams except
 where otherwise noted. Minor patches are covered as derivative works
 (or editorial comment or whatever the appropriate legal term is) and
 folded into the rest of ivl. However, if a submission can reasonably
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2001-2012 Stephen Williams ([email protected])
+ * Copyright (c) 2001-2014 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -22,22 +22,26 @@
 # include  <iostream>
 # include  <cstring>
 # include  <cstdlib>
-# include  <climits>

+using namespace std;

 hname_t::hname_t()
 {
-      number_ = INT_MIN;
 }

 hname_t::hname_t(perm_string text)
 : name_(text)
 {
-      number_ = INT_MIN;
 }

 hname_t::hname_t(perm_string text, int num)
-: name_(text), number_(num)
+: name_(text), number_(1)
+{
+      number_[0] = num;
+}
+
+hname_t::hname_t(perm_string text, const vector<int>&nums)
+: name_(text), number_(nums)
 {
 }

@@ -53,24 +57,50 @@ hname_t& hname_t::operator = (const hname_t&that)
      return *this;
 }

-bool operator < (const hname_t&l, const hname_t&r)
+bool hname_t::operator < (const hname_t&r) const
 {
-      int cmp = strcmp(l.peek_name(), r.peek_name());
+      int cmp = strcmp(name_, r.name_);
      if (cmp < 0) return true;
      if (cmp > 0) return false;
-      if (l.has_number() && r.has_number())
-	    return l.peek_number() < r.peek_number();
-      else
-	    return false;
+
+	// The text parts are equal, so compare then number
+	// parts. Finish as soon as we find one to be less or more
+	// than the other.
+      size_t idx = 0;
+      while (number_.size() > idx || r.number_.size() > idx) {
+
+	      // Ran out of l numbers, so less.
+	    if (number_.size() <= idx)
+		  return true;
+
+	      // Ran out of r numbers, so greater.
+	    if (r.number_.size() <= idx)
+		  return false;
+
+	    if (number_[idx] < r.number_[idx])
+		  return true;
+
+	    if (number_[idx] > r.number_[idx])
+		  return false;
+
+	    idx += 1;
+      }
+
+	// Fall-through means that we are equal, including all the
+	// number parts, so not less.
+      return false;
 }

-bool operator == (const hname_t&l, const hname_t&r)
+bool hname_t::operator == (const hname_t&r) const
 {
-      if (l.peek_name() == r.peek_name()) {
-	    if (l.has_number() && r.has_number())
-		  return l.peek_number() == r.peek_number();
-	    else
-		  return true;
+      if (name_ == r.name_) {
+	    if (number_.size() != r.number_.size())
+		  return false;
+
+	    for (size_t idx = 0 ; idx < number_.size() ; idx += 1)
+		  if (number_[idx] != r.number_[idx]) return false;
+
+	    return true;
      }

      return false;
@@ -84,8 +114,8 @@ ostream& operator<< (ostream&out, const hname_t&that)
      }

      out << that.peek_name();
-      if (that.has_number())
-	    out << "[" << that.peek_number() << "]";
+      for (size_t idx = 0 ; idx < that.number_.size() ; idx += 1)
+	    out << "[" << that.number_[idx] << "]";

      return out;
 }
@@ -1,7 +1,7 @@
-#ifndef __HName_H
-#define __HName_H
+#ifndef IVL_HName_H
+#define IVL_HName_H
 /*
- * Copyright (c) 2001-2010 Stephen Williams ([email protected])
+ * Copyright (c) 2001-2014 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -21,13 +21,10 @@

 # include  <iostream>
 # include  <list>
+# include  <vector>
 # include  "StringHeap.h"
-# include  <climits>
-#ifdef __GNUC__
-#if __GNUC__ > 2
-using namespace std;
-#endif
-#endif
+
+# include  <cassert>

 /*
 * This class represents a component of a Verilog hierarchical name. A
@@ -39,27 +36,33 @@ using namespace std;

 class hname_t {

+      friend ostream& operator<< (ostream&out, const hname_t&that);
+
    public:
      hname_t ();
      explicit hname_t (perm_string text);
      explicit hname_t (perm_string text, int num);
+      explicit hname_t (perm_string text, const std::vector<int>&nums);
      hname_t (const hname_t&that);
      ~hname_t();

      hname_t& operator= (const hname_t&);

+      bool operator == (const hname_t&that) const;
+      bool operator <  (const hname_t&that) const;
+
 	// Return the string part of the hname_t.
      perm_string peek_name(void) const;

-      bool has_number() const;
-      int peek_number() const;
+      size_t has_numbers() const;
+      int peek_number(size_t idx) const;
+      const std::vector<int>&peek_numbers() const;

    private:
      perm_string name_;
-	// If the number is anything other than INT_MIN, then this is
-	// the numeric part of the name. Otherwise, it is not part of
-	// the name at all.
-      int number_;
+	// If this vector has size, then the numbers all together make
+	// up part of the hierarchical name.
+      std::vector<int> number_;

    private: // not implemented
 };
@@ -73,18 +76,22 @@ inline perm_string hname_t::peek_name(void) const
      return name_;
 }

-inline int hname_t::peek_number() const
+inline int hname_t::peek_number(size_t idx) const
+{
+      assert(number_.size() > idx);
+      return number_[idx];
+}
+
+inline const std::vector<int>& hname_t::peek_numbers(void) const
 {
      return number_;
 }

-inline bool hname_t::has_number() const
+inline size_t hname_t::has_numbers() const
 {
-      return number_ != INT_MIN;
+      return number_.size();
 }

-extern bool operator <  (const hname_t&, const hname_t&);
-extern bool operator == (const hname_t&, const hname_t&);
 extern ostream& operator<< (ostream&, const hname_t&);

 inline bool operator != (const hname_t&l, const hname_t&r)
@@ -102,4 +109,4 @@ inline ostream& operator<< (ostream&out, const list<hname_t>&ll)
      return out;
 }

-#endif
+#endif /* IVL_HName_H */
@@ -38,7 +38,7 @@ srcdir = @srcdir@
 datarootdir = @datarootdir@

 SUBDIRS = ivlpp vhdlpp vvp vpi libveriuser cadpli tgt-null tgt-stub tgt-vvp \
-          tgt-vhdl tgt-vlog95 tgt-pcb tgt-blif driver
+          tgt-vhdl tgt-vlog95 tgt-pcb tgt-blif tgt-sizer driver
 # Only run distclean for these directories.
 NOTUSED = tgt-fpga tgt-pal tgt-verilog

@@ -68,9 +68,10 @@ dllib=@DLLIB@

 # For a cross compile these defines will need to be set accordingly.
 HOSTCC = @CC@
-HOSTCFLAGS = @WARNING_FLAGS@ @CFLAGS@
+HOSTCFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CC@ @CFLAGS@

-CC = @CC@
+BUILDCC = @CC_FOR_BUILD@
+BUILDEXT = @BUILD_EXEEXT@
 CXX = @CXX@
 DLLTOOL = @DLLTOOL@
 INSTALL = @INSTALL@
@@ -90,7 +91,7 @@ INCLUDE_PATH = -I. -I$(srcdir) -I$(srcdir)/libmisc
 endif

 CPPFLAGS = @DEFS@ $(INCLUDE_PATH) @CPPFLAGS@
-CFLAGS = @WARNING_FLAGS@ @CFLAGS@
+CFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CC@ @CFLAGS@
 CXXFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CXX@ @CXXFLAGS@
 PICFLAGS = @PICFLAG@
 LDFLAGS = @rdynamic@ @LDFLAGS@
@@ -100,7 +101,7 @@ CTARGETFLAGS = @CTARGETFLAGS@
 M = LineInfo.o StringHeap.o

 TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o t-dll-analog.o
-FF = cprop.o nodangle.o synth.o synth2.o syn-rules.o
+FF = cprop.o exposenodes.o nodangle.o synth.o synth2.o syn-rules.o

 O = main.o async.o design_dump.o discipline.o dup_expr.o elaborate.o \
    elab_expr.o elaborate_analog.o elab_lval.o elab_net.o \
@@ -109,17 +110,17 @@ O = main.o async.o design_dump.o discipline.o dup_expr.o elaborate.o \
    eval_tree.o expr_synth.o functor.o lexor.o lexor_keyword.o link_const.o \
    load_module.o netlist.o netmisc.o nettypes.o net_analog.o net_assign.o \
    net_design.o netclass.o netdarray.o \
-    netenum.o netparray.o netscalar.o netstruct.o netvector.o \
+    netenum.o netparray.o netqueue.o netscalar.o netstruct.o netvector.o \
    net_event.o net_expr.o net_func.o \
    net_func_eval.o net_link.o net_modulo.o \
    net_nex_input.o net_nex_output.o net_proc.o net_scope.o net_tran.o \
    net_udp.o pad_to_width.o parse.o parse_misc.o pform.o pform_analog.o \
    pform_disciplines.o pform_dump.o pform_package.o pform_pclass.o \
    pform_class_type.o pform_string_type.o pform_struct_type.o pform_types.o \
-    symbol_search.o sync.o sys_funcs.o verinum.o verireal.o target.o \
-    Attrib.o HName.o Module.o PClass.o PDelays.o PEvent.o PExpr.o PGate.o \
-    PGenerate.o PPackage.o PScope.o PSpec.o PTask.o PUdp.o PFunction.o PWire.o \
-    Statement.o AStatement.o $M $(FF) $(TT)
+    symbol_search.o sync.o sys_funcs.o verinum.o verireal.o vpi_modules.o target.o \
+    Attrib.o HName.o Module.o PClass.o PDelays.o PEvent.o PExpr.o PFunction.o \
+    PGate.o PGenerate.o PModport.o PNamedItem.o PPackage.o PScope.o PSpec.o \
+    PTask.o PUdp.o PWire.o Statement.o AStatement.o $M $(FF) $(TT)

 all: dep config.h _pli_types.h version_tag.h ivl@EXEEXT@ version.exe iverilog-vpi.man
 	$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
@@ -127,9 +128,9 @@ all: dep config.h _pli_types.h version_tag.h ivl@EXEEXT@ version.exe iverilog-vp
 # In the windows world, the installer will need a dosify program to
 # dosify text files.
 ifeq (@MINGW32@,yes)
-all: dosify.exe
-dosify.exe: $(srcdir)/dosify.c
-	$(HOSTCC) $(HOSTCFLAGS) -o dosify.exe $(srcdir)/dosify.c
+all: dosify$(BUILDEXT)
+dosify$(BUILDEXT): $(srcdir)/dosify.c
+	$(BUILDCC) $(CFLAGS) -o dosify$(BUILDEXT) $(srcdir)/dosify.c
 endif

 # This rule rules the compiler in the trivial hello.vl program to make
@@ -137,7 +138,7 @@ endif
 check: all
 	$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
 	test -r check.conf || cp $(srcdir)/check.conf .
-	driver/iverilog -B. -BPivlpp -tcheck -ocheck.vvp $(srcdir)/examples/hello.vl
+	driver/iverilog -B. -BMvpi -BPivlpp -tcheck -ocheck.vvp $(srcdir)/examples/hello.vl
 ifeq (@WIN32@,yes)
 ifeq (@install_suffix@,)
 	vvp/vvp -M- -M./vpi ./check.vvp | grep 'Hello, World'
@@ -156,7 +157,7 @@ clean:
 	$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
 	rm -f *.o parse.cc parse.h lexor.cc
 	rm -f ivl.exp iverilog-vpi.man iverilog-vpi.pdf iverilog-vpi.ps
-	rm -f parse.output syn-rules.output dosify.exe ivl@EXEEXT@ check.vvp
+	rm -f parse.output syn-rules.output dosify$(BUILDEXT) ivl@EXEEXT@ check.vvp
 	rm -f lexor_keyword.cc libivl.a libvpi.a iverilog-vpi syn-rules.cc
 	rm -rf dep
 	rm -f version.exe
@@ -174,7 +175,10 @@ endif
 	rm -rf autom4te.cache

 cppcheck: $(O:.o=.cc) $(srcdir)/dosify.c $(srcdir)/version.c
-	cppcheck --enable=all -f --suppressions-list=$(srcdir)/cppcheck.sup \
+	cppcheck --enable=all --std=posix --std=c99 --std=c++03 -f \
+	         --suppressions-list=$(srcdir)/cppcheck.sup \
+	         -UYYPARSE_PARAM -UYYPRINT -Ushort -Usize_t -Uyyoverflow \
+	         -UYYTYPE_INT8 -UYYTYPE_INT16 -UYYTYPE_UINT8 -UYYTYPE_UINT16 \
 	         --relative-paths=$(srcdir) $(INCLUDE_PATH) $^

 cppcheck-all:
@@ -237,7 +241,7 @@ iverilog-vpi: $(srcdir)/iverilog-vpi.sh Makefile
 endif

 version.exe: $(srcdir)/version.c $(srcdir)/version_base.h version_tag.h
-	$(HOSTCC) $(HOSTCFLAGS) -o version.exe -I. -I$(srcdir) $(srcdir)/version.c
+	$(BUILDCC) $(CFLAGS) -o version.exe -I. -I$(srcdir) $(srcdir)/version.c

 %.o: %.cc config.h
 	$(CXX) $(CPPFLAGS) $(CXXFLAGS) @DEPENDENCY_FLAG@ -c $< -o $*.o
@@ -250,11 +254,9 @@ lexor.o: lexor.cc parse.h

 parse.o: parse.cc

-# Build this in two steps to avoid parallel build issues (see pr3462585)
-parse.cc: $(srcdir)/parse.y
-	$(YACC) --verbose -t -p VL -d -o $@ $<
-parse.h: parse.cc
-	mv parse.cc.h $@ 2>/dev/null || mv parse.hh $@
+# Use pattern rules to avoid parallel build issues (see pr3462585)
+parse%cc parse%h: $(srcdir)/parse%y
+	$(YACC) --verbose -t -p VL --defines=parse.h -o parse.cc $<

 syn-rules.cc: $(srcdir)/syn-rules.y
 	$(YACC) --verbose -t -p syn_ -o $@ $<
@@ -265,7 +267,7 @@ lexor.cc: $(srcdir)/lexor.lex
 lexor_keyword.o: lexor_keyword.cc parse.h

 lexor_keyword.cc: $(srcdir)/lexor_keyword.gperf
-	gperf -o -i 7 -C -k 1-4,6,9,$$ -L ANSI-C -H keyword_hash -N check_identifier -t $(srcdir)/lexor_keyword.gperf > lexor_keyword.cc || (rm -f lexor_keyword.cc ; false)
+	gperf -o -i 7 -C -k 1-4,6,9,$$ -H keyword_hash -N check_identifier -t $(srcdir)/lexor_keyword.gperf > lexor_keyword.cc || (rm -f lexor_keyword.cc ; false)

 iverilog-vpi.man: $(srcdir)/iverilog-vpi.man.in version.exe
 	./version.exe `head -1 $(srcdir)/iverilog-vpi.man.in`'\n' > $@
@@ -290,7 +292,7 @@ endif
 version_tag.h version:
 	@if $(GIT_PRESENT) && test -d $(srcdir)/.git; then \
 	    echo "Using git-describe for VERSION_TAG"; \
-	    tmp=`$(GIT) --git-dir $(srcdir)/.git describe --always --dirty \
+	    tmp=`(cd $(srcdir) && $(GIT) describe --always --dirty) \
 		   | sed -e 's;\(.*\);#define VERSION_TAG "\1";'`; \
 	    echo "$$tmp" | diff - version_tag.h > /dev/null 2>&1 || echo "$$tmp" > version_tag.h || exit 1; \
 	elif test -r $(srcdir)/version_tag.h; then \
@@ -303,66 +305,61 @@ version_tag.h version:

 ifeq (@MINGW32@,yes)
 ifeq ($(MAN),none)
-INSTALL_DOC = $(mandir)/man1/iverilog-vpi$(suffix).1
+INSTALL_DOC = installman
 else
 ifeq ($(PS2PDF),none)
-INSTALL_DOC = $(mandir)/man1/iverilog-vpi$(suffix).1
+INSTALL_DOC = installman
 else
-INSTALL_DOC = $(prefix)/iverilog-vpi$(suffix).pdf $(mandir)/man1/iverilog-vpi$(suffix).1
+INSTALL_DOC = installpdf installman
 all: dep iverilog-vpi.pdf
 endif
 endif
 INSTALL_DOCDIR = $(mandir)/man1
 else
-INSTALL_DOC = $(mandir)/man1/iverilog-vpi$(suffix).1
+INSTALL_DOC = installman
 INSTALL_DOCDIR = $(mandir)/man1
 endif

 ifeq (@MINGW32@,yes)
 WIN32_INSTALL =
 else
-WIN32_INSTALL = $(bindir)/iverilog-vpi$(suffix)
+WIN32_INSTALL = installwin32
 endif

-install: all installdirs $(libdir)/ivl$(suffix)/ivl@EXEEXT@  $(libdir)/ivl$(suffix)/include/constants.vams $(libdir)/ivl$(suffix)/include/disciplines.vams $(includedir)/ivl_target.h $(includedir)/_pli_types.h $(includedir)/sv_vpi_user.h $(includedir)/vpi_user.h $(includedir)/acc_user.h $(includedir)/veriuser.h $(WIN32_INSTALL) $(INSTALL_DOC)
+install: all installdirs installfiles
 	$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true

-$(bindir)/iverilog-vpi$(suffix): ./iverilog-vpi
+F = ./ivl@EXEEXT@ \
+	$(srcdir)/constants.vams \
+	$(srcdir)/disciplines.vams \
+	$(srcdir)/ivl_target.h \
+	./_pli_types.h \
+	$(srcdir)/sv_vpi_user.h \
+	$(srcdir)/vpi_user.h \
+	$(srcdir)/acc_user.h \
+	$(srcdir)/veriuser.h \
+	$(INSTALL_DOC) \
+	$(WIN32_INSTALL)
+
+installwin32: ./iverilog-vpi installdirs
 	$(INSTALL_SCRIPT) ./iverilog-vpi "$(DESTDIR)$(bindir)/iverilog-vpi$(suffix)"

-$(libdir)/ivl$(suffix)/ivl@EXEEXT@: ./ivl@EXEEXT@
-	$(INSTALL_PROGRAM) ./ivl@EXEEXT@ "$(DESTDIR)$(libdir)/ivl$(suffix)/ivl@EXEEXT@"
-
-$(libdir)/ivl$(suffix)/include/constants.vams: $(srcdir)/constants.vams
-	$(INSTALL_DATA) $(srcdir)/constants.vams "$(DESTDIR)$(libdir)/ivl$(suffix)/include/constants.vams"
-
-$(libdir)/ivl$(suffix)/include/disciplines.vams: $(srcdir)/disciplines.vams
-	$(INSTALL_DATA) $(srcdir)/disciplines.vams "$(DESTDIR)$(libdir)/ivl$(suffix)/include/disciplines.vams"
-
-$(includedir)/ivl_target.h: $(srcdir)/ivl_target.h
-	$(INSTALL_DATA) $(srcdir)/ivl_target.h "$(DESTDIR)$(includedir)/ivl_target.h"
-
-$(includedir)/_pli_types.h: _pli_types.h
-	$(INSTALL_DATA) $< "$(DESTDIR)$(includedir)/_pli_types.h"
-
-$(includedir)/sv_vpi_user.h: $(srcdir)/sv_vpi_user.h
-	$(INSTALL_DATA) $(srcdir)/sv_vpi_user.h "$(DESTDIR)$(includedir)/sv_vpi_user.h"
-
-$(includedir)/vpi_user.h: $(srcdir)/vpi_user.h
-	$(INSTALL_DATA) $(srcdir)/vpi_user.h "$(DESTDIR)$(includedir)/vpi_user.h"
-
-$(includedir)/acc_user.h: $(srcdir)/acc_user.h
-	$(INSTALL_DATA) $(srcdir)/acc_user.h "$(DESTDIR)$(includedir)/acc_user.h"
-
-$(includedir)/veriuser.h: $(srcdir)/veriuser.h
-	$(INSTALL_DATA) $(srcdir)/veriuser.h "$(DESTDIR)$(includedir)/veriuser.h"
-
-$(mandir)/man1/iverilog-vpi$(suffix).1: iverilog-vpi.man
+installman: iverilog-vpi.man installdirs
 	$(INSTALL_DATA) iverilog-vpi.man "$(DESTDIR)$(mandir)/man1/iverilog-vpi$(suffix).1"

-$(prefix)/iverilog-vpi$(suffix).pdf: iverilog-vpi.pdf
+installpdf: iverilog-vpi.pdf installdirs
 	$(INSTALL_DATA) iverilog-vpi.pdf "$(DESTDIR)$(prefix)/iverilog-vpi$(suffix).pdf"

+installfiles: $(F) | installdirs
+	$(INSTALL_PROGRAM) ./ivl@EXEEXT@ "$(DESTDIR)$(libdir)/ivl$(suffix)/ivl@EXEEXT@"
+	$(INSTALL_DATA) $(srcdir)/constants.vams "$(DESTDIR)$(libdir)/ivl$(suffix)/include/constants.vams"
+	$(INSTALL_DATA) $(srcdir)/disciplines.vams "$(DESTDIR)$(libdir)/ivl$(suffix)/include/disciplines.vams"
+	$(INSTALL_DATA) $(srcdir)/ivl_target.h "$(DESTDIR)$(includedir)/ivl_target.h"
+	$(INSTALL_DATA) ./_pli_types.h "$(DESTDIR)$(includedir)/_pli_types.h"
+	$(INSTALL_DATA) $(srcdir)/sv_vpi_user.h "$(DESTDIR)$(includedir)/sv_vpi_user.h"
+	$(INSTALL_DATA) $(srcdir)/vpi_user.h "$(DESTDIR)$(includedir)/vpi_user.h"
+	$(INSTALL_DATA) $(srcdir)/acc_user.h "$(DESTDIR)$(includedir)/acc_user.h"
+	$(INSTALL_DATA) $(srcdir)/veriuser.h "$(DESTDIR)$(includedir)/veriuser.h"

 installdirs: $(srcdir)/mkinstalldirs
 	$(srcdir)/mkinstalldirs "$(DESTDIR)$(bindir)" \
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2010 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -32,12 +32,9 @@ Module::Module(LexicalScope*parent, perm_string n)
 {
      library_flag = false;
      is_cell = false;
+      is_interface = false;
      program_block = false;
      uc_drive = UCD_NONE;
-      timescale_warn_done = false;
-      time_unit = 0;
-      time_precision = 0;
-      time_from_timescale = false;
 }

 Module::~Module()
@@ -94,13 +91,15 @@ perm_string Module::get_port_name(unsigned idx) const
 {

      assert(idx < ports.size());
-      if (ports[idx] == 0) {
+      if (ports[idx] == 0 || ports[idx]->name.str() == 0) {
              /* It is possible to have undeclared ports. These
                 are ports that are skipped in the declaration,
                 for example like so: module foo(x ,, y); The
                 port between x and y is unnamed and thus
-                 inaccessible to binding by name. */
-            return perm_string::literal("");
+                 inaccessible to binding by name. Port references
+		 that aren't simple or escaped identifiers are
+		 also inaccessible to binding by name. */
+            return perm_string::literal("unnamed");
      }
      return ports[idx]->name;
 }
@@ -123,3 +122,13 @@ const list<PGate*>& Module::get_gates() const
 {
      return gates_;
 }
+
+PNamedItem::SymbolType Module::symbol_type() const
+{
+      if (program_block)
+            return PROGRAM;
+      if (is_interface)
+            return INTERFACE;
+
+      return MODULE;
+}
@@ -1,7 +1,7 @@
-#ifndef __Module_H
-#define __Module_H
+#ifndef IVL_Module_H
+#define IVL_Module_H
 /*
- * Copyright (c) 1998-2010,2012 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -28,13 +28,14 @@
 # include  "HName.h"
 # include  "named.h"
 # include  "PScope.h"
-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  "netlist.h"
 # include  "pform_types.h"
 class PExpr;
 class PEIdent;
 class PGate;
 class PGenerate;
+class PModport;
 class PSpecPath;
 class PTask;
 class PFunction;
@@ -47,9 +48,13 @@ class NetScope;
 * A module is a named container and scope. A module holds a bunch of
 * semantic quantities such as wires and gates. The module is
 * therefore the handle for grasping the described circuit.
+ *
+ * SystemVerilog introduces program blocks and interfaces. These have
+ * much in common with modules, so the Module class is used to represent
+ * these containers as well.
 */

-class Module : public PScopeExtra, public LineInfo {
+class Module : public PScopeExtra, public PNamedItem {

 	/* The module ports are in general a vector of port_t
 	   objects. Each port has a name and an ordered list of
@@ -64,7 +69,7 @@ class Module : public PScopeExtra, public LineInfo {

    public:
 	/* The name passed here is the module name, not the instance
-	   name. This make must be a permallocated string. */
+	   name. This name must be a permallocated string. */
      explicit Module(LexicalScope*parent, perm_string name);
      ~Module();

@@ -81,13 +86,18 @@ class Module : public PScopeExtra, public LineInfo {
 	   restrictions and slightly modify scheduling semantics. */
      bool program_block;

+	/* This is true if the module represents a interface
+	   instead of a module/cell. Interfaces have different
+	   content restrictions and some extra allowed items. */
+      bool is_interface;
+
      enum UCDriveType { UCD_NONE, UCD_PULL0, UCD_PULL1 };
      UCDriveType uc_drive;

 	/* specparams are simpler than other parameters, in that they
 	   can have a range, but not an explicit type. The restrictions
 	   are enforced by the parser. */
-      map<perm_string,param_expr_t>specparams;
+      map<perm_string,param_expr_t*>specparams;

 	/* The module also has defparam assignments which don't create
 	   new parameters within the module, but may be used to set
@@ -111,12 +121,6 @@ class Module : public PScopeExtra, public LineInfo {

      map<perm_string,PExpr*> attributes;

-	/* These are the timescale for this module. The default is
-	   set by the `timescale directive. */
-      int time_unit, time_precision;
-      bool time_from_timescale;
-      bool timescale_warn_done;
-
 	/* The module has a list of generate schemes that appear in
 	   the module definition. These are used at elaboration time. */
      list<PGenerate*> generate_schemes;
@@ -125,6 +129,11 @@ class Module : public PScopeExtra, public LineInfo {
 	   unless they are instantiated, implicitly or explicitly. */
      std::map<perm_string,Module*> nested_modules;

+	/* An interface can contain one or more named modport lists.
+           The parser will ensure these don't appear in modules or
+           program blocks. */
+      map<perm_string,PModport*> modports;
+
      list<PSpecPath*> specify_paths;

 	// The mod_name() is the name of the module type.
@@ -151,6 +160,8 @@ class Module : public PScopeExtra, public LineInfo {

      bool elaborate_sig(Design*, NetScope*scope) const;

+      SymbolType symbol_type() const;
+
    private:
      void dump_specparams_(ostream&out, unsigned indent) const;
      list<PGate*> gates_;
@@ -160,4 +171,4 @@ class Module : public PScopeExtra, public LineInfo {
      Module& operator= (const Module&);
 };

-#endif
+#endif /* IVL_Module_H */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 Stephen Williams ([email protected])
+ * Copyright (c) 2012-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -20,7 +20,7 @@
 # include  "PClass.h"

 PClass::PClass(perm_string name, LexicalScope*parent)
-: PScopeExtra(name, parent)
+: PScopeExtra(name, parent), type(0)
 {
 }

@@ -28,3 +28,8 @@ PClass::PClass(perm_string name, LexicalScope*parent)
 PClass::~PClass()
 {
 }
+
+PNamedItem::SymbolType PClass::symbol_type() const
+{
+      return CLASS;
+}
@@ -1,7 +1,7 @@
-#ifndef __PClass_H
-#define __PClass_H
+#ifndef IVL_PClass_H
+#define IVL_PClass_H
 /*
- * Copyright (c) 2012 Stephen Williams ([email protected])
+ * Copyright (c) 2012-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -20,17 +20,19 @@
 */

 # include  "PScope.h"
-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  "StringHeap.h"
 # include  <iostream>

+class PChainConstructor;
+
 /*
 * SystemVerilog supports class declarations with their own lexical
 * scope, etc. The parser arranges for these to be created and
 * collected.
 */

-class PClass : public PScopeExtra, public LineInfo {
+class PClass : public PScopeExtra, public PNamedItem {

    public:
      explicit PClass (perm_string name, LexicalScope*parent);
@@ -38,8 +40,10 @@ class PClass : public PScopeExtra, public LineInfo {

      void dump(std::ostream&out, unsigned indent) const;

+      SymbolType symbol_type() const;
+
    public:
      class_type_t*type;
 };

-#endif
+#endif /* IVL_PClass_H */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2011 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2017 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -26,11 +26,6 @@
 # include  "verinum.h"
 # include  "netmisc.h"

-bool dly_used_no_timescale = false;
-bool dly_used_timescale = false;
-bool display_ts_dly_warning = true;
-
-
 PDelays::PDelays()
 {
      delete_flag_ = true;
@@ -80,19 +75,7 @@ static NetExpr*calculate_val(Design*des, NetScope*scope, PExpr*expr)
 {
      NetExpr*dex = elab_and_eval(des, scope, expr, -1);

-	/* Print a warning if we find default and `timescale based
-	 * delays in the design, since this is likely an error. */
-      if (scope->time_from_timescale()) dly_used_timescale = true;
-      else dly_used_no_timescale = true;
-
-      if (display_ts_dly_warning &&
-          dly_used_no_timescale && dly_used_timescale) {
-	    cerr << "warning: Found both default and "
-	            "`timescale based delays. Use" << endl;
-	    cerr << "         -Wtimescale to find the "
-	            "module(s) with no `timescale." << endl;
-	    display_ts_dly_warning = false;
-      }
+      check_for_inconsistent_delays(scope);

 	/* If the delay expression is a real constant or vector
 	   constant, then evaluate it, scale it to the local time
@@ -1,7 +1,7 @@
-#ifndef __PDelays_H
-#define __PDelays_H
+#ifndef IVL_PDelays_H
+#define IVL_PDelays_H
 /*
- * Copyright (c) 1999-2010 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2014 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -72,4 +72,4 @@ class PDelays {

 ostream& operator << (ostream&o, const PDelays&);

-#endif
+#endif /* IVL_PDelays_H */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2004 Stephen Williams ([email protected])
+ * Copyright (c) 2004-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -35,3 +35,7 @@ perm_string  PEvent::name() const
      return name_;
 }

+PNamedItem::SymbolType PEvent::symbol_type() const
+{
+      return EVENT;
+}
@@ -1,7 +1,7 @@
-#ifndef __PEvent_H
-#define __PEvent_H
+#ifndef IVL_PEvent_H
+#define IVL_PEvent_H
 /*
- * Copyright (c) 2000-2004 Stephen Williams ([email protected])
+ * Copyright (c) 2000-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,7 +19,7 @@
 *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 */

-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  "StringHeap.h"
 # include  <string>

@@ -31,7 +31,7 @@ class NetScope;
 * are declared in Verilog as ``event foo;'' The name passed to the
 * constructor is the "foo" part of the declaration.
 */
-class PEvent : public LineInfo {
+class PEvent : public PNamedItem {

    public:
 	// The name is a perm-allocated string. It is the simple name
@@ -43,6 +43,8 @@ class PEvent : public LineInfo {

      void elaborate_scope(Design*des, NetScope*scope) const;

+      SymbolType symbol_type() const;
+
    private:
      perm_string name_;

@@ -51,4 +53,4 @@ class PEvent : public LineInfo {
      PEvent& operator= (const PEvent&);
 };

-#endif
+#endif /* IVL_PEvent_H */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2012 Stephen Williams <[email protected]>
+ * Copyright (c) 1998-2020 Stephen Williams <[email protected]>
 * Copyright CERN 2013 / Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
@@ -83,17 +83,38 @@ const char* PExpr::width_mode_name(width_mode_t mode)
      switch (mode) {
          case PExpr::SIZED:
            return "sized";
+          case PExpr::UNSIZED:
+            return "unsized";
          case PExpr::EXPAND:
            return "expand";
          case PExpr::LOSSLESS:
            return "lossless";
-          case PExpr::UNSIZED:
-            return "unsized";
+          case PExpr::UPSIZE:
+            return "upsize";
          default:
            return "??";
      }
 }

+PEAssignPattern::PEAssignPattern()
+{
+}
+
+PEAssignPattern::PEAssignPattern(const list<PExpr*>&p)
+: parms_(p.size())
+{
+      size_t idx = 0;
+      for (list<PExpr*>::const_iterator cur = p.begin()
+		 ; cur != p.end() ; ++cur) {
+	    parms_[idx] = *cur;
+	    idx += 1;
+      }
+}
+
+PEAssignPattern::~PEAssignPattern()
+{
+}
+
 PEBinary::PEBinary(char op, PExpr*l, PExpr*r)
 : op_(op), left_(l), right_(r)
 {
@@ -105,9 +126,8 @@ PEBinary::~PEBinary()

 void PEBinary::declare_implicit_nets(LexicalScope*scope, NetNet::Type type)
 {
-      assert(left_ && right_);
-      left_->declare_implicit_nets(scope, type);
-      right_->declare_implicit_nets(scope, type);
+      if (left_) left_->declare_implicit_nets(scope, type);
+      if (right_) right_->declare_implicit_nets(scope, type);
 }

 bool PEBinary::has_aa_term(Design*des, NetScope*scope) const
@@ -116,7 +136,7 @@ bool PEBinary::has_aa_term(Design*des, NetScope*scope) const
      return left_->has_aa_term(des, scope) || right_->has_aa_term(des, scope);
 }

-PECastSize::PECastSize(unsigned si, PExpr*b)
+PECastSize::PECastSize(PExpr*si, PExpr*b)
 : size_(si), base_(b)
 {
 }
@@ -125,6 +145,15 @@ PECastSize::~PECastSize()
 {
 }

+PECastType::PECastType(data_type_t*t, PExpr*b)
+: target_(t), base_(b)
+{
+}
+
+PECastType::~PECastType()
+{
+}
+
 PEBComp::PEBComp(char op, PExpr*l, PExpr*r)
 : PEBinary(op, l, r)
 {
@@ -139,7 +168,7 @@ PEBComp::~PEBComp()
 PEBLogic::PEBLogic(char op, PExpr*l, PExpr*r)
 : PEBinary(op, l, r)
 {
-      assert(op == 'a' || op == 'o');
+      assert(op == 'a' || op == 'o' || op == 'q' || op == 'Q');
 }

 PEBLogic::~PEBLogic()
@@ -174,12 +203,12 @@ PEBShift::~PEBShift()
 }

 PECallFunction::PECallFunction(const pform_name_t&n, const vector<PExpr *> &parms)
-: package_(0), path_(n), parms_(parms)
+: package_(0), path_(n), parms_(parms), is_overridden_(false)
 {
 }

 PECallFunction::PECallFunction(PPackage*pkg, const pform_name_t&n, const vector<PExpr *> &parms)
-: package_(pkg), path_(n), parms_(parms)
+: package_(pkg), path_(n), parms_(parms), is_overridden_(false)
 {
 }

@@ -192,7 +221,7 @@ static pform_name_t pn_from_ps(perm_string n)
 }

 PECallFunction::PECallFunction(PPackage*pkg, perm_string n, const list<PExpr *> &parms)
-: package_(pkg), path_(pn_from_ps(n)), parms_(parms.size())
+: package_(pkg), path_(pn_from_ps(n)), parms_(parms.size()), is_overridden_(false)
 {
      int tmp_idx = 0;
      assert(parms_.size() == parms.size());
@@ -202,18 +231,18 @@ PECallFunction::PECallFunction(PPackage*pkg, perm_string n, const list<PExpr *>
 }

 PECallFunction::PECallFunction(perm_string n, const vector<PExpr*>&parms)
-: package_(0), path_(pn_from_ps(n)), parms_(parms)
+: package_(0), path_(pn_from_ps(n)), parms_(parms), is_overridden_(false)
 {
 }

 PECallFunction::PECallFunction(perm_string n)
-: package_(0), path_(pn_from_ps(n))
+: package_(0), path_(pn_from_ps(n)), is_overridden_(false)
 {
 }

 // NOTE: Anachronism. Try to work all use of svector out.
 PECallFunction::PECallFunction(const pform_name_t&n, const list<PExpr *> &parms)
-: package_(0), path_(n), parms_(parms.size())
+: package_(0), path_(n), parms_(parms.size()), is_overridden_(false)
 {
      int tmp_idx = 0;
      assert(parms_.size() == parms.size());
@@ -223,7 +252,7 @@ PECallFunction::PECallFunction(const pform_name_t&n, const list<PExpr *> &parms)
 }

 PECallFunction::PECallFunction(perm_string n, const list<PExpr*>&parms)
-: package_(0), path_(pn_from_ps(n)), parms_(parms.size())
+: package_(0), path_(pn_from_ps(n)), parms_(parms.size()), is_overridden_(false)
 {
      int tmp_idx = 0;
      assert(parms_.size() == parms.size());
@@ -417,12 +446,12 @@ bool PEIdent::has_aa_term(Design*des, NetScope*scope) const
            return false;
 }

-PENew::PENew(PExpr*size_expr)
-: size_(size_expr)
+PENewArray::PENewArray(PExpr*size_expr, PExpr*init_expr)
+: size_(size_expr), init_(init_expr)
 {
 }

-PENew::~PENew()
+PENewArray::~PENewArray()
 {
      delete size_;
 }
@@ -519,6 +548,15 @@ bool PETernary::has_aa_term(Design*des, NetScope*scope) const
           || fal_->has_aa_term(des, scope);
 }

+PETypename::PETypename(data_type_t*dt)
+: data_type_(dt)
+{
+}
+
+PETypename::~PETypename()
+{
+}
+
 PEUnary::PEUnary(char op, PExpr*ex)
 : op_(op), expr_(ex)
 {
@@ -1,7 +1,7 @@
-#ifndef __PExpr_H
-#define __PExpr_H
+#ifndef IVL_PExpr_H
+#define IVL_PExpr_H
 /*
- * Copyright (c) 1998-2013 Stephen Williams <[email protected]>
+ * Copyright (c) 1998-2019 Stephen Williams <[email protected]>
 * Copyright CERN 2013 / Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
@@ -45,9 +45,10 @@ class PPackage;
 class PExpr : public LineInfo {

    public:
-      enum width_mode_t { SIZED, EXPAND, LOSSLESS, UNSIZED };
+	// Mode values used by test_width() (see below for description).
+      enum width_mode_t { SIZED, UNSIZED, EXPAND, LOSSLESS, UPSIZE };

-        // Flag values that can be passed to elaborate_expr.
+        // Flag values that can be passed to elaborate_expr().
      static const unsigned NO_FLAGS     = 0x0;
      static const unsigned NEED_CONST   = 0x1;
      static const unsigned SYS_TASK_ARG = 0x2;
@@ -82,33 +83,42 @@ class PExpr : public LineInfo {
 	// without changing the result. This allows the expression width to
 	// be pruned when not all bits of the result are used.
 	//
-	// Normally mode should be initialised to SIZED before starting to
+	// Normally mode should be initialized to SIZED before starting to
 	// test the width of an expression. In SIZED mode the expression
 	// width will be calculated strictly according to the IEEE standard
 	// rules for expression width.
-	// If the expression contains an unsized literal, mode will be
-	// changed to LOSSLESS. In LOSSLESS mode the expression width will
-	// be calculated as the minimum width necessary to avoid arithmetic
-	// overflow or underflow.
-	// If the expression both contains an unsized literal and contains
-	// an operation that coerces a vector operand to a different type
-	// (signed <-> unsigned), mode is changed to UNSIZED. UNSIZED mode
-	// is the same as LOSSLESS, except that the final expression width
-	// will be forced to be at least integer_width. This is necessary
-	// to ensure compatibility with the IEEE standard, which requires
-	// unsized literals to be treated as having the same width as an
-	// integer. The lossless width calculation is inadequate in this
-	// case because coercing an operand to a different type means that
-	// the expression no longer obeys the normal rules of arithmetic.
 	//
-	// If mode is initialised to EXPAND instead of SIZED, the expression
+	// If the expression is found to contain an unsized literal number
+	// and gn_strict_expr_width_flag is set, mode will be changed to
+	// UNSIZED. In UNSIZED mode the expression width will be calculated
+	// exactly as in SIZED mode - the change in mode simply flags that
+	// the expression contains an unsized numbers.
+	//
+	// If the expression is found to contain an unsized literal number
+	// and gn_strict_expr_width_flag is not set, mode will be changed
+	// to LOSSLESS. In LOSSLESS mode the expression width will be
+	// calculated as the minimum width necessary to avoid arithmetic
+	// overflow or underflow.
+	//
+	// Once in LOSSLESS mode, if the expression is found to contain
+	// an operation that coerces a vector operand to a different type
+	// (signed <-> unsigned), mode will be changed to UPSIZE. UPSIZE
+	// mode is the same as LOSSLESS, except that the final expression
+	// width will be forced to be at least integer_width. This is
+	// necessary to ensure compatibility with the IEEE standard, which
+	// requires unsized numbers to be treated as having the same width
+	// as an integer. The lossless width calculation is inadequate in
+	// this case because coercing an operand to a different type means
+	// that the expression no longer obeys the normal rules of arithmetic.
+	//
+	// If mode is initialized to EXPAND instead of SIZED, the expression
 	// width will be calculated as the minimum width necessary to avoid
 	// arithmetic overflow or underflow, even if it contains no unsized
-	// literals. mode will be changed LOSSLESS or UNSIZED as described
+	// literals. mode will be changed LOSSLESS or UPSIZE as described
 	// above. This supports a non-standard mode of expression width
 	// calculation.
 	//
-	// When the final value of mode is UNSIZED, the width returned by
+	// When the final value of mode is UPSIZE, the width returned by
 	// this method is the calculated lossless width, but the width
 	// returned by a subsequent call to the expr_width method will be
 	// the final expression width.
@@ -194,6 +204,29 @@ class PExpr : public LineInfo {

 ostream& operator << (ostream&, const PExpr&);

+class PEAssignPattern : public PExpr {
+    public:
+      explicit PEAssignPattern();
+      explicit PEAssignPattern(const std::list<PExpr*>&p);
+      ~PEAssignPattern();
+
+      void dump(std::ostream&) const;
+
+      virtual unsigned test_width(Design*des, NetScope*scope, width_mode_t&mode);
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
+				     ivl_type_t type, unsigned flags) const;
+
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
+				     unsigned expr_wid,
+                                     unsigned flags) const;
+    private:
+      NetExpr* elaborate_expr_darray_(Design*des, NetScope*scope,
+				      ivl_type_t type, unsigned flags) const;
+
+    private:
+      std::vector<PExpr*>parms_;
+};
+
 class PEConcat : public PExpr {

    public:
@@ -212,6 +245,10 @@ class PEConcat : public PExpr {

      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope) const;
      virtual NetNet* elaborate_bi_net(Design*des, NetScope*scope) const;
+
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
+				     ivl_type_t type, unsigned flags) const;
+
      virtual NetExpr*elaborate_expr(Design*des, NetScope*,
 				     unsigned expr_wid,
                                     unsigned flags) const;
@@ -279,6 +316,8 @@ class PEFNumber : public PExpr {

      virtual unsigned test_width(Design*des, NetScope*scope,
 				  width_mode_t&mode);
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*,
+				     ivl_type_t type, unsigned flags) const;
      virtual NetExpr*elaborate_expr(Design*des, NetScope*,
 				     unsigned expr_wid,
                                     unsigned flags) const;
@@ -331,10 +370,17 @@ class PEIdent : public PExpr {
 	// only applies to Ident expressions.
      NetNet* elaborate_subport(Design*des, NetScope*sc) const;

+	// Elaborate the identifier allowing for unpacked arrays. This
+	// method only applies to Ident expressions because only Ident
+	// expressions can can be unpacked arrays.
+      NetNet* elaborate_unpacked_net(Design*des, NetScope*sc) const;
+
      verinum* eval_const(Design*des, NetScope*sc) const;

      virtual bool is_collapsible_net(Design*des, NetScope*scope) const;

+      const PPackage* package() const { return package_; }
+
      const pform_name_t& path() const { return path_; }

    private:
@@ -389,10 +435,10 @@ class PEIdent : public PExpr {
 				   bool need_const_idx) const;
      NetAssign_*elaborate_lval_net_class_member_(Design*, NetScope*,
 						   NetNet*,
-						   const perm_string&) const;
+						   pform_name_t) const;
      bool elaborate_lval_net_packed_member_(Design*, NetScope*,
 					     NetAssign_*,
-					     const perm_string&) const;
+					     pform_name_t member_path) const;
      bool elaborate_lval_darray_bit_(Design*, NetScope*,
 				       NetAssign_*) const;

@@ -465,25 +511,34 @@ class PEIdent : public PExpr {
 				      NetESignal*net,
 				      NetScope*found,
                                      bool need_const) const;
+      NetExpr*elaborate_expr_net_bit_last_(Design*des,
+					   NetScope*scope,
+					   NetESignal*net,
+					   NetScope*found,
+					   bool need_const) const;

      NetExpr*elaborate_expr_class_member_(Design*des,
 					   NetScope*scope,
 					   unsigned expr_wid,
 					   unsigned flags) const;

+      unsigned test_width_method_(Design*des, NetScope*scope, width_mode_t&mode);
+
+
    private:
      NetNet* elaborate_lnet_common_(Design*des, NetScope*scope,
 				     bool bidirectional_flag) const;

+
      bool eval_part_select_(Design*des, NetScope*scope, NetNet*sig,
 			     long&midx, long&lidx) const;
 };

-class PENew : public PExpr {
+class PENewArray : public PExpr {

    public:
-      explicit PENew (PExpr*s);
-      ~PENew();
+      explicit PENewArray (PExpr*s, PExpr*i);
+      ~PENewArray();

      virtual void dump(ostream&) const;
      virtual unsigned test_width(Design*des, NetScope*scope,
@@ -496,6 +551,7 @@ class PENew : public PExpr {

    private:
      PExpr*size_;
+      PExpr*init_;
 };

 class PENewClass : public PExpr {
@@ -515,10 +571,15 @@ class PENewClass : public PExpr {
 				  width_mode_t&mode);
 	// Note that class (new) expressions only appear in context
 	// that uses this form of the elaborate_expr method. In fact,
-	// the type argument is going to be a netclas_t object.
+	// the type argument is going to be a netclass_t object.
      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
 				     ivl_type_t type, unsigned flags) const;

+    private:
+      NetExpr* elaborate_expr_constructor_(Design*des, NetScope*scope,
+					   const netclass_t*ctype,
+					   NetExpr*obj, unsigned flags) const;
+
    private:
      std::vector<PExpr*>parms_;
 };
@@ -535,7 +596,7 @@ class PENewCopy : public PExpr {
 				  width_mode_t&mode);
 	// Note that class (new) expressions only appear in context
 	// that uses this form of the elaborate_expr method. In fact,
-	// the type argument is going to be a netclas_t object.
+	// the type argument is going to be a netclass_t object.
      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
 				     ivl_type_t type, unsigned flags) const;

@@ -570,7 +631,7 @@ class PENumber : public PExpr {
      virtual unsigned test_width(Design*des, NetScope*scope,
 				  width_mode_t&mode);

-      virtual NetEConst*elaborate_expr(Design*des, NetScope*scope,
+      virtual NetExpr  *elaborate_expr(Design*des, NetScope*scope,
 				       ivl_type_t type, unsigned flags) const;
      virtual NetEConst*elaborate_expr(Design*des, NetScope*,
 				       unsigned expr_wid, unsigned) const;
@@ -606,6 +667,9 @@ class PEString : public PExpr {
      virtual unsigned test_width(Design*des, NetScope*scope,
 				  width_mode_t&mode);

+      virtual NetEConst*elaborate_expr(Design*des, NetScope*scope,
+				       ivl_type_t type, unsigned flags) const;
+
      virtual NetEConst*elaborate_expr(Design*des, NetScope*,
 				       unsigned expr_wid, unsigned) const;
      verinum* eval_const(Design*, NetScope*) const;
@@ -614,6 +678,23 @@ class PEString : public PExpr {
      char*text_;
 };

+class PETypename : public PExpr {
+    public:
+      explicit PETypename(data_type_t*data_type);
+      ~PETypename();
+
+      virtual void dump(ostream&) const;
+      virtual unsigned test_width(Design*des, NetScope*scope,
+				  width_mode_t&mode);
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
+				     ivl_type_t type, unsigned flags) const;
+
+      inline data_type_t* get_type() const { return data_type_; }
+
+    private:
+      data_type_t*data_type_;
+};
+
 class PEUnary : public PExpr {

    public:
@@ -834,8 +915,10 @@ class PECallFunction : public PExpr {
      virtual bool has_aa_term(Design*des, NetScope*scope) const;

      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
-				     unsigned expr_wid,
-                                     unsigned flags) const;
+				     ivl_type_t type, unsigned flags) const;
+
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
+				     unsigned expr_wid, unsigned flags) const;

      virtual unsigned test_width(Design*des, NetScope*scope,
 				  width_mode_t&mode);
@@ -845,6 +928,9 @@ class PECallFunction : public PExpr {
      pform_name_t path_;
      std::vector<PExpr *> parms_;

+        // For system functions.
+      bool is_overridden_;
+
      bool check_call_matches_definition_(Design*des, NetScope*dscope) const;


@@ -853,7 +939,8 @@ class PECallFunction : public PExpr {
      NetExpr*elaborate_expr_pkg_(Design*des, NetScope*scope,
 				  unsigned expr_wid, unsigned flags)const;
      NetExpr*elaborate_expr_method_(Design*des, NetScope*scope,
-				     unsigned expr_wid) const;
+				     unsigned expr_wid,
+				     bool add_this_flag = false) const;
 #if 0
      NetExpr*elaborate_expr_string_method_(Design*des, NetScope*scope) const;
      NetExpr*elaborate_expr_enum_method_(Design*des, NetScope*scope,
@@ -885,7 +972,7 @@ class PECallFunction : public PExpr {
 class PECastSize  : public PExpr {

    public:
-      explicit PECastSize(unsigned expr_wid, PExpr*base);
+      explicit PECastSize(PExpr*size, PExpr*base);
      ~PECastSize();

      void dump(ostream &out) const;
@@ -898,7 +985,32 @@ class PECastSize  : public PExpr {
 				  width_mode_t&mode);

    private:
-      unsigned size_;
+      PExpr* size_;
+      PExpr* base_;
+};
+
+/*
+ * Support the SystemVerilog cast to a different type.
+ */
+class PECastType  : public PExpr {
+
+    public:
+      explicit PECastType(data_type_t*target, PExpr*base);
+      ~PECastType();
+
+      void dump(ostream &out) const;
+
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
+				     ivl_type_t type, unsigned flags) const;
+
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
+				     unsigned expr_wid, unsigned flags) const;
+
+      virtual unsigned test_width(Design*des, NetScope*scope,
+				  width_mode_t&mode);
+
+    private:
+      data_type_t* target_;
      PExpr* base_;
 };

@@ -917,4 +1029,4 @@ class PEVoid : public PExpr {
                                     unsigned flags) const;
 };

-#endif
+#endif /* IVL_PExpr_H */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2008,2010 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,7 +19,9 @@

 # include "config.h"
 # include "PTask.h"
+# include "Statement.h"
 # include <cassert>
+# include "ivl_assert.h"

 PFunction::PFunction(perm_string name, LexicalScope*parent, bool is_auto__)
 : PTaskFunc(name, parent), statement_(0)
@@ -39,7 +41,51 @@ void PFunction::set_statement(Statement*s)
      statement_ = s;
 }

-void PFunction::set_return(const data_type_t*t)
+void PFunction::push_statement_front(Statement*stmt)
+{
+        // This should not be possible.
+      ivl_assert(*this, statement_);
+
+	// Get the PBlock of the statement. If it is not a PBlock,
+	// then create one to wrap the existing statement and the new
+	// statement that we're pushing.
+      PBlock*blk = dynamic_cast<PBlock*> (statement_);
+      if (blk == 0) {
+	    PBlock*tmp = new PBlock(PBlock::BL_SEQ);
+	    tmp->set_line(*this);
+	    vector<Statement*>tmp_list(1);
+	    tmp_list[0] = statement_;
+	    tmp->set_statement(tmp_list);
+
+	    statement_ = tmp;
+	    blk = tmp;
+      }
+
+	// Now do the push.
+      blk->push_statement_front(stmt);
+}
+
+void PFunction::set_return(data_type_t*t)
 {
      return_type_ = t;
 }
+
+PChainConstructor* PFunction::extract_chain_constructor()
+{
+      PChainConstructor*res = 0;
+
+      if ((res = dynamic_cast<PChainConstructor*> (statement_))) {
+	    statement_ = new PBlock(PBlock::BL_SEQ);
+	    statement_->set_line(*this);
+
+      } else if (PBlock*blk = dynamic_cast<PBlock*>(statement_)) {
+	    res = blk->extract_chain_constructor();
+      }
+
+      return res;
+}
+
+PNamedItem::SymbolType PFunction::symbol_type() const
+{
+      return FUNCTION;
+}
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2013 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -117,6 +117,11 @@ unsigned PGate::delay_count() const
      return delay_.delay_count();
 }

+PNamedItem::SymbolType PGate::symbol_type() const
+{
+      return INSTANCE;
+}
+
 PGAssign::PGAssign(list<PExpr*>*pins)
 : PGate(perm_string(), pins)
 {
@@ -1,7 +1,7 @@
-#ifndef __PGate_H
-#define __PGate_H
+#ifndef IVL_PGate_H
+#define IVL_PGate_H
 /*
- * Copyright (c) 1998-2011 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -22,7 +22,7 @@
 # include  "svector.h"
 # include  "StringHeap.h"
 # include  "named.h"
-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  "PDelays.h"
 # include  "netlist.h"
 # include  <map>
@@ -47,7 +47,7 @@ class Module;
 * single strength pair. There is a strength of the 0 drive, and a
 * strength of the 1 drive.
 */
-class PGate : public LineInfo {
+class PGate : public PNamedItem {

    public:
      explicit PGate(perm_string name, list<PExpr*>*pins,
@@ -88,6 +88,8 @@ class PGate : public LineInfo {
      virtual void elaborate_scope(Design*des, NetScope*sc) const;
      virtual bool elaborate_sig(Design*des, NetScope*scope) const;

+      SymbolType symbol_type() const;
+
    protected:
      const vector<PExpr*>& get_pins() const { return pins_; }

@@ -124,6 +126,7 @@ class PGAssign  : public PGate {
      virtual bool elaborate_sig(Design*des, NetScope*scope) const;

    private:
+      void elaborate_unpacked_array_(Design*des, NetScope*scope, NetNet*lval) const;
 };


@@ -216,6 +219,8 @@ class PGModule  : public PGate {
 	// method to pass the range to the pform.
      void set_range(PExpr*msb, PExpr*lsb);

+      map<perm_string,PExpr*> attributes;
+
      virtual void dump(ostream&out, unsigned ind =4) const;
      virtual void elaborate(Design*, NetScope*scope) const;
      virtual void elaborate_scope(Design*des, NetScope*sc) const;
@@ -259,4 +264,4 @@ class PGModule  : public PGate {
 				 NetNet::PortType dir, bool as_signed) const;
 };

-#endif
+#endif /* IVL_PGate_H */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2011 Stephen Williams ([email protected])
+ * Copyright (c) 2006-2020 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -26,6 +26,7 @@ PGenerate::PGenerate(LexicalScope*parent, unsigned id)
 {
      direct_nested_ = false;
      scheme_type = GS_NONE;
+      local_index = false;
      loop_init = 0;
      loop_test = 0;
      loop_step = 0;
@@ -112,3 +113,8 @@ ostream& operator << (ostream&out, PGenerate::scheme_t type)
      }
      return out;
 }
+
+PNamedItem::SymbolType PGenerate::symbol_type() const
+{
+      return GENBLOCK;
+}
@@ -1,7 +1,7 @@
-#ifndef __PGenerate_H
-#define __PGenerate_H
+#ifndef IVL_PGenerate_H
+#define IVL_PGenerate_H
 /*
- * Copyright (c) 2006-2010,2012 Stephen Williams ([email protected])
+ * Copyright (c) 2006-2020 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,7 +19,7 @@
 *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 */

-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  "StringHeap.h"
 # include  "HName.h"
 # include  "PScope.h"
@@ -50,7 +50,7 @@ class PWire;
 *    The parent points to the GS_CASE that contains this item.
 *    the loop_test is compared with the parent->loop_test expression.
 */
-class PGenerate : public LineInfo, public LexicalScope {
+class PGenerate : public PNamedItem, public LexicalScope {

    public:
      explicit PGenerate(LexicalScope*parent, unsigned id_number);
@@ -71,6 +71,9 @@ class PGenerate : public LineInfo, public LexicalScope {

 	// generate loops have an index variable and three
 	// expressions: for (index = <init>; <test>; index=<step>)
+	// the index is local if it was declared in the init expression,
+	// e.g. for (genvar index = <init>; <test>; index=<step>)
+      bool local_index;
      perm_string loop_index;
      PExpr*loop_init;
      PExpr*loop_test;
@@ -107,6 +110,8 @@ class PGenerate : public LineInfo, public LexicalScope {

      void dump(ostream&out, unsigned indent) const;

+      SymbolType symbol_type() const;
+
    private:
      bool generate_scope_loop_(Design*des, NetScope*container);
      bool generate_scope_condit_(Design*des, NetScope*container, bool else_flag);
@@ -139,4 +144,4 @@ class PGenerate : public LineInfo, public LexicalScope {

 extern std::ostream& operator << (std::ostream&, PGenerate::scheme_t);

-#endif
+#endif /* IVL_PGenerate_H */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2015-2019 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,10 +17,20 @@
 *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 */

-/*
- * Things that should be statically linked by VPI modules go here.
- */
+# include "config.h"

-void __libvpi_c_dummy_function()
+# include  "PModport.h"
+
+PModport::PModport(perm_string n)
+: name_(n)
 {
 }
+
+PModport::~PModport()
+{
+}
+
+PNamedItem::SymbolType PModport::symbol_type() const
+{
+      return MODPORT;
+}
@@ -0,0 +1,54 @@
+#ifndef IVL_PModport_H
+#define IVL_PModport_H
+/*
+ * Copyright (c) 2015-2019 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+# include  "PNamedItem.h"
+# include  "PScope.h"
+# include  "StringHeap.h"
+# include  "netlist.h"
+# include  <vector>
+
+/*
+ * The PModport class represents a parsed SystemVerilog modport list.
+ */
+class PModport : public PNamedItem {
+
+    public:
+	// The name is a perm-allocated string. It is the simple name
+	// of the modport, without any scope.
+      explicit PModport(perm_string name);
+      ~PModport();
+
+      perm_string name() const { return name_; }
+
+      typedef pair <NetNet::PortType,PExpr*> simple_port_t;
+      map<perm_string,simple_port_t> simple_ports;
+
+      SymbolType symbol_type() const;
+
+    private:
+      perm_string name_;
+
+    private: // not implemented
+      PModport(const PModport&);
+      PModport& operator= (const PModport&);
+};
+
+#endif /* IVL_PModport_H */
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2019 Martin Whitaker ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+# include  "PNamedItem.h"
+# include  <ostream>
+
+PNamedItem::PNamedItem()
+{
+}
+
+PNamedItem::~PNamedItem()
+{
+}
+
+PNamedItem::SymbolType PNamedItem::symbol_type() const
+{
+      return ANY;
+}
+
+std::ostream& operator << (std::ostream&o, PNamedItem::SymbolType st)
+{
+      switch (st) {
+          case PNamedItem::ANY:
+            o << "a symbol";
+            break;
+          case PNamedItem::PARAM:
+            o << "a parameter";
+            break;
+          case PNamedItem::NET:
+            o << "a net";
+            break;
+          case PNamedItem::VAR:
+            o << "a variable";
+            break;
+          case PNamedItem::GENVAR:
+            o << "a genvar";
+            break;
+          case PNamedItem::EVENT:
+            o << "an event";
+            break;
+          case PNamedItem::TYPE:
+            o << "a type";
+            break;
+          case PNamedItem::ENUM:
+            o << "an enum type or value";
+            break;
+          case PNamedItem::CLASS:
+            o << "a class";
+            break;
+          case PNamedItem::FUNCTION:
+            o << "a function";
+            break;
+          case PNamedItem::TASK:
+            o << "a task";
+            break;
+          case PNamedItem::BLOCK:
+            o << "a named block";
+            break;
+          case PNamedItem::GENBLOCK:
+            o << "a generate block";
+            break;
+          case PNamedItem::MODPORT:
+            o << "a modport";
+            break;
+          case PNamedItem::PACKAGE:
+            o << "a package";
+            break;
+          case PNamedItem::MODULE:
+            o << "a module";
+            break;
+          case PNamedItem::PROGRAM:
+            o << "a program";
+            break;
+          case PNamedItem::INTERFACE:
+            o << "an interface";
+            break;
+          case PNamedItem::PRIMITIVE:
+            o << "a primitive";
+            break;
+          case PNamedItem::INSTANCE:
+            o << "an instance name";
+            break;
+          default:
+            break;
+      }
+      return o;
+}
+
+PGenvar::PGenvar()
+{
+}
+
+PGenvar::~PGenvar()
+{
+}
+
+PNamedItem::SymbolType PGenvar::symbol_type() const
+{
+      return GENVAR;
+}
@@ -0,0 +1,57 @@
+#ifndef IVL_PNamedItem_H
+#define IVL_PNamedItem_H
+/*
+ * Copyright (c) 2019 Martin Whitaker ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+# include  "LineInfo.h"
+
+/*
+ * The PNamedItem class is the base class for all items that can be added
+ * to a scope's local symbol map.
+ */
+class PNamedItem : virtual public LineInfo {
+
+    public:
+      enum SymbolType { ANY, PARAM, NET, VAR, GENVAR, EVENT, TYPE, ENUM,
+                        CLASS, FUNCTION, TASK, BLOCK, GENBLOCK, MODPORT,
+                        PACKAGE, MODULE, PROGRAM, INTERFACE, PRIMITIVE,
+                        INSTANCE };
+
+      explicit PNamedItem();
+      virtual ~PNamedItem();
+
+      virtual SymbolType symbol_type() const;
+};
+
+extern std::ostream& operator << (std::ostream&, PNamedItem::SymbolType);
+
+/*
+ * The PGenvar class represents a genvar. This is only used to represent
+ * genvar in a scope's local symbol map.
+ */
+class PGenvar : public PNamedItem {
+
+    public:
+      explicit PGenvar();
+      virtual ~PGenvar();
+
+      SymbolType symbol_type() const;
+};
+
+#endif /* IVL_PNamedItem_H */
@@ -1,7 +1,7 @@
-#ifndef __PPackage_H
-#define __PPackage_H
+#ifndef IVL_PPackage_H
+#define IVL_PPackage_H
 /*
- * Copyright (c) 2012 Stephen Williams ([email protected])
+ * Copyright (c) 2012-2014 Stephen Williams ([email protected])
 * Copyright CERN 2013 / Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
@@ -44,4 +44,4 @@ class PPackage : public PScopeExtra, public LineInfo {
      void pform_dump(std::ostream&out) const;
 };

-#endif
+#endif /* IVL_PPackage_H */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008,2010 Stephen Williams ([email protected])
+ * Copyright (c) 2008-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,18 +19,9 @@

 # include  "PScope.h"

-PScope::PScope(perm_string n, LexicalScope*parent)
-: LexicalScope(parent), name_(n)
-{
-}
-
-PScope::PScope(perm_string n)
-: LexicalScope(0), name_(n)
-{
-}
-
-PScope::~PScope()
+bool LexicalScope::var_init_needs_explicit_lifetime() const
 {
+      return false;
 }

 PWire* LexicalScope::wires_find(perm_string name)
@@ -42,17 +33,34 @@ PWire* LexicalScope::wires_find(perm_string name)
 	    return (*cur).second;
 }

+PNamedItem::SymbolType LexicalScope::param_expr_t::symbol_type() const
+{
+      return PARAM;
+}
+
+PScope::PScope(perm_string n, LexicalScope*parent)
+: LexicalScope(parent), name_(n)
+{
+      time_unit = 0;
+      time_precision = 0;
+      time_unit_is_default = true;
+      time_prec_is_default = true;
+}
+
+PScope::~PScope()
+{
+    for(map<perm_string, data_type_t*>::iterator it = typedefs.begin();
+        it != typedefs.end(); ++it)
+        delete it->second;
+}
+
 PScopeExtra::PScopeExtra(perm_string n, LexicalScope*parent)
 : PScope(n, parent)
 {
-}
-
-PScopeExtra::PScopeExtra(perm_string n)
-: PScope(n)
-{
+      time_unit_is_local = false;
+      time_prec_is_local = false;
 }

 PScopeExtra::~PScopeExtra()
 {
 }
-
@@ -1,7 +1,7 @@
-#ifndef __PScope_H
-#define __PScope_H
+#ifndef IVL_PScope_H
+#define IVL_PScope_H
 /*
- * Copyright (c) 2008,2010 Stephen Williams ([email protected])
+ * Copyright (c) 2008-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,11 +19,12 @@
 *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 */

-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  "StringHeap.h"
 # include  "pform_types.h"
 # include  "ivl_target.h"
 # include  <map>
+# include  <set>
 # include  <vector>

 class PEvent;
@@ -35,6 +36,7 @@ class PProcess;
 class PClass;
 class PTask;
 class PWire;
+class Statement;

 class Design;
 class NetScope;
@@ -51,10 +53,32 @@ class NetScope;
 class LexicalScope {

    public:
-      explicit LexicalScope(LexicalScope*parent) : parent_(parent) { }
+      enum lifetime_t { INHERITED, STATIC, AUTOMATIC };
+
+      explicit LexicalScope(LexicalScope*parent) : default_lifetime(INHERITED), parent_(parent) { }
 	// A virtual destructor is so that dynamic_cast can work.
      virtual ~LexicalScope() { }

+      lifetime_t default_lifetime;
+
+	// Symbols that are defined or declared in this scope.
+      std::map<perm_string,PNamedItem*>local_symbols;
+
+	// Symbols that are explicitly imported. Bind the imported name
+	// to the package from which the name is imported.
+      std::map<perm_string,PPackage*>explicit_imports;
+
+	// Packages that are wildcard imported. When identifiers from
+	// these packages are referenced, they will be added to the
+	// explicit imports (IEEE 1800-2012 26.3).
+      std::set<PPackage*>potential_imports;
+
+	// A task or function call may reference a task or function defined
+	// later in the scope. So here we stash the potential imports for
+	// task and function calls. They will be added to the explicit
+	// imports if we don't find a local definition.
+      std::map<perm_string,PPackage*>possible_imports;
+
      struct range_t {
 	      // True if this is an exclude
 	    bool exclude_flag;
@@ -73,7 +97,7 @@ class LexicalScope {
 	/* The scope has parameters that are evaluated when the scope
 	   is elaborated. During parsing, I put the parameters into
 	   this map. */
-      struct param_expr_t : public LineInfo {
+      struct param_expr_t : public PNamedItem {
 	    param_expr_t() : type(IVL_VT_NO_TYPE), msb(0), lsb(0), signed_flag(false), expr(0), range(0) { }
 	      // Type information
 	    ivl_variable_type_t type;
@@ -84,9 +108,11 @@ class LexicalScope {
 	    PExpr*expr;
 	      // If there are range constraints, list them here
 	    range_t*range;
+
+	    SymbolType symbol_type() const;
      };
-      map<perm_string,param_expr_t>parameters;
-      map<perm_string,param_expr_t>localparams;
+      map<perm_string,param_expr_t*>parameters;
+      map<perm_string,param_expr_t*>localparams;

 	// Defined types in the scope.
      map<perm_string,data_type_t*>typedefs;
@@ -94,10 +120,6 @@ class LexicalScope {
 	// Named events in the scope.
      map<perm_string,PEvent*>events;

-	// Symbols that are imported. Bind the imported name to the
-	// package from which the name is imported.
-      std::map<perm_string,PPackage*>imports;
-
 	// Nets and variables (wires) in the scope
      map<perm_string,PWire*>wires;
      PWire* wires_find(perm_string name);
@@ -107,15 +129,20 @@ class LexicalScope {
        // creating implicit nets.
      map<perm_string,LineInfo*> genvars;

+	// Variable initializations in this scope
+      vector<Statement*> var_inits;
+
 	// Behaviors (processes) in this scope
      list<PProcess*> behaviors;
      list<AProcess*> analog_behaviors;

 	// Enumeration sets.
-      list<enum_type_t*> enum_sets;
+      std::set<enum_type_t*> enum_sets;

      LexicalScope* parent_scope() const { return parent_; }

+      virtual bool var_init_needs_explicit_lifetime() const;
+
    protected:
      void dump_typedefs_(ostream&out, unsigned indent) const;

@@ -129,6 +156,10 @@ class LexicalScope {

      void dump_wires_(ostream&out, unsigned indent) const;

+      void dump_var_inits_(ostream&out, unsigned indent) const;
+
+      bool elaborate_var_inits_(Design*des, NetScope*scope) const;
+
    private:
      LexicalScope*parent_;
 };
@@ -144,12 +175,24 @@ class PScope : public LexicalScope {
 	// modules do not nest in Verilog, the parent must be nil for
 	// modules. Scopes for tasks and functions point to their
 	// containing module.
-      PScope(perm_string name, LexicalScope*parent);
-      PScope(perm_string name);
+      explicit PScope(perm_string name, LexicalScope*parent =0);
      virtual ~PScope();

      perm_string pscope_name() const { return name_; }

+	/* These are the timescale for this scope. The value is
+	   set by the `timescale directive or, in SystemVerilog,
+	   by timeunit and timeprecision statements. */
+      int time_unit, time_precision;
+
+	/* Flags used to support warnings about timescales. */
+      bool time_unit_is_default;
+      bool time_prec_is_default;
+
+      bool has_explicit_timescale() const {
+	     return !(time_unit_is_default || time_prec_is_default);
+	   }
+
    protected:
      bool elaborate_sig_wires_(Design*des, NetScope*scope) const;

@@ -167,23 +210,26 @@ class PScope : public LexicalScope {
 class PScopeExtra : public PScope {

    public:
-      PScopeExtra(perm_string, LexicalScope*parent);
-      PScopeExtra(perm_string);
+      explicit PScopeExtra(perm_string, LexicalScope*parent =0);
      ~PScopeExtra();

 	/* Task definitions within this module */
      std::map<perm_string,PTask*> tasks;
      std::map<perm_string,PFunction*> funcs;
-	/* class definitions within this module. */
+	/* Class definitions within this module. */
      std::map<perm_string,PClass*> classes;
 	/* This is the lexical order of the classes, and is used by
 	   elaboration to choose an elaboration order. */
      std::vector<PClass*> classes_lexical;

+	/* Flags used to support warnings about timescales. */
+      bool time_unit_is_local;
+      bool time_prec_is_local;
+
    protected:
      void dump_classes_(ostream&out, unsigned indent) const;
      void dump_tasks_(ostream&out, unsigned indent) const;
      void dump_funcs_(ostream&out, unsigned indent) const;
 };

-#endif
+#endif /* IVL_PScope_H */
@@ -1,7 +1,7 @@
-#ifndef __PSpec_H
-#define __PSpec_H
+#ifndef IVL_PSpec_H
+#define IVL_PSpec_H
 /*
- * Copyright (c) 2006-2011 Stephen Williams <[email protected]>
+ * Copyright (c) 2006-2014 Stephen Williams <[email protected]>
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -84,4 +84,4 @@ class PSpecPath  : public LineInfo {
      std::vector<class PExpr*>delays;
 };

-#endif
+#endif /* IVL_PSpec_H */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2008,2010 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -30,7 +30,12 @@ PTaskFunc::~PTaskFunc()
 {
 }

-void PTaskFunc::set_ports(vector<PWire*>*p)
+bool PTaskFunc::var_init_needs_explicit_lifetime() const
+{
+      return default_lifetime == STATIC;
+}
+
+void PTaskFunc::set_ports(vector<pform_tf_port_t>*p)
 {
      assert(ports_ == 0);
      ports_ = p;
@@ -41,16 +46,16 @@ void PTaskFunc::set_this(class_type_t*type, PWire*this_wire)
      assert(this_type_ == 0);
      this_type_ = type;

-	// Push a synthetis argument that is the "this" value.
+	// Push a synthesis argument that is the "this" value.
      if (ports_==0)
-	    ports_ = new vector<PWire*>;
+	    ports_ = new vector<pform_tf_port_t>;

      size_t use_size = ports_->size();
      ports_->resize(use_size + 1);
      for (size_t idx = use_size ; idx > 0 ; idx -= 1)
 	    ports_->at(idx) = ports_->at(idx-1);

-      ports_->at(0) = this_wire;
+      ports_->at(0) = pform_tf_port_t(this_wire);
 }

 PTask::PTask(perm_string name, LexicalScope*parent, bool is_auto__)
@@ -68,3 +73,8 @@ void PTask::set_statement(Statement*s)
      assert(statement_ == 0);
      statement_ = s;
 }
+
+PNamedItem::SymbolType PTask::symbol_type() const
+{
+      return TASK;
+}
@@ -1,7 +1,7 @@
-#ifndef __PTask_H
-#define __PTask_H
+#ifndef IVL_PTask_H
+#define IVL_PTask_H
 /*
- * Copyright (c) 1999-2008,2010,2012 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,27 +19,31 @@
 *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 */

-# include  "LineInfo.h"
 # include  "PScope.h"
+# include  "PNamedItem.h"
 # include  "StringHeap.h"
 # include  <string>
 # include  <vector>
 # include  <list>
 class Design;
+class NetExpr;
 class NetNet;
 class NetScope;
+class PChainConstructor;
 class PWire;
 class Statement;
 class PExpr;


-class PTaskFunc : public PScope, public LineInfo {
+class PTaskFunc : public PScope, public PNamedItem {

    public:
      PTaskFunc(perm_string name, LexicalScope*parent);
      ~PTaskFunc();

-      void set_ports(std::vector<PWire *>*p);
+      bool var_init_needs_explicit_lifetime() const;
+
+      void set_ports(std::vector<pform_tf_port_t>*p);

      void set_this(class_type_t*use_type, PWire*this_wire);

@@ -47,15 +51,25 @@ class PTaskFunc : public PScope, public LineInfo {
 	// to the class type.
      inline class_type_t* method_of() const { return this_type_; }

+
+      virtual void elaborate_sig(Design*des, NetScope*scope) const =0;
+      virtual void elaborate(Design*des, NetScope*scope) const =0;
+
+      virtual void dump(std::ostream&, unsigned) const =0;
+
    protected:
+	// Elaborate the ports list. Write into the ports vector the
+	// NetNet pointers for the ports, and write into the pdefs the
+	// default value expressions, if any.
      void elaborate_sig_ports_(Design*des, NetScope*scope,
-				std::vector<NetNet*>&ports) const;
+				std::vector<NetNet*>&ports,
+				std::vector<NetExpr*>&pdefs) const;

      void dump_ports_(std::ostream&out, unsigned ind) const;

    private:
      class_type_t*this_type_;
-      std::vector<PWire*>*ports_;
+      std::vector<pform_tf_port_t>*ports_;
 };

 /*
@@ -85,6 +99,8 @@ class PTask  : public PTaskFunc {

      void dump(ostream&, unsigned) const;

+      SymbolType symbol_type() const;
+
    private:
      Statement*statement_;
      bool is_auto_;
@@ -108,10 +124,20 @@ class PFunction : public PTaskFunc {
      ~PFunction();

      void set_statement(Statement *s);
-      void set_return(const data_type_t*t);
+      void set_return(data_type_t*t);

      inline Statement* get_statement() { return statement_; }

+	// Push this statement to the front of the existing
+	// definition. If the statement is a simple statement, make a
+	// block to contain the statements.
+      void push_statement_front(Statement*stmt);
+
+	// This is only used if this function is a constructor. In
+	// that case, this method looks for a PChainConstructor in the
+	// statement and extracts it if found.
+      PChainConstructor*extract_chain_constructor();
+
      void elaborate_scope(Design*des, NetScope*scope) const;

 	/* elaborate the ports and return value. */
@@ -124,10 +150,12 @@ class PFunction : public PTaskFunc {

      void dump(ostream&, unsigned) const;

+      SymbolType symbol_type() const;
+
    private:
-      const data_type_t* return_type_;
+      data_type_t* return_type_;
      Statement *statement_;
      bool is_auto_;
 };

-#endif
+#endif /* IVL_PTask_H */
@@ -1,7 +1,7 @@
-#ifndef __PUdp_H
-#define __PUdp_H
+#ifndef IVL_PUdp_H
+#define IVL_PUdp_H
 /*
- * Copyright (c) 1998-2011 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2014 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -76,4 +76,4 @@ class PUdp : public LineInfo {
      PUdp& operator= (const PUdp&);
 };

-#endif
+#endif /* IVL_PUdp_H */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2012 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -29,7 +29,7 @@ PWire::PWire(perm_string n,
 : name_(n), type_(t), port_type_(pt), data_type_(dt),
  signed_(false), isint_(false),
  port_set_(false), net_set_(false), is_scalar_(false),
-  error_cnt_(0), set_data_type_(0),
+  error_cnt_(0), uarray_type_(0), set_data_type_(0),
  discipline_(0)
 {
      if (t == NetNet::INTEGER) {
@@ -67,6 +67,7 @@ bool PWire::set_wire_type(NetNet::Type t)
 		  isint_ = true;
 		  return true;
 	    }
+	    if (t == NetNet::IMPLICIT_REG) return true;
 	    return false;
 	  case NetNet::REG:
 	    if (t == NetNet::INTEGER) {
@@ -282,3 +283,15 @@ ivl_discipline_t PWire::get_discipline(void) const
 {
      return discipline_;
 }
+
+PNamedItem::SymbolType PWire::symbol_type() const
+{
+      switch (type_) {
+          case NetNet::IMPLICIT_REG:
+          case NetNet::INTEGER:
+          case NetNet::REG:
+            return VAR;
+          default:
+            return NET;
+    }
+}
@@ -1,7 +1,7 @@
-#ifndef __PWire_H
-#define __PWire_H
+#ifndef IVL_PWire_H
+#define IVL_PWire_H
 /*
- * Copyright (c) 1998-2009,2012 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -20,7 +20,7 @@
 */

 # include  "netlist.h"
-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  <list>
 # include  <map>
 # include  "StringHeap.h"
@@ -51,7 +51,7 @@ enum PWSRType {SR_PORT, SR_NET, SR_BOTH};
 * from that perspective, sub-scopes within the module are a part of
 * the wire name.
 */
-class PWire : public LineInfo {
+class PWire : public PNamedItem {

    public:
      PWire(perm_string name,
@@ -80,6 +80,7 @@ class PWire : public LineInfo {
      void set_range(const std::list<pform_range_t>&ranges, PWSRType type);

      void set_unpacked_idx(const std::list<pform_range_t>&ranges);
+      void set_uarray_type(uarray_type_t*type) { uarray_type_ = type; }

      void set_data_type(data_type_t*type);

@@ -93,6 +94,8 @@ class PWire : public LineInfo {

      NetNet* elaborate_sig(Design*, NetScope*scope) const;

+      SymbolType symbol_type() const;
+
    private:
      perm_string name_;
      NetNet::Type type_;
@@ -117,6 +120,7 @@ class PWire : public LineInfo {
 	// If this wire is actually a memory, these indices will give
 	// me the size and address ranges of the memory.
      std::list<pform_range_t>unpacked_;
+      uarray_type_t*uarray_type_;

 	// This is the complex type of the wire. the data_type_ may
 	// modify how this is interpreted.
@@ -129,4 +133,4 @@ class PWire : public LineInfo {
      PWire& operator= (const PWire&);
 };

-#endif
+#endif /* IVL_PWire_H */
@@ -1,14 +1,14 @@
 		THE ICARUS VERILOG COMPILATION SYSTEM
-		Copyright 2000-2004 Stephen Williams
+		Copyright 2000-2019 Stephen Williams


 1.0 What is ICARUS Verilog?

 Icarus Verilog is intended to compile ALL of the Verilog HDL as
 described in the IEEE-1364 standard. Of course, it's not quite there
-yet. It does currently handle a mix of structural and behavioral
+yet. It does currently handle a mix of structural and behavioural
 constructs. For a view of the current state of Icarus Verilog, see its
-home page at <http://www.icarus.com/eda/verilog>.
+home page at <http://iverilog.icarus.com/>.

 Icarus Verilog is not aimed at being a simulator in the traditional
 sense, but a compiler that generates code employed by back-end
@@ -20,13 +20,13 @@ tools.

 2.0 Building/Installing Icarus Verilog From Source

-If you are starting from source, the build process is designed to be
+If you are starting from the source, the build process is designed to be
 as simple as practical. Someone basically familiar with the target
 system and C/C++ compilation should be able to build the source
 distribution with little effort. Some actual programming skills are
 not required, but helpful in case of problems.

-If you are building for Windows, see the mingw.txt file.
+If you are building on Windows, see the mingw.txt file.

 2.1 Compile Time Prerequisites

@@ -46,8 +46,12 @@ on a UNIX-like system:
 	  to work. MSVC++ 5 and 6 are known to definitely *not* work.

 	- bison and flex
+          OSX note: bison 2.3 shipped with MacOS including Catalina generates
+          broken code, but bison 3+ works. We recommend using the Fink
+          project version of bison and flex (finkproject.org), brew version
+          works fine either.

-	- gperf 2.7
+	- gperf 3.0 or later
 	  The lexical analyzer doesn't recognize keywords directly,
 	  but instead matches symbols and looks them up in a hash
 	  table in order to get the proper lexical code. The gperf
@@ -56,18 +60,18 @@ on a UNIX-like system:
 	  A version problem with this program is the most common cause
 	  of difficulty. See the Icarus Verilog FAQ.

-	- readline 4.2
+	- readline 4.2 or later
 	  On Linux systems, this usually means the readline-devel
 	  rpm. In any case, it is the development headers of readline
 	  that are needed.

 	- termcap
-	  The readline library in turn uses termcap.
+	  The readline library, in turn, uses termcap.

 If you are building from git, you will also need software to generate
 the configure scripts.

-	- autoconf 2.53
+	- autoconf 2.53 or later
 	  This generates configure scripts from configure.in. The 2.53
 	  or later versions are known to work, autoconf 2.13 is
 	  reported to *not* work.
@@ -75,15 +79,21 @@ the configure scripts.
 2.2 Compilation

 Unpack the tar-ball and cd into the verilog-######### directory
-(presumably that is how you got to this README) and compile the source
+(presumably, that is how you got to this README) and compile the source
 with the commands:

  ./configure
  make

+If you are building from git, you have to run the command below before
+compiling the source. This will generate the "configure" file, which is
+automatically done when building from tarball.
+
+  sh autoconf.sh
+
 Normally, this command automatically figures out everything it needs
 to know. It generally works pretty well. There are a few flags to the
-configure script that modify its behavior:
+configure script that modify its behaviour:

 	--prefix=<root>
 	    The default is /usr/local, which causes the tool suite to
@@ -106,6 +116,12 @@ configure script that modify its behavior:
 	    with the same prefix but different suffix are guaranteed
 	    to not interfere with each other.

+	--host=<host-type>
+	    Compile iverilog for a different platform. You can use:
+                x64_64-w64-mingw32 for building 64-bit Windows executables
+                i686-w64-mingw32 for building 32-bit Windows executables
+            Both options require installing the required mingw-w64 packages.
+
 2.3 (Optional) Testing

 To run a simple test before installation, execute
@@ -155,7 +171,7 @@ output of the parse is a list of Module objects in "pform". The pform
 step. There may be dangling references, and it is not yet clear which
 module is the root.

-One can see a human readable version of the final pform by using the
+One can see a human-readable version of the final pform by using the
 ``-P <path>'' flag to the ``ivl'' subcommand. This will cause ivl
 to dump the pform into the file named <path>. (Note that this is not
 normally done, unless debugging the ``ivl'' subcommand.)
@@ -167,17 +183,17 @@ This phase takes the pform and generates a netlist. The driver selects
 resolves references and expands the instantiations to form the design
 netlist. (See netlist.txt.) Final semantic checks are performed during
 elaboration, and some simple optimizations are performed. The netlist
-includes all the behavioral descriptions, as well as gates and wires.
+includes all the behavioural descriptions, as well as gates and wires.

 The elaborate() function performs the elaboration.

-One can see a human readable version of the final, elaborated and
+One can see a human-readable version of the final, elaborated and
 optimized netlist by using the ``-N <path>'' flag to the compiler. If
 elaboration succeeds, the final netlist (i.e., after optimizations but
 before code generation) will be dumped into the file named <path>.

-Elaboration is actually performed in two steps: scopes and parameters
-first, followed by the structural and behavioral elaboration.
+Elaboration is performed in two steps: scopes and parameters
+first, followed by the structural and behavioural elaboration.

 3.3.1 Scope Elaboration

@@ -186,7 +202,7 @@ tree of NetScope objects is built up and placed in the Design object,
 with the root module represented by the root NetScope object. The
 elab_scope.cc file contains most of the code for handling this phase.

-The tail of the elaborate_scope behavior (after the pform is
+The tail of the elaborate_scope behaviour (after the pform is
 traversed) includes a scan of the NetScope tree to locate defparam
 assignments that were collected during scope elaboration. This is when
 the defparam overrides are applied to the parameters.
@@ -195,14 +211,14 @@ the defparam overrides are applied to the parameters.

 After the scopes and parameters are generated and the NetScope tree
 fully formed, the elaboration runs through the pform again, this time
-generating the structural and behavioral netlist. Parameters are
+generating the structural and behavioural netlist. Parameters are
 elaborated and evaluated by now so all the constants of code
 generation are now known locally, so the netlist can be generated by
 simply passing through the pform.

 3.4 Optimization

-This is actually a collection of processing steps that perform
+This is a collection of processing steps that perform
 optimizations that do not depend on the target technology. Examples of
 some useful transformations are

@@ -220,7 +236,7 @@ generator (see target.h). This may require transforming the
 design to suit the technology.

 The emit() method of the Design class performs this step. It runs
-through the design elements, calling target functions as need arises
+through the design elements, calling target functions as the need arises
 to generate actual output.

 The user selects the target code generator with the -t flag on the
@@ -228,7 +244,7 @@ command line.

 3.6 ATTRIBUTES

-    NOTE: The $attribute syntax will soon be deprecated in favor of the
+    NOTE: The $attribute syntax will soon be deprecated in favour of the
    Verilog-2001 attribute syntax, which is cleaner and standardized.

 The parser accepts, as an extension to Verilog, the $attribute module
@@ -251,7 +267,7 @@ Attributes can also be applied to gate types. When this is done, the
 attribute is given to every instantiation of the primitive. The syntax
 for the attribute statement is the same, except that the <identifier>
 names a primitive earlier in the compilation unit and the statement is
-placed in global scope, instead of within a module. The semicolon is
+placed in the global scope, instead of within a module. The semicolon is
 not part of a type attribute.

 Note that attributes are also occasionally used for communication
@@ -310,7 +326,7 @@ by the compiler. See the iverilog(1) man page.

 Icarus Verilog is in development - as such it still only supports a
 (growing) subset of Verilog.  Below is a description of some of the
-currently unsupported Verilog features. This list is not exhaustive,
+currently unsupported Verilog features. This list is not exhaustive
 and does not account for errors in the compiler. See the Icarus
 Verilog web page for the current state of support for Verilog, and in
 particular, browse the bug report database for reported unsupported
@@ -339,7 +355,7 @@ constructs.
 5.1 Nonstandard Constructs or Behaviors

 Icarus Verilog includes some features that are not part of the
-IEEE1364 standard, but have well defined meaning, and also sometimes
+IEEE1364 standard, but have well-defined meaning, and also sometimes
 gives nonstandard (but extended) meanings to some features of the
 language that are defined. See the "extensions.txt" documentation for
 more details.
@@ -356,7 +372,7 @@ more details.
 	function is undefined if the argument doesn't have a
 	self-determined size.

-	The $sizeof function is deprecated in favor of $bits, which is
+	The $sizeof function is deprecated in favour of $bits, which is
 	the same thing, but included in the SystemVerilog definition.

    $simtime
@@ -382,8 +398,8 @@ more details.

    Builtin system functions

-	Certain of the system functions have well defined meanings, so
-	can theoretically be evaluated at compile time, instead of
+	Certain of the system functions have well-defined meanings, so
+	can theoretically be evaluated at compile-time, instead of
 	using runtime VPI code. Doing so means that VPI cannot
 	override the definitions of functions handled in this
 	manner. On the other hand, this makes them synthesizable, and
@@ -402,8 +418,8 @@ more details.

 	Icarus Verilog does preprocess modules that are loaded from
 	libraries via the -y mechanism. However, the only macros
-	defined during compilation of that file are those that it
-	defines itself (or includes) or that are defined on the
+	defined during the compilation of that file are those that it
+	defines itself (or includes) or that are defined in the
 	command line or command file.

 	Specifically, macros defined in the non-library source files
@@ -420,7 +436,7 @@ more details.
 	Standard Verilog does not allow width fields in the %t formats
 	of display strings. For example, this is illegal:

-		$display("Time is %0t", %time);
+		$display("Time is %0t", $time);

 	Standard Verilog instead relies on the $timeformat to
 	completely specify the format.
@@ -444,7 +460,7 @@ more details.

    time 0 race resolution.

-	Combinational logic is routinely modeled using always
+	Combinational logic is routinely modelled using always
 	blocks. However, this can lead to race conditions if the
 	inputs to the combinational block are initialized in initial
 	statements. Icarus Verilog slightly modifies time 0 scheduling
@@ -455,7 +471,7 @@ more details.

    Nets with Types

-	Icarus Verilog support an extension syntax that allows nets
+	Icarus Verilog supports an extended syntax that allows nets
 	and regs to be explicitly typed. The currently supported types
 	are logic, bool and real. This implies that "logic" and "bool"
 	are new keywords. Typical syntax is:
@@ -472,6 +488,6 @@ more details.
 Except where otherwise noted, Icarus Verilog, ivl and ivlpp are
 Copyright Stephen Williams. The proper notices are in the head of each
 file. However, I have early on received aid in the form of fixes,
-Verilog guidance, and especially testing from many people. Testers in
-particular include a larger community of people interested in a GPL
+Verilog guidance, and especially testing from many people. Testers, in
+particular, include a larger community of people interested in a GPL
 Verilog for Linux.
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2008,2010,2012-2013 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2019 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -115,6 +115,26 @@ PBlock::~PBlock()
 	    delete list_[idx];
 }

+bool PBlock::var_init_needs_explicit_lifetime() const
+{
+      return default_lifetime == STATIC;
+}
+
+PChainConstructor* PBlock::extract_chain_constructor()
+{
+      if (list_.empty())
+	    return 0;
+
+      if (PChainConstructor*res = dynamic_cast<PChainConstructor*> (list_[0])) {
+	    for (size_t idx = 0 ; idx < list_.size()-1 ; idx += 1)
+		  list_[idx] = list_[idx+1];
+	    list_.resize(list_.size()-1);
+	    return res;
+      }
+
+      return 0;
+}
+
 void PBlock::set_join_type(PBlock::BL_TYPE type)
 {
      assert(bl_type_ == BL_PAR);
@@ -138,6 +158,11 @@ void PBlock::push_statement_front(Statement*that)
      list_[0] = that;
 }

+PNamedItem::SymbolType PBlock::symbol_type() const
+{
+      return BLOCK;
+}
+
 PCallTask::PCallTask(const pform_name_t&n, const list<PExpr*>&p)
 : package_(0), path_(n), parms_(p.size())
 {
@@ -181,8 +206,8 @@ const pform_name_t& PCallTask::path() const
      return path_;
 }

-PCase::PCase(NetCase::TYPE t, PExpr*ex, svector<PCase::Item*>*l)
-: type_(t), expr_(ex), items_(l)
+PCase::PCase(ivl_case_quality_t q, NetCase::TYPE t, PExpr*ex, svector<PCase::Item*>*l)
+: quality_(q), type_(t), expr_(ex), items_(l)
 {
 }

@@ -206,6 +231,21 @@ PCAssign::~PCAssign()
      delete expr_;
 }

+PChainConstructor::PChainConstructor(const list<PExpr*>&parms)
+: parms_(parms.size())
+{
+      list<PExpr*>::const_iterator cur = parms.begin();
+      for (size_t idx = 0 ; idx < parms_.size() ; idx += 1) {
+	    parms_[idx] = *cur;
+	    ++cur;
+      }
+      assert(cur == parms.end());
+}
+
+PChainConstructor::~PChainConstructor()
+{
+}
+
 PCondit::PCondit(PExpr*ex, Statement*i, Statement*e)
 : expr_(ex), if_(i), else_(e)
 {
@@ -247,21 +287,32 @@ PDisable::~PDisable()
 {
 }

+PDoWhile::PDoWhile(PExpr*ex, Statement*st)
+: cond_(ex), statement_(st)
+{
+}
+
+PDoWhile::~PDoWhile()
+{
+      delete cond_;
+      delete statement_;
+}
+
 PEventStatement::PEventStatement(const svector<PEEvent*>&ee)
-: expr_(ee), statement_(0)
+: expr_(ee), statement_(0), always_sens_(false)
 {
      assert(expr_.count() > 0);
 }


 PEventStatement::PEventStatement(PEEvent*ee)
-: expr_(1), statement_(0)
+: expr_(1), statement_(0), always_sens_(false)
 {
      expr_[0] = ee;
 }

-PEventStatement::PEventStatement(void)
-: statement_(0)
+PEventStatement::PEventStatement(bool always_sens)
+: statement_(0), always_sens_(always_sens)
 {
 }

@@ -295,6 +346,20 @@ PForce::~PForce()
      delete expr_;
 }

+PForeach::PForeach(perm_string av, const list<perm_string>&ix, Statement*s)
+: array_var_(av), index_vars_(ix.size()), statement_(s)
+{
+      size_t idx = 0;
+      for (list<perm_string>::const_iterator cur = ix.begin()
+		 ; cur != ix.end() ; ++cur)
+	    index_vars_[idx++] = *cur;
+}
+
+PForeach::~PForeach()
+{
+      delete statement_;
+}
+
 PForever::PForever(Statement*s)
 : statement_(s)
 {
@@ -351,8 +416,8 @@ PReturn::~PReturn()
      delete expr_;
 }

-PTrigger::PTrigger(const pform_name_t&e)
-: event_(e)
+PTrigger::PTrigger(PPackage*pkg, const pform_name_t&e)
+: package_(pkg), event_(e)
 {
 }

@@ -360,8 +425,8 @@ PTrigger::~PTrigger()
 {
 }

-PWhile::PWhile(PExpr*e1, Statement*st)
-: cond_(e1), statement_(st)
+PWhile::PWhile(PExpr*ex, Statement*st)
+: cond_(ex), statement_(st)
 {
 }

@@ -1,7 +1,7 @@
-#ifndef __Statement_H
-#define __Statement_H
+#ifndef IVL_Statement_H
+#define IVL_Statement_H
 /*
- * Copyright (c) 1998-2013 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2020 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -31,6 +31,7 @@
 # include  "HName.h"
 # include  "LineInfo.h"
 class PExpr;
+class PChainConstructor;
 class PPackage;
 class Statement;
 class PEventStatement;
@@ -74,7 +75,7 @@ class PProcess : public LineInfo {
 * fact, the Statement class is abstract and represents all the
 * possible kinds of statements that exist in Verilog.
 */
-class Statement : public LineInfo {
+class Statement : virtual public LineInfo {

    public:
      Statement() { }
@@ -105,8 +106,10 @@ class PAssign_  : public Statement {

    protected:
      NetAssign_* elaborate_lval(Design*, NetScope*scope) const;
-      NetExpr* elaborate_rval_(Design*, NetScope*, unsigned lv_width,
-			       ivl_variable_type_t type) const;
+      NetExpr* elaborate_rval_(Design*, NetScope*, ivl_type_t lv_net_type,
+			       ivl_variable_type_t lv_type,
+			       unsigned lv_width,
+			       bool force_unsigned =false) const;
      NetExpr* elaborate_rval_(Design*, NetScope*, ivl_type_t ntype) const;

      NetExpr* elaborate_rval_obj_(Design*, NetScope*,
@@ -167,7 +170,7 @@ class PAssignNB  : public PAssign_ {
 * statements before constructing this object, so it knows a priori
 * what is contained.
 */
-class PBlock  : public PScope, public Statement {
+class PBlock  : public PScope, public Statement, public PNamedItem {

    public:
      enum BL_TYPE { BL_SEQ, BL_PAR, BL_JOIN_NONE, BL_JOIN_ANY };
@@ -180,6 +183,13 @@ class PBlock  : public PScope, public Statement {

      BL_TYPE bl_type() const { return bl_type_; }

+      bool var_init_needs_explicit_lifetime() const;
+
+	// This is only used if this block is the statement list for a
+	// constructor. We look for a PChainConstructor as the first
+	// statement, and if it is there, extract it.
+      PChainConstructor*extract_chain_constructor();
+
 	// If the bl_type() is BL_PAR, it is possible to replace it
 	// with JOIN_NONE or JOIN_ANY. This is to help the parser.
      void set_join_type(BL_TYPE);
@@ -195,6 +205,8 @@ class PBlock  : public PScope, public Statement {
      virtual void elaborate_scope(Design*des, NetScope*scope) const;
      virtual void elaborate_sig(Design*des, NetScope*scope) const;

+      SymbolType symbol_type() const;
+
    private:
      BL_TYPE bl_type_;
      std::vector<Statement*>list_;
@@ -217,11 +229,23 @@ class PCallTask  : public Statement {
      NetProc* elaborate_sys(Design*des, NetScope*scope) const;
      NetProc* elaborate_usr(Design*des, NetScope*scope) const;

-      NetProc*elaborate_method_(Design*des, NetScope*scope) const;
+      NetProc*elaborate_method_(Design*des, NetScope*scope,
+                                bool add_this_flag = false) const;
      NetProc*elaborate_function_(Design*des, NetScope*scope) const;
+      NetProc*elaborate_void_function_(Design*des, NetScope*scope,
+				       NetFuncDef*def) const;

      NetProc*elaborate_build_call_(Design*des, NetScope*scope,
 				    NetScope*task, NetExpr*use_this) const;
+      NetProc*elaborate_sys_task_method_(Design*des, NetScope*scope,
+					 NetNet*net,
+					 perm_string method_name,
+					 const char*sys_task_name) const;
+      NetProc*elaborate_queue_method_(Design*des, NetScope*scope,
+				      NetNet*net,
+				      perm_string method_name,
+				      const char*sys_task_name) const;
+      bool test_task_calls_ok_(Design*des, NetScope*scope) const;

      PPackage*package_;
      pform_name_t path_;
@@ -236,7 +260,7 @@ class PCase  : public Statement {
 	    Statement*stat;
      };

-      PCase(NetCase::TYPE, PExpr*ex, svector<Item*>*);
+      PCase(ivl_case_quality_t, NetCase::TYPE, PExpr*ex, svector<Item*>*);
      ~PCase();

      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
@@ -245,6 +269,7 @@ class PCase  : public Statement {
      virtual void dump(ostream&out, unsigned ind) const;

    private:
+      ivl_case_quality_t quality_;
      NetCase::TYPE type_;
      PExpr*expr_;

@@ -269,6 +294,26 @@ class PCAssign  : public Statement {
      PExpr*expr_;
 };

+/*
+ * This represents the syntax "super.new(...)". This is not really an
+ * executable statement, but the elaborator will handle these
+ * specially and will remove them from the statement stream. If any
+ */
+class PChainConstructor : public Statement {
+    public:
+      explicit PChainConstructor(const list<PExpr*>&parms);
+      ~PChainConstructor();
+
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
+      virtual void dump(ostream&out, unsigned ind) const;
+
+      inline const std::vector<PExpr*>& chain_args(void) const
+      { return parms_; }
+
+    private:
+      std::vector<PExpr*> parms_;
+};
+
 class PCondit  : public Statement {

    public:
@@ -336,6 +381,22 @@ class PDisable  : public Statement {
      pform_name_t scope_;
 };

+class PDoWhile  : public Statement {
+
+    public:
+      PDoWhile(PExpr*ex, Statement*st);
+      ~PDoWhile();
+
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
+      virtual void elaborate_scope(Design*des, NetScope*scope) const;
+      virtual void elaborate_sig(Design*des, NetScope*scope) const;
+      virtual void dump(ostream&out, unsigned ind) const;
+
+    private:
+      PExpr*cond_;
+      Statement*statement_;
+};
+
 /*
 * The event statement represents the event delay in behavioral
 * code. It comes from such things as:
@@ -350,8 +411,9 @@ class PEventStatement  : public Statement {

      explicit PEventStatement(const svector<PEEvent*>&ee);
      explicit PEventStatement(PEEvent*ee);
-	// Make an @* statement.
-      explicit PEventStatement(void);
+	// Make an @* statement or make a special @* version with the items
+	// from functions added and outputs removed for always_comb/latch.
+      explicit PEventStatement(bool always_sens = false);

      ~PEventStatement();

@@ -372,10 +434,12 @@ class PEventStatement  : public Statement {
      NetProc* elaborate_st(Design*des, NetScope*scope, NetProc*st) const;

      NetProc* elaborate_wait(Design*des, NetScope*scope, NetProc*st) const;
+      NetProc* elaborate_wait_fork(Design*des, NetScope*scope) const;

    private:
      svector<PEEvent*>expr_;
      Statement*statement_;
+      bool always_sens_;
 };

 ostream& operator << (ostream&o, const PEventStatement&obj);
@@ -394,6 +458,26 @@ class PForce  : public Statement {
      PExpr*expr_;
 };

+class PForeach : public Statement {
+    public:
+      explicit PForeach(perm_string var, const std::list<perm_string>&ix, Statement*stmt);
+      ~PForeach();
+
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
+      virtual void elaborate_scope(Design*des, NetScope*scope) const;
+      virtual void elaborate_sig(Design*des, NetScope*scope) const;
+      virtual void dump(ostream&out, unsigned ind) const;
+
+    private:
+      NetProc* elaborate_static_array_(Design*des, NetScope*scope,
+				       const std::vector<netrange_t>&dims) const;
+
+    private:
+      perm_string array_var_;
+      std::vector<perm_string> index_vars_;
+      Statement*statement_;
+};
+
 class PForever : public Statement {
    public:
      explicit PForever(Statement*s);
@@ -486,20 +570,21 @@ class PReturn  : public Statement {
 class PTrigger  : public Statement {

    public:
-      explicit PTrigger(const pform_name_t&ev);
+      explicit PTrigger(PPackage*pkg, const pform_name_t&ev);
      ~PTrigger();

      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
      virtual void dump(ostream&out, unsigned ind) const;

    private:
+      PPackage*package_;
      pform_name_t event_;
 };

 class PWhile  : public Statement {

    public:
-      PWhile(PExpr*e1, Statement*st);
+      PWhile(PExpr*ex, Statement*st);
      ~PWhile();

      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
@@ -512,4 +597,4 @@ class PWhile  : public Statement {
      Statement*statement_;
 };

-#endif
+#endif /* IVL_Statement_H */
@@ -1,7 +1,7 @@
-#ifndef PLI_TYPES
-#define PLI_TYPES
+#ifndef PLI_TYPES_H
+#define PLI_TYPES_H
 /*
- * Copyright (c) 2003 Stephen Williams ([email protected])
+ * Copyright (c) 2003-2014 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -85,4 +85,4 @@ typedef char           PLI_BYTE8;
 typedef unsigned char  PLI_UBYTE8;
 #endif

-#endif
+#endif /* PLI_TYPES_H */
@@ -1,7 +1,7 @@
-#ifndef __acc_user_H
-#define __acc_user_H
+#ifndef ACC_USER_H
+#define ACC_USER_H
 /*
- * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2002-2014 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -228,6 +228,7 @@ extern PLI_INT32 acc_fetch_size(handle obj);

 extern PLI_INT32 acc_fetch_type(handle obj);
 extern PLI_INT32 acc_fetch_fulltype(handle obj);
+extern PLI_INT32 acc_fetch_paramtype(handle obj);
 extern PLI_INT32 acc_fetch_range(handle object, int *msb, int *lsb);
 extern const char* acc_fetch_type_str(PLI_INT32 type);

@@ -270,4 +271,4 @@ extern char* acc_version(void);

 EXTERN_C_END

-#endif
+#endif /* ACC_USER_H */
@@ -23,11 +23,13 @@ AC_SUBST(install_suffix)
 # ------------------------------
 # Sub-macro for AX_C_UNDERSCORES_LEADING and AX_C_UNDERSCORES_TRAILING.
 # Unwarranted assumptions:
-#   - the object file produced by AC_COMPILE_IFELSE is called "conftest.$ac_objext"
-#   - the nm(1) utility is available, and its name is "nm".
+#   - the object file produced by AC_COMPILE_IFELSE is called
+#     "conftest.$ac_objext"
+#   - the nm(1) utility or an equivalent is available, and its name
+#     is defined by the $NM variable.
 AC_DEFUN([_AX_C_UNDERSCORES_MATCH_IF],
 [AC_COMPILE_IFELSE([AC_LANG_SOURCE([void underscore(void){}])],
-[AS_IF([nm conftest.$ac_objext|grep $1 >/dev/null 2>/dev/null],[$2],[$3])],
+[AS_IF([$NM conftest.$ac_objext|grep $1 >/dev/null 2>/dev/null],[$2],[$3])],
 [AC_MSG_ERROR([underscore test crashed])]
 )])

@@ -218,24 +220,16 @@ AC_SUBST(strip_dynamic)
 # AC_MSG_RESULT($strip_dynamic)
 ])# AX_LD_RDYNAMIC

-# AX_CPP_PRECOMP
-# --------------
-AC_DEFUN([AX_CPP_PRECOMP],
-[# Darwin requires -no-cpp-precomp
-case "${host}" in
-    *-*-darwin*)
-        CPPFLAGS="-no-cpp-precomp $CPPFLAGS"
-        CFLAGS="-no-cpp-precomp $CFLAGS"
-        ;;
-esac
-])# AX_CPP_PRECOMP

 # AX_C99_STRTOD
 # -------------
 AC_DEFUN([AX_C99_STRTOD],
 [# On MinGW we need to jump through hoops to get a C99 compliant strtod().
+ # mingw-w64 doesn't need this, and the 64-bit version doesn't support it.
 case "${host}" in
-    *-*-mingw*)
+    x86_64-w64-mingw32)
+        ;;
+    *-*-mingw32)
        LDFLAGS+=" -Wl,--undefined=___strtod,--wrap,strtod,--defsym,___wrap_strtod=___strtod"
        ;;
 esac
@@ -254,3 +248,130 @@ _config_header=$1
 _stamp_name=stamp-`expr //$_config_header : '.*/\([[^./]]*\)\.[[^./]]*$'`-h
 echo "timestamp for $_config_header" > `AS_DIRNAME(["$_config_header"])`/[]$_stamp_name
 ]) #_AC_AM_CONFIG_HEADER_HOOK
+
+# ===========================================================================
+#   http://www.gnu.org/software/autoconf-archive/ax_prog_cc_for_build.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_PROG_CC_FOR_BUILD
+#
+# DESCRIPTION
+#
+#   This macro searches for a C compiler that generates native executables,
+#   that is a C compiler that surely is not a cross-compiler. This can be
+#   useful if you have to generate source code at compile-time like for
+#   example GCC does.
+#
+#   The macro sets the CC_FOR_BUILD and CPP_FOR_BUILD macros to anything
+#   needed to compile or link (CC_FOR_BUILD) and preprocess (CPP_FOR_BUILD).
+#   The value of these variables can be overridden by the user by specifying
+#   a compiler with an environment variable (like you do for standard CC).
+#
+#   It also sets BUILD_EXEEXT and BUILD_OBJEXT to the executable and object
+#   file extensions for the build platform, and GCC_FOR_BUILD to `yes' if
+#   the compiler we found is GCC. All these variables but GCC_FOR_BUILD are
+#   substituted in the Makefile.
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Paolo Bonzini <[email protected]>
+#
+#   Copying and distribution of this file, with or without modification, are
+#   permitted in any medium without royalty provided the copyright notice
+#   and this notice are preserved. This file is offered as-is, without any
+#   warranty.
+
+#serial 8
+
+AU_ALIAS([AC_PROG_CC_FOR_BUILD], [AX_PROG_CC_FOR_BUILD])
+AC_DEFUN([AX_PROG_CC_FOR_BUILD], [dnl
+AC_REQUIRE([AC_PROG_CC])dnl
+AC_REQUIRE([AC_PROG_CPP])dnl
+AC_REQUIRE([AC_EXEEXT])dnl
+AC_REQUIRE([AC_CANONICAL_HOST])dnl
+
+dnl Use the standard macros, but make them use other variable names
+dnl
+pushdef([ac_cv_prog_CPP], ac_cv_build_prog_CPP)dnl
+pushdef([ac_cv_prog_gcc], ac_cv_build_prog_gcc)dnl
+pushdef([ac_cv_prog_cc_works], ac_cv_build_prog_cc_works)dnl
+pushdef([ac_cv_prog_cc_cross], ac_cv_build_prog_cc_cross)dnl
+pushdef([ac_cv_prog_cc_g], ac_cv_build_prog_cc_g)dnl
+pushdef([ac_cv_exeext], ac_cv_build_exeext)dnl
+pushdef([ac_cv_objext], ac_cv_build_objext)dnl
+pushdef([ac_exeext], ac_build_exeext)dnl
+pushdef([ac_objext], ac_build_objext)dnl
+pushdef([CC], CC_FOR_BUILD)dnl
+pushdef([CPP], CPP_FOR_BUILD)dnl
+pushdef([CFLAGS], CFLAGS_FOR_BUILD)dnl
+pushdef([CPPFLAGS], CPPFLAGS_FOR_BUILD)dnl
+pushdef([LDFLAGS], LDFLAGS_FOR_BUILD)dnl
+pushdef([host], build)dnl
+pushdef([host_alias], build_alias)dnl
+pushdef([host_cpu], build_cpu)dnl
+pushdef([host_vendor], build_vendor)dnl
+pushdef([host_os], build_os)dnl
+pushdef([ac_cv_host], ac_cv_build)dnl
+pushdef([ac_cv_host_alias], ac_cv_build_alias)dnl
+pushdef([ac_cv_host_cpu], ac_cv_build_cpu)dnl
+pushdef([ac_cv_host_vendor], ac_cv_build_vendor)dnl
+pushdef([ac_cv_host_os], ac_cv_build_os)dnl
+pushdef([ac_cpp], ac_build_cpp)dnl
+pushdef([ac_compile], ac_build_compile)dnl
+pushdef([ac_link], ac_build_link)dnl
+
+save_cross_compiling=$cross_compiling
+save_ac_tool_prefix=$ac_tool_prefix
+cross_compiling=no
+ac_tool_prefix=
+
+AC_PROG_CC
+AC_PROG_CPP
+AC_EXEEXT
+
+ac_tool_prefix=$save_ac_tool_prefix
+cross_compiling=$save_cross_compiling
+
+dnl Restore the old definitions
+dnl
+popdef([ac_link])dnl
+popdef([ac_compile])dnl
+popdef([ac_cpp])dnl
+popdef([ac_cv_host_os])dnl
+popdef([ac_cv_host_vendor])dnl
+popdef([ac_cv_host_cpu])dnl
+popdef([ac_cv_host_alias])dnl
+popdef([ac_cv_host])dnl
+popdef([host_os])dnl
+popdef([host_vendor])dnl
+popdef([host_cpu])dnl
+popdef([host_alias])dnl
+popdef([host])dnl
+popdef([LDFLAGS])dnl
+popdef([CPPFLAGS])dnl
+popdef([CFLAGS])dnl
+popdef([CPP])dnl
+popdef([CC])dnl
+popdef([ac_objext])dnl
+popdef([ac_exeext])dnl
+popdef([ac_cv_objext])dnl
+popdef([ac_cv_exeext])dnl
+popdef([ac_cv_prog_cc_g])dnl
+popdef([ac_cv_prog_cc_cross])dnl
+popdef([ac_cv_prog_cc_works])dnl
+popdef([ac_cv_prog_gcc])dnl
+popdef([ac_cv_prog_CPP])dnl
+
+dnl Finally, set Makefile variables
+dnl
+BUILD_EXEEXT=$ac_build_exeext
+BUILD_OBJEXT=$ac_build_objext
+AC_SUBST(BUILD_EXEEXT)dnl
+AC_SUBST(BUILD_OBJEXT)dnl
+AC_SUBST([CFLAGS_FOR_BUILD])dnl
+AC_SUBST([CPPFLAGS_FOR_BUILD])dnl
+AC_SUBST([LDFLAGS_FOR_BUILD])dnl
+])
+
@@ -50,8 +50,8 @@ bool NetEvWait::is_asynchronous()
 	   level sensitive, but the nex_async_ method takes care of
 	   that test. */
      NexusSet*sense = new NexusSet;
-      for (unsigned idx = 0 ;  idx < nevents_ ;  idx += 1) {
-	    NexusSet*tmp = event(idx)->nex_async_();
+      for (unsigned idx = 0 ;  idx < events_.size() ;  idx += 1) {
+	    NexusSet*tmp = events_[idx]->nex_async_();
 	    if (tmp == 0) {
 		  delete sense;
 		  return false;
@@ -10,4 +10,7 @@ echo "Autoconf in root..."
 autoconf -f

 echo "Precompiling lexor_keyword.gperf"
-gperf -o -i 7 -C -k 1-4,6,9,\$ -L ANSI-C -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc
+gperf -o -i 7 -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc
+
+echo "Precompiling vhdlpp/lexor_keyword.gperf"
+(cd vhdlpp ; gperf -o -i 7 --ignore-case -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc )
@@ -43,7 +43,7 @@ INCLUDE_PATH = -I. -I.. -I$(srcdir) -I$(srcdir)/..
 endif

 CPPFLAGS = $(INCLUDE_PATH) @CPPFLAGS@ @DEFS@ @PICFLAG@
-CFLAGS = @WARNING_FLAGS@ @CFLAGS@
+CFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CC@ @CFLAGS@
 LDFLAGS = @LDFLAGS@

 O = cadpli.o
@@ -59,7 +59,7 @@ distclean: clean
 	rm -f Makefile config.log

 cppcheck: $(O:.o=.c)
-	cppcheck --enable=all -f $(INCLUDE_PATH) $^
+	cppcheck --enable=all --std=posix --std=c99 --std=c++03 -f $(INCLUDE_PATH) $^

 Makefile: $(srcdir)/Makefile.in ../config.status
 	cd ..; ./config.status --file=cadpli/$@
@@ -71,17 +71,19 @@ dep:
 	$(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c $<
 	mv $*.d dep

-SYSTEM_VPI_LDFLAGS = -L../vvp -lvpi
+SYSTEM_VPI_LDFLAGS = -L../vpi -lvpi
 ifeq (@MINGW32@,yes)
    SYSTEM_VPI_LDFLAGS += @EXTRALIBS@
 endif

-cadpli.vpl: $O ../vvp/libvpi.a ../libveriuser/libveriuser.o
+cadpli.vpl: $O ../vpi/libvpi.a ../libveriuser/libveriuser.o
 	$(CC) @shared@ $(LDFLAGS) -o $@ $O ../libveriuser/libveriuser.o $(SYSTEM_VPI_LDFLAGS)

-install: all installdirs $(vpidir)/cadpli.vpl
+install: all installdirs installfiles

-$(vpidir)/cadpli.vpl: ./cadpli.vpl
+F = ./cadpli.vpl
+
+installfiles: $(F) | installdirs
 	$(INSTALL_PROGRAM) ./cadpli.vpl "$(DESTDIR)$(vpidir)/cadpli.vpl"

 installdirs: $(srcdir)/../mkinstalldirs
@@ -79,7 +79,7 @@ static void thunker_register(void)
      }
 }

-void (*vlog_startup_routines[])() = {
+void (*vlog_startup_routines[])(void) = {
      thunker_register,
      0
 };
@@ -1,7 +1,7 @@
-#ifndef __ivl_dlfcn_H
-#define __ivl_dlfcn_H
+#ifndef IVL_ivl_dlfcn_H
+#define IVL_ivl_dlfcn_H
 /*
- * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2001-2014 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -91,4 +91,4 @@ static __inline__ const char*dlerror(void)
 { return strerror( errno ); }
 #endif

-#endif
+#endif /* IVL_ivl_dlfcn_H */
@@ -1,7 +1,7 @@
-#ifndef __compiler_H
-#define __compiler_H
+#ifndef IVL_compiler_H
+#define IVL_compiler_H
 /*
- * Copyright (c) 1999-2013 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2019 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -36,6 +36,11 @@
 */
 extern unsigned integer_width;

+/*
+ * The width_cap is the width limit for unsized expressions.
+ */
+extern unsigned width_cap;
+
 /*
 * This is the maximum number of recursive module loops allowed within
 * a generate block.
@@ -75,6 +80,10 @@ extern unsigned recursive_mod_limit;
 /* Implicit definitions of wires. */
 extern bool warn_implicit;

+/* Warn if dimensions of port or var/net are implicitly taken from
+   the input/output/inout declaration. */
+extern bool warn_implicit_dimensions;
+
 /* inherit timescales across files. */
 extern bool warn_timescale;

@@ -92,9 +101,12 @@ extern bool warn_inf_loop;
 extern bool warn_sens_entire_vec;
 extern bool warn_sens_entire_arr;

-/* Warn about level-appropriate anochronisms. */
+/* Warn about level-appropriate anachronisms. */
 extern bool warn_anachronisms;

+/* Warn about nets that are references but not driven. */
+extern bool warn_floating_nets;
+
 /* This is true if verbose output is requested. */
 extern bool verbose_flag;

@@ -105,6 +117,13 @@ extern bool debug_emit;
 extern bool debug_synth2;
 extern bool debug_optimizer;

+/* Ignore errors about missing modules */
+extern bool ignore_missing_modules;
+
+/* Treat each source file as a separate compilation unit (as defined
+   by SystemVerilog). */
+extern bool separate_compilation;
+
 /* Control evaluation of functions at compile time:
 *   0 = only for functions in constant expressions
 *   1 = only for automatic functions
@@ -133,7 +152,8 @@ extern int build_library_index(const char*path, bool key_case_sensitive);

 /* This is the generation of Verilog that the compiler is asked to
   support. Then there are also more detailed controls for more
-   specific language features. */
+   specific language features. Note that the compiler often assumes
+   this is an ordered list. */
 enum generation_t {
      GN_VER1995  = 1,
      GN_VER2001_NOCONFIG  = 2,
@@ -157,6 +177,13 @@ extern bool gn_icarus_misc_flag;
   is false, then skip elaboration of specify behavior. */
 extern bool gn_specify_blocks_flag;

+/* If this flag is true, then elaborate supported assertion statements. If
+   this flag is false, then stub out supported assertion statements. */
+extern bool gn_supported_assertions_flag;
+/* If this flag is true, then error on unsupported assertion statements. If
+   this flag is false, then stub out unsupported assertion statements. */
+extern bool gn_unsupported_assertions_flag;
+
 /* If this flag is true, then support/elaborate Verilog-AMS. */
 extern bool gn_verilog_ams_flag;

@@ -173,25 +200,24 @@ extern bool gn_strict_ca_eval_flag;
   standard expression width rules. */
 extern bool gn_strict_expr_width_flag;

-/* If variables can be converted to uwires by a continuous assignment
-   (assuming no procedural assign, then return true. This will be true
-   for SystemVerilog */
-static inline bool gn_var_can_be_uwire(void)
+/* If this flag is true, then don't add a for-loop control variable
+   to an implicit event_expression list if it is only used inside the
+   loop. */
+extern bool gn_shared_loop_index_flag;
+
+static inline bool gn_system_verilog(void)
 {
-      if (generation_flag == GN_VER2005_SV ||
-          generation_flag == GN_VER2009  ||
-          generation_flag == GN_VER2012)
+      if (generation_flag >= GN_VER2005_SV)
 	    return true;
      return false;
 }

-static inline bool gn_system_verilog(void)
+/* If variables can be converted to uwires by a continuous assignment
+   (assuming no procedural assign), then return true. This will be true
+   for SystemVerilog */
+static inline bool gn_var_can_be_uwire(void)
 {
-      if (generation_flag == GN_VER2005_SV ||
-          generation_flag == GN_VER2009  ||
-          generation_flag == GN_VER2012)
-	    return true;
-      return false;
+      return gn_system_verilog();
 }

 static inline bool gn_modules_nest(void)
@@ -260,12 +286,20 @@ struct sfunc_return_type {
      const char*   name;
      ivl_variable_type_t type;
      unsigned      wid;
-      int           signed_flag;
+      bool          signed_flag;
+      bool          override_flag;
 };

+extern void add_sys_func(const struct sfunc_return_type&ret_type);
 extern const struct sfunc_return_type* lookup_sys_func(const char*name);
 extern int load_sys_func_table(const char*path);
 extern void cleanup_sys_func_table();
+/*
+ * This temporarily loads a VPI module, to determine the return values
+ * of system functions provided by that module, and adds the return values
+ * to the system function table.
+ */
+extern bool load_vpi_module(const char*path);

 /*
 * In system Verilog it is allowed with a warning to call a function
@@ -274,4 +308,4 @@ extern void cleanup_sys_func_table();
 */
 extern ivl_sfunc_as_task_t def_sfunc_as_task;

-#endif
+#endif /* IVL_compiler_H */
@@ -1,7 +1,7 @@
-#ifndef __config_H                                           /* -*- c++ -*- */
-#define __config_H
+#ifndef IVL_config_H                                           /* -*- c++ -*- */
+#define IVL_config_H
 /*
- * Copyright (c) 2001-2012 Stephen Williams ([email protected])
+ * Copyright (c) 2001-2015 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -55,6 +55,7 @@
 # undef HAVE_FSEEKO
 /* And this is needed by the fst files (copied from GTKWave). */
 # undef HAVE_LIBPTHREAD
+# undef HAVE_REALPATH

 /*
 * Define this if you want to compile vvp with memory freeing and
@@ -62,4 +63,4 @@
 */
 # undef CHECK_WITH_VALGRIND

-#endif /* __config_H */
+#endif /* IVL_config_H */
@@ -1,44 +1,40 @@
 #! /bin/sh
 # Configuration validation subroutine script.
-#   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-#   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
-#   Free Software Foundation, Inc.
+#   Copyright 1992-2015 Free Software Foundation, Inc.

-timestamp='2009-04-17'
+timestamp='2015-03-08'

-# This file is (in principle) common to ALL GNU software.
-# The presence of a machine in this file suggests that SOME GNU software
-# can handle that machine.  It does not imply ALL GNU software can.
-#
-# This file is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
 # (at your option) any later version.
 #
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
-# 02110-1301, USA.
+# along with this program; if not, see <http://www.gnu.org/licenses/>.
 #
 # As a special exception to the GNU General Public License, if you
 # distribute this file as part of a program that contains a
 # configuration script generated by Autoconf, you may include it under
-# the same distribution terms that you use for the rest of that program.
+# the same distribution terms that you use for the rest of that
+# program.  This Exception is an additional permission under section 7
+# of the GNU General Public License, version 3 ("GPLv3").


-# Please send patches to <[email protected]>.  Submit a context
-# diff and a properly formatted ChangeLog entry.
+# Please send patches to <[email protected]>.
 #
 # Configuration subroutine to validate and canonicalize a configuration type.
 # Supply the specified configuration type as an argument.
 # If it is invalid, we print an error message on stderr and exit with code 1.
 # Otherwise, we print the canonical config type on stdout and succeed.

+# You can get the latest version of this script from:
+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD
+
 # This file is supposed to be the same for all GNU packages
 # and recognize all the CPU types, system types and aliases
 # that are meaningful with *any* GNU software.
@@ -72,8 +68,7 @@ Report bugs and patches to <[email protected]>."
 version="\
 GNU config.sub ($timestamp)

-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
-2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+Copyright 1992-2015 Free Software Foundation, Inc.

 This is free software; see the source for copying conditions.  There is NO
 warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
@@ -120,13 +115,18 @@ esac
 # Here we must recognize all the valid KERNEL-OS combinations.
 maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
 case $maybe_os in
-  nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \
-  uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \
+  nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \
+  linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \
+  knetbsd*-gnu* | netbsd*-gnu* | netbsd*-eabi* | \
  kopensolaris*-gnu* | \
  storm-chaos* | os2-emx* | rtmk-nova*)
    os=-$maybe_os
    basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`
    ;;
+  android-linux)
+    os=-linux-android
+    basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`-unknown
+    ;;
  *)
    basic_machine=`echo $1 | sed 's/-[^-]*$//'`
    if [ $basic_machine != $1 ]
@@ -149,10 +149,13 @@ case $os in
 	-convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\
 	-c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \
 	-harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \
-	-apple | -axis | -knuth | -cray)
+	-apple | -axis | -knuth | -cray | -microblaze*)
 		os=
 		basic_machine=$1
 		;;
+	-bluegene*)
+		os=-cnk
+		;;
 	-sim | -cisco | -oki | -wec | -winbond)
 		os=
 		basic_machine=$1
@@ -167,10 +170,10 @@ case $os in
 		os=-chorusos
 		basic_machine=$1
 		;;
- 	-chorusrdb)
- 		os=-chorusrdb
+	-chorusrdb)
+		os=-chorusrdb
 		basic_machine=$1
- 		;;
+		;;
 	-hiux*)
 		os=-hiuxwe2
 		;;
@@ -215,6 +218,12 @@ case $os in
 	-isc*)
 		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
 		;;
+	-lynx*178)
+		os=-lynxos178
+		;;
+	-lynx*5)
+		os=-lynxos5
+		;;
 	-lynx*)
 		os=-lynxos
 		;;
@@ -239,20 +248,28 @@ case $basic_machine in
 	# Some are omitted here because they have special meanings below.
 	1750a | 580 \
 	| a29k \
+	| aarch64 | aarch64_be \
 	| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \
 	| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
 	| am33_2.0 \
-	| arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \
+	| arc | arceb \
+	| arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \
+	| avr | avr32 \
+	| be32 | be64 \
 	| bfin \
-	| c4x | clipper \
+	| c4x | c8051 | clipper \
 	| d10v | d30v | dlx | dsp16xx \
-	| fido | fr30 | frv \
+	| e2k | epiphany \
+	| fido | fr30 | frv | ft32 \
 	| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
+	| hexagon \
 	| i370 | i860 | i960 | ia64 \
 	| ip2k | iq2000 \
+	| k1om \
+	| le32 | le64 \
 	| lm32 \
 	| m32c | m32r | m32rle | m68000 | m68k | m88k \
-	| maxq | mb | microblaze | mcore | mep | metag \
+	| maxq | mb | microblaze | microblazeel | mcore | mep | metag \
 	| mips | mipsbe | mipseb | mipsel | mipsle \
 	| mips16 \
 	| mips64 | mips64el \
@@ -266,36 +283,55 @@ case $basic_machine in
 	| mips64vr5900 | mips64vr5900el \
 	| mipsisa32 | mipsisa32el \
 	| mipsisa32r2 | mipsisa32r2el \
+	| mipsisa32r6 | mipsisa32r6el \
 	| mipsisa64 | mipsisa64el \
 	| mipsisa64r2 | mipsisa64r2el \
+	| mipsisa64r6 | mipsisa64r6el \
 	| mipsisa64sb1 | mipsisa64sb1el \
 	| mipsisa64sr71k | mipsisa64sr71kel \
+	| mipsr5900 | mipsr5900el \
 	| mipstx39 | mipstx39el \
 	| mn10200 | mn10300 \
 	| moxie \
 	| mt \
 	| msp430 \
-	| nios | nios2 \
+	| nds32 | nds32le | nds32be \
+	| nios | nios2 | nios2eb | nios2el \
 	| ns16k | ns32k \
-	| or32 \
+	| open8 | or1k | or1knd | or32 \
 	| pdp10 | pdp11 | pj | pjl \
-	| powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \
+	| powerpc | powerpc64 | powerpc64le | powerpcle \
 	| pyramid \
+	| riscv32 | riscv64 \
+	| rl78 | rx \
 	| score \
 	| sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
 	| sh64 | sh64le \
 	| sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \
 	| sparcv8 | sparcv9 | sparcv9b | sparcv9v \
-	| spu | strongarm \
-	| tahoe | thumb | tic4x | tic80 | tron \
-	| v850 | v850e \
+	| spu \
+	| tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \
+	| ubicom32 \
+	| v850 | v850e | v850e1 | v850e2 | v850es | v850e2v3 \
+	| visium \
 	| we32k \
-	| x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \
+	| x86 | xc16x | xstormy16 | xtensa \
 	| z8k | z80)
 		basic_machine=$basic_machine-unknown
 		;;
-	m6811 | m68hc11 | m6812 | m68hc12)
-		# Motorola 68HC11/12.
+	c54x)
+		basic_machine=tic54x-unknown
+		;;
+	c55x)
+		basic_machine=tic55x-unknown
+		;;
+	c6x)
+		basic_machine=tic6x-unknown
+		;;
+	leon|leon[3-9])
+		basic_machine=sparc-$basic_machine
+		;;
+	m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip)
 		basic_machine=$basic_machine-unknown
 		os=-none
 		;;
@@ -305,6 +341,21 @@ case $basic_machine in
 		basic_machine=mt-unknown
 		;;

+	strongarm | thumb | xscale)
+		basic_machine=arm-unknown
+		;;
+	xgate)
+		basic_machine=$basic_machine-unknown
+		os=-none
+		;;
+	xscaleeb)
+		basic_machine=armeb-unknown
+		;;
+
+	xscaleel)
+		basic_machine=armel-unknown
+		;;
+
 	# We use `pc' rather than `unknown'
 	# because (1) that's what they normally are, and
 	# (2) the word "unknown" tends to confuse beginning users.
@@ -319,25 +370,31 @@ case $basic_machine in
 	# Recognize the basic CPU types with company name.
 	580-* \
 	| a29k-* \
+	| aarch64-* | aarch64_be-* \
 	| alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \
 	| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \
-	| alphapca5[67]-* | alpha64pca5[67]-* | arc-* \
+	| alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \
 	| arm-*  | armbe-* | armle-* | armeb-* | armv*-* \
 	| avr-* | avr32-* \
+	| be32-* | be64-* \
 	| bfin-* | bs2000-* \
-	| c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \
-	| clipper-* | craynv-* | cydra-* \
+	| c[123]* | c30-* | [cjt]90-* | c4x-* \
+	| c8051-* | clipper-* | craynv-* | cydra-* \
 	| d10v-* | d30v-* | dlx-* \
-	| elxsi-* \
+	| e2k-* | elxsi-* \
 	| f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \
 	| h8300-* | h8500-* \
 	| hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \
+	| hexagon-* \
 	| i*86-* | i860-* | i960-* | ia64-* \
 	| ip2k-* | iq2000-* \
+	| k1om-* \
+	| le32-* | le64-* \
 	| lm32-* \
 	| m32c-* | m32r-* | m32rle-* \
 	| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
 	| m88110-* | m88k-* | maxq-* | mcore-* | metag-* \
+	| microblaze-* | microblazeel-* \
 	| mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
 	| mips16-* \
 	| mips64-* | mips64el-* \
@@ -351,32 +408,42 @@ case $basic_machine in
 	| mips64vr5900-* | mips64vr5900el-* \
 	| mipsisa32-* | mipsisa32el-* \
 	| mipsisa32r2-* | mipsisa32r2el-* \
+	| mipsisa32r6-* | mipsisa32r6el-* \
 	| mipsisa64-* | mipsisa64el-* \
 	| mipsisa64r2-* | mipsisa64r2el-* \
+	| mipsisa64r6-* | mipsisa64r6el-* \
 	| mipsisa64sb1-* | mipsisa64sb1el-* \
 	| mipsisa64sr71k-* | mipsisa64sr71kel-* \
+	| mipsr5900-* | mipsr5900el-* \
 	| mipstx39-* | mipstx39el-* \
 	| mmix-* \
 	| mt-* \
 	| msp430-* \
-	| nios-* | nios2-* \
+	| nds32-* | nds32le-* | nds32be-* \
+	| nios-* | nios2-* | nios2eb-* | nios2el-* \
 	| none-* | np1-* | ns16k-* | ns32k-* \
+	| open8-* \
+	| or1k*-* \
 	| orion-* \
 	| pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
-	| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \
+	| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \
 	| pyramid-* \
-	| romp-* | rs6000-* \
+	| rl78-* | romp-* | rs6000-* | rx-* \
 	| sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
 	| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
 	| sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \
 	| sparclite-* \
-	| sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \
-	| tahoe-* | thumb-* \
-	| tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* | tile-* \
+	| sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx?-* \
+	| tahoe-* \
+	| tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \
+	| tile*-* \
 	| tron-* \
-	| v850-* | v850e-* | vax-* \
+	| ubicom32-* \
+	| v850-* | v850e-* | v850e1-* | v850es-* | v850e2-* | v850e2v3-* \
+	| vax-* \
+	| visium-* \
 	| we32k-* \
-	| x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \
+	| x86-* | x86_64-* | xc16x-* | xps100-* \
 	| xstormy16-* | xtensa*-* \
 	| ymp-* \
 	| z8k-* | z80-*)
@@ -401,7 +468,7 @@ case $basic_machine in
 		basic_machine=a29k-amd
 		os=-udi
 		;;
-    	abacus)
+	abacus)
 		basic_machine=abacus-unknown
 		;;
 	adobe68k)
@@ -451,6 +518,9 @@ case $basic_machine in
 		basic_machine=i386-pc
 		os=-aros
 		;;
+        asmjs)
+		basic_machine=asmjs-unknown
+		;;
 	aux)
 		basic_machine=m68k-apple
 		os=-aux
@@ -467,11 +537,24 @@ case $basic_machine in
 		basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'`
 		os=-linux
 		;;
+	bluegene*)
+		basic_machine=powerpc-ibm
+		os=-cnk
+		;;
+	c54x-*)
+		basic_machine=tic54x-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	c55x-*)
+		basic_machine=tic55x-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	c6x-*)
+		basic_machine=tic6x-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
 	c90)
 		basic_machine=c90-cray
 		os=-unicos
 		;;
-        cegcc)
+	cegcc)
 		basic_machine=arm-unknown
 		os=-cegcc
 		;;
@@ -503,7 +586,7 @@ case $basic_machine in
 		basic_machine=craynv-cray
 		os=-unicosmp
 		;;
-	cr16)
+	cr16 | cr16-*)
 		basic_machine=cr16-unknown
 		os=-elf
 		;;
@@ -661,7 +744,6 @@ case $basic_machine in
 	i370-ibm* | ibm*)
 		basic_machine=i370-ibm
 		;;
-# I'm not sure what "Sysv32" means.  Should this be sysv3.2?
 	i*86v32)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
 		os=-sysv32
@@ -700,6 +782,9 @@ case $basic_machine in
 		basic_machine=m68k-isi
 		os=-sysv
 		;;
+	leon-*|leon[3-9]-*)
+		basic_machine=sparc-`echo $basic_machine | sed 's/-.*//'`
+		;;
 	m68knommu)
 		basic_machine=m68k-unknown
 		os=-linux
@@ -719,8 +804,15 @@ case $basic_machine in
 		basic_machine=ns32k-utek
 		os=-sysv
 		;;
+	microblaze*)
+		basic_machine=microblaze-xilinx
+		;;
+	mingw64)
+		basic_machine=x86_64-pc
+		os=-mingw64
+		;;
 	mingw32)
-		basic_machine=i386-pc
+		basic_machine=i686-pc
 		os=-mingw32
 		;;
 	mingw32ce)
@@ -748,6 +840,10 @@ case $basic_machine in
 		basic_machine=powerpc-unknown
 		os=-morphos
 		;;
+	moxiebox)
+		basic_machine=moxie-unknown
+		os=-moxiebox
+		;;
 	msdos)
 		basic_machine=i386-pc
 		os=-msdos
@@ -755,10 +851,18 @@ case $basic_machine in
 	ms1-*)
 		basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'`
 		;;
+	msys)
+		basic_machine=i686-pc
+		os=-msys
+		;;
 	mvs)
 		basic_machine=i370-ibm
 		os=-mvs
 		;;
+	nacl)
+		basic_machine=le32-unknown
+		os=-nacl
+		;;
 	ncr3000)
 		basic_machine=i486-ncr
 		os=-sysv4
@@ -823,6 +927,12 @@ case $basic_machine in
 	np1)
 		basic_machine=np1-gould
 		;;
+	neo-tandem)
+		basic_machine=neo-tandem
+		;;
+	nse-tandem)
+		basic_machine=nse-tandem
+		;;
 	nsr-tandem)
 		basic_machine=nsr-tandem
 		;;
@@ -905,9 +1015,10 @@ case $basic_machine in
 		;;
 	power)	basic_machine=power-ibm
 		;;
-	ppc)	basic_machine=powerpc-unknown
+	ppc | ppcbe)	basic_machine=powerpc-unknown
 		;;
-	ppc-*)	basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'`
+	ppc-* | ppcbe-*)
+		basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'`
 		;;
 	ppcle | powerpclittle | ppc-le | powerpc-little)
 		basic_machine=powerpcle-unknown
@@ -932,7 +1043,11 @@ case $basic_machine in
 		basic_machine=i586-unknown
 		os=-pw32
 		;;
-	rdos)
+	rdos | rdos64)
+		basic_machine=x86_64-pc
+		os=-rdos
+		;;
+	rdos32)
 		basic_machine=i386-pc
 		os=-rdos
 		;;
@@ -1001,6 +1116,9 @@ case $basic_machine in
 		basic_machine=i860-stratus
 		os=-sysv4
 		;;
+	strongarm-* | thumb-*)
+		basic_machine=arm-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
 	sun2)
 		basic_machine=m68000-sun
 		;;
@@ -1057,20 +1175,8 @@ case $basic_machine in
 		basic_machine=t90-cray
 		os=-unicos
 		;;
-	tic54x | c54x*)
-		basic_machine=tic54x-unknown
-		os=-coff
-		;;
-	tic55x | c55x*)
-		basic_machine=tic55x-unknown
-		os=-coff
-		;;
-	tic6x | c6x*)
-		basic_machine=tic6x-unknown
-		os=-coff
-		;;
 	tile*)
-		basic_machine=tile-unknown
+		basic_machine=$basic_machine-unknown
 		os=-linux-gnu
 		;;
 	tx39)
@@ -1140,6 +1246,9 @@ case $basic_machine in
 	xps | xps100)
 		basic_machine=xps100-honeywell
 		;;
+	xscale-* | xscalee[bl]-*)
+		basic_machine=`echo $basic_machine | sed 's/^xscale/arm/'`
+		;;
 	ymp)
 		basic_machine=ymp-cray
 		os=-unicos
@@ -1237,9 +1346,12 @@ esac
 if [ x"$os" != x"" ]
 then
 case $os in
-        # First match some system type aliases
-        # that might get confused with valid system types.
+	# First match some system type aliases
+	# that might get confused with valid system types.
 	# -solaris* is a basic system type, with this one exception.
+	-auroraux)
+		os=-auroraux
+		;;
 	-solaris1 | -solaris1.*)
 		os=`echo $os | sed -e 's|solaris1|sunos4|'`
 		;;
@@ -1260,30 +1372,31 @@ case $os in
 	# Each alternative MUST END IN A *, to match a version number.
 	# -sysv* is not here because it comes later, after sysvr4.
 	-gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \
-	      | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\
-	      | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \
-	      | -kopensolaris* \
+	      | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\
+	      | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \
+	      | -sym* | -kopensolaris* | -plan9* \
 	      | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \
-	      | -aos* | -aros* \
+	      | -aos* | -aros* | -cloudabi* \
 	      | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \
 	      | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \
 	      | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \
-	      | -openbsd* | -solidbsd* \
+	      | -bitrig* | -openbsd* | -solidbsd* \
 	      | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \
 	      | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \
 	      | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \
 	      | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
 	      | -chorusos* | -chorusrdb* | -cegcc* \
-	      | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
-	      | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \
-	      | -uxpv* | -beos* | -mpeix* | -udk* \
+	      | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
+	      | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \
+	      | -linux-newlib* | -linux-musl* | -linux-uclibc* \
+	      | -uxpv* | -beos* | -mpeix* | -udk* | -moxiebox* \
 	      | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \
 	      | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \
 	      | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \
 	      | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \
 	      | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \
 	      | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \
-	      | -skyos* | -haiku* | -rdos* | -toppers* | -drops*)
+	      | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* | -tirtos*)
 	# Remember, each alternative MUST END IN *, to match a version number.
 		;;
 	-qnx*)
@@ -1322,7 +1435,7 @@ case $os in
 	-opened*)
 		os=-openedition
 		;;
-        -os400*)
+	-os400*)
 		os=-os400
 		;;
 	-wince*)
@@ -1371,7 +1484,7 @@ case $os in
 	-sinix*)
 		os=-sysv4
 		;;
-        -tpf*)
+	-tpf*)
 		os=-tpf
 		;;
 	-triton*)
@@ -1407,15 +1520,14 @@ case $os in
 	-aros*)
 		os=-aros
 		;;
-	-kaos*)
-		os=-kaos
-		;;
 	-zvmoe)
 		os=-zvmoe
 		;;
 	-dicos*)
 		os=-dicos
 		;;
+	-nacl*)
+		;;
 	-none)
 		;;
 	*)
@@ -1438,10 +1550,10 @@ else
 # system, and we'll never get to this point.

 case $basic_machine in
-        score-*)
+	score-*)
 		os=-elf
 		;;
-        spu-*)
+	spu-*)
 		os=-elf
 		;;
 	*-acorn)
@@ -1453,8 +1565,23 @@ case $basic_machine in
 	arm*-semi)
 		os=-aout
 		;;
-        c4x-* | tic4x-*)
-        	os=-coff
+	c4x-* | tic4x-*)
+		os=-coff
+		;;
+	c8051-*)
+		os=-elf
+		;;
+	hexagon-*)
+		os=-elf
+		;;
+	tic54x-*)
+		os=-coff
+		;;
+	tic55x-*)
+		os=-coff
+		;;
+	tic6x-*)
+		os=-coff
 		;;
 	# This must come before the *-dec entry.
 	pdp10-*)
@@ -1474,14 +1601,11 @@ case $basic_machine in
 		;;
 	m68000-sun)
 		os=-sunos3
-		# This also exists in the configure program, but was not the
-		# default.
-		# os=-sunos4
 		;;
 	m68*-cisco)
 		os=-aout
 		;;
-        mep-*)
+	mep-*)
 		os=-elf
 		;;
 	mips*-cisco)
@@ -1508,7 +1632,7 @@ case $basic_machine in
 	*-ibm)
 		os=-aix
 		;;
-    	*-knuth)
+	*-knuth)
 		os=-mmixware
 		;;
 	*-wec)
@@ -1613,7 +1737,7 @@ case $basic_machine in
 			-sunos*)
 				vendor=sun
 				;;
-			-aix*)
+			-cnk*|-aix*)
 				vendor=ibm
 				;;
 			-beos*)
@@ -14,10 +14,6 @@ AC_CANONICAL_HOST
 dnl Checks for programs.
 AC_PROG_CC
 # AC_PROG_CC_C99 is only available in autoconf version 2.60 and later.
-# If you must use an older version then comment out the following two
-# lines, but be warned that there could be issues with finding the
-# nan(), etc. functions. It is really best to upgrade to a supported
-# version of autoconf.
 AC_PREREQ([2.60])
 AC_PROG_CC_C99
 AC_PROG_CXX
@@ -58,6 +54,10 @@ then
        exit 1
 fi

+if test "x$NM" = "x"; then
+	NM=nm
+fi
+
 AC_EXEEXT
 AC_SUBST(EXEEXT)

@@ -85,8 +85,9 @@ AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[]])],
 CFLAGS="$iverilog_temp_cflags"

 AC_SUBST(DEPENDENCY_FLAG, [-MD])
-AC_SUBST(WARNING_FLAGS, ["-Wall -Wshadow"])
-AC_SUBST(WARNING_FLAGS_CXX, ["$iverilog_wextra_flag"])
+AC_SUBST(WARNING_FLAGS, ["-Wall $iverilog_wextra_flag -Wshadow"])
+AC_SUBST(WARNING_FLAGS_CC, ["-Wstrict-prototypes"])
+AC_SUBST(WARNING_FLAGS_CXX, [""])
 fi

 AC_LANG(C++)
@@ -138,7 +139,13 @@ AC_CHECK_SIZEOF(unsigned)
 # vvp uses these...
 AC_CHECK_LIB(termcap, tputs)
 AC_CHECK_LIB(readline, readline)
+AC_CHECK_LIB(readline, add_history, NEED_LIBHISTORY=no, NEED_LIBHISTORY=yes)
+if test "$NEED_LIBHISTORY" = "yes"; then
 AC_CHECK_LIB(history, add_history)
+else
+# libreadline includes libhistory functions
+AC_DEFINE(HAVE_LIBHISTORY, 1)
+fi
 AC_CHECK_HEADERS(readline/readline.h readline/history.h sys/resource.h)
 case "${host}" in *linux*) AC_DEFINE([LINUX], [1], [Host operating system is Linux.]) ;; esac

@@ -217,9 +224,6 @@ AX_LD_EXTRALIBS
 # CFLAGS inherited by cadpli/Makefile?
 AX_C_PICFLAG

-# may modify CPPFLAGS and CFLAGS
-AX_CPP_PRECOMP
-
 # may modify LDFLAGS
 AX_C99_STRTOD

@@ -229,6 +233,10 @@ case "${host}" in
 	CPPFLAGS="-mieee $CPPFLAGS"
 	CFLAGS="-mieee $CFLAGS"
 	;;
+    *-*-mingw*)
+	CXXFLAGS="-D__USE_MINGW_ANSI_STDIO=1 $CXXFLAGS"
+	CFLAGS="-D__USE_MINGW_ANSI_STDIO=1 $CFLAGS"
+	;;
 esac

 # Do some more operating system specific setup. We put the file64_support
@@ -244,6 +252,9 @@ case "${host}" in
 esac
 AC_SUBST(file64_support)

+# fstapi.c (from GTKWave) needs this define.
+AC_CHECK_FUNCS(realpath)
+
 # Check that these functions exist. They are mostly C99
 # functions that older compilers may not yet support.
 AC_CHECK_FUNCS(fopen64)
@@ -324,5 +335,5 @@ then
 AC_MSG_ERROR(cannot configure white space in libdir: $libdir)
 fi
 AC_MSG_RESULT(ok)
-
-AC_OUTPUT(Makefile ivlpp/Makefile vhdlpp/Makefile vvp/Makefile vpi/Makefile driver/Makefile driver-vpi/Makefile cadpli/Makefile libveriuser/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-vvp/Makefile tgt-vhdl/Makefile tgt-fpga/Makefile tgt-verilog/Makefile tgt-pal/Makefile tgt-vlog95/Makefile tgt-pcb/Makefile tgt-blif/Makefile)
+AX_PROG_CC_FOR_BUILD
+AC_OUTPUT(Makefile ivlpp/Makefile vhdlpp/Makefile vvp/Makefile vpi/Makefile driver/Makefile driver-vpi/Makefile cadpli/Makefile libveriuser/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-vvp/Makefile tgt-vhdl/Makefile tgt-fpga/Makefile tgt-verilog/Makefile tgt-pal/Makefile tgt-vlog95/Makefile tgt-pcb/Makefile tgt-blif/Makefile tgt-sizer/Makefile)
@@ -1,3 +1,619 @@
 // These are correct and are used to find the base (zero) pin.
-thisSubtraction:netlist.h:4545
-thisSubtraction:netlist.h:4554
+thisSubtraction:netlist.h:5126
+thisSubtraction:netlist.h:5135
+
+// These are the functions that the compiler exports to the targets.
+//ivl_branch_island()
+unusedFunction:t-dll-api.cc:39
+//ivl_branch_terminal()
+unusedFunction:t-dll-api.cc:45
+
+//ivl_const_bits()
+unusedFunction:t-dll-api.cc:196
+//ivl_const_delay()
+unusedFunction:t-dll-api.cc:214
+//ivl_const_file()
+unusedFunction:t-dll-api.cc:221
+//ivl_const_lineno()
+unusedFunction:t-dll-api.cc:227
+//ivl_const_nex()
+unusedFunction:t-dll-api.cc:233
+//ivl_const_real()
+unusedFunction:t-dll-api.cc:239
+//ivl_const_scope()
+unusedFunction:t-dll-api.cc:246
+//ivl_const_signed()
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+unusedFunction:t-dll-api.cc:1029
+//ivl_udp_nin()
+unusedFunction:t-dll-api.cc:993
+//ivl_udp_port()
+unusedFunction:t-dll-api.cc:1005
+//ivl_udp_row()
+unusedFunction:t-dll-api.cc:1014
+//ivl_udp_rows()
+unusedFunction:t-dll-api.cc:1023
+// ivl_udp_sequ()
+unusedFunction:t-dll-api.cc:987
+
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2010,2012 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2013 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -163,11 +163,6 @@ void cprop_functor::lpm_mux(Design*des, NetMux*obj)
      if (! sel_nex->drivers_constant())
 	    return;

-	// If the select input is assigned or forced, then again there
-	// is nothing we can do here.
-      if (sel_nex->assign_lval())
-	    return;
-
 	// If the constant select is 'bz or 'bx, then give up.
      verinum::V sel_val = sel_nex->driven_value();
      if (sel_val == verinum::Vz || sel_val == verinum::Vx)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2012 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2020 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -30,6 +30,7 @@
 # include  "discipline.h"
 # include  "netclass.h"
 # include  "netdarray.h"
+# include  "netqueue.h"
 # include  "netvector.h"
 # include  "ivl_assert.h"
 # include  "PExpr.h"
@@ -113,6 +114,9 @@ ostream& operator << (ostream&o, ivl_variable_type_t val)
 	  case IVL_VT_CLASS:
 	    o << "class";
 	    break;
+	  case IVL_VT_QUEUE:
+	    o << "queue";
+	    break;
      }
      return o;
 }
@@ -145,21 +149,98 @@ ostream& operator << (ostream&o, ivl_switch_type_t val)
      return o;
 }

+ostream& operator << (ostream&fd, PortType::Enum val)
+{
+      switch (val) {
+	  case PortType::NOT_A_PORT:
+	    fd << "NOT_A_PORT";
+	    break;
+	  case PortType::PIMPLICIT:
+	    fd << "PIMPLICIT";
+	    break;
+	  case PortType::PINPUT:
+	    fd << "PINPUT";
+	    break;
+	  case PortType::POUTPUT:
+	    fd << "POUTPUT";
+	    break;
+	  case PortType::PINOUT:
+	    fd << "PINOUT";
+	    break;
+	  case PortType::PREF:
+	    fd << "PREF";
+	    break;
+	  default:
+	    fd << "PortType::Enum::?";
+	    break;
+      }
+
+      return fd;
+}
+
+ostream& operator << (ostream&fd, NetCaseCmp::kind_t that)
+{
+      switch (that) {
+	  case NetCaseCmp::EEQ:
+	    fd << "===";
+	    break;
+	  case NetCaseCmp::NEQ:
+	    fd << "!==";
+	    break;
+	  case NetCaseCmp::WEQ:
+	    fd << "==?";
+	    break;
+	  case NetCaseCmp::WNE:
+	    fd << "!=?";
+	    break;
+	  case NetCaseCmp::XEQ:
+	    fd << "==x?";
+	    break;
+	  case NetCaseCmp::ZEQ:
+	    fd << "==z?";
+	    break;
+      }
+      return fd;
+}
+
 ostream& ivl_type_s::debug_dump(ostream&o) const
 {
      o << typeid(*this).name();
      return o;
 }

+ostream& netclass_t::debug_dump(ostream&fd) const
+{
+      fd << "class " << name_ << "{";
+      for (size_t idx = 0 ; idx < property_table_.size() ; idx += 1) {
+	    if (idx != 0) fd << "; ";
+	    if (property_table_[idx].type)
+		  property_table_[idx].type->debug_dump(fd);
+	    else
+		  fd << "NO_TYPE";
+	    fd << " " << property_table_[idx].name;
+      }
+      fd << "}";
+      return fd;
+}
+
 ostream& netdarray_t::debug_dump(ostream&o) const
 {
      o << "dynamic array of " << *element_type();
      return o;
 }

+ostream& netqueue_t::debug_dump(ostream&fd) const
+{
+      fd << "queue of ";
+      if (max_idx_ >= 0) fd << "(maximum of " << max_idx_+1 << " elements) ";
+      fd << *element_type();
+      return fd;
+}
+
 ostream& netvector_t::debug_dump(ostream&o) const
 {
-      o << type_ << (signed_? " signed" : " unsigned") << packed_dims_;
+      o << "netvector_t:" << type_ << (signed_? " signed" : " unsigned") << packed_dims_;
      return o;
 }

@@ -170,10 +251,7 @@ static inline void dump_scope_path(ostream&o, const NetScope*scope)
 	    dump_scope_path(o, parent);
 	    o << ".";
      }
-      const hname_t name = scope->fullname();
-      o << name.peek_name();
-      if (name.has_number())
-	    o << "[" << name.peek_number() << "]";
+      o << scope->fullname();
 }

 ostream& operator <<(ostream&o, struct __ScopePathManip marg)
@@ -183,6 +261,77 @@ ostream& operator <<(ostream&o, struct __ScopePathManip marg)
      return o;
 }

+ostream& operator <<(ostream&o, struct __ObjectPathManip marg)
+{
+      if (marg.obj != 0) {
+	    dump_scope_path(o, marg.obj->scope());
+	    o << "." << marg.obj->name();
+      }
+      return o;
+}
+
+ostream& operator <<(ostream&fd, Link::DIR dir)
+{
+      switch (dir) {
+	  case Link::PASSIVE:
+	    fd << "PASSIVE";
+	    break;
+	  case Link::INPUT:
+	    fd << "INPUT";
+	    break;
+	  case Link::OUTPUT:
+	    fd << "OUTPUT";
+	    break;
+	  default:
+	    fd << "<" << (int)dir << ">";
+	    break;
+      }
+      return fd;
+}
+
+void NetPins::show_type(ostream&fd) const
+{
+      fd << typeid(*this).name();
+}
+
+void NetObj::show_type(ostream&fd) const
+{
+      fd << typeid(*this).name() << "[" << scope_path(scope_) << "." << name_ << "]";
+}
+
+struct __ShowTypeManip { const NetPins*pins; };
+inline __ShowTypeManip show_type(const NetPins*pins)
+{ __ShowTypeManip tmp; tmp.pins = pins; return tmp; }
+
+inline ostream& operator << (ostream&fd, __ShowTypeManip man)
+{
+      if (man.pins == 0)
+	    fd << "NexusSet";
+      else
+	    man.pins->show_type(fd);
+      return fd;
+}
+
+
+void Link::dump_link(ostream&fd, unsigned ind) const
+{
+      const Link*cur;
+      const Nexus*nex = nexus();
+
+      if (nex == 0) {
+	    fd << setw(ind) << "" << "<unlinked>" << endl;
+	    return;
+      }
+
+      for (cur = nex->first_nlink() ; cur; cur = cur->next_nlink()) {
+	    const NetPins*obj = cur->get_obj();
+	    unsigned pin = cur->get_pin();
+	    fd << setw(ind) << "" << "Pin " << pin
+	       << " of " << show_type(obj)
+	       << ", dir=" << cur->dir_ << endl;
+      }
+}
+
 void NetBranch::dump(ostream&o, unsigned ind) const
 {
      static const char*pin_names[2] = {
@@ -203,6 +352,10 @@ void NetDelaySrc::dump(ostream&o, unsigned ind) const
 	    if (has_condit()) o << " if";
 	    else o << " ifnone";
      }
+      if (parallel_)
+	    o << " parallel";
+      else
+	    o << " full";
      o << " src "
 	<< "(" << transition_delays_[IVL_PE_01]
 	<< "," << transition_delays_[IVL_PE_10]
@@ -514,10 +667,7 @@ void NetBUFZ::dump_node(ostream&o, unsigned ind) const

 void NetCaseCmp::dump_node(ostream&o, unsigned ind) const
 {
-      if (eeq_)
-	    o << setw(ind) << "" << "case compare === : " << name() << endl;
-      else
-	    o << setw(ind) << "" << "case compare !== : " << name() << endl;
+      o << setw(ind) << "" << "case compare " << kind_ << ": " << name() << endl;

      dump_node_pins(o, ind+4);
 }
@@ -539,13 +689,25 @@ void NetConst::dump_node(ostream&o, unsigned ind) const
 void NetFF::dump_node(ostream&o, unsigned ind) const
 {
      o << setw(ind) << "" << "LPM_FF: " << name()
-	<< " scope=" << scope_path(scope())
-	<< " aset_value=" << aset_value_ << endl;
+	<< " scope=" << scope_path(scope());
+      if (negedge_)
+	    o << " negedge";
+      else
+	    o << " posedge";
+      o << " aset_value=" << aset_value_ << endl;

      dump_node_pins(o, ind+4);
      dump_obj_attr(o, ind+4);
 }

+void NetLatch::dump_node(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << "LPM_LATCH: " << name()
+	<< " scope=" << scope_path(scope()) << endl;
+      dump_node_pins(o, ind+4);
+      dump_obj_attr(o, ind+4);
+}
+
 void NetLiteral::dump_node(ostream&o, unsigned ind) const
 {
      o << setw(ind) << "" << "constant real " << real_
@@ -579,6 +741,12 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
 	  case CMOS:
 	    o << "cmos";
 	    break;
+	  case EQUIV:
+	    o << "<->";
+	    break;
+	  case IMPL:
+	    o << "->";
+	    break;
 	  case NAND:
 	    o << "nand";
 	    break;
@@ -665,6 +833,21 @@ void NetPartSelect::dump_node(ostream&o, unsigned ind) const
      dump_obj_attr(o, ind+4);
 }

+void NetSubstitute::dump_node(ostream&fd, unsigned ind) const
+{
+      fd << setw(ind) << "" << "NetSubstitute: "
+	 << name();
+      if (rise_time())
+	    fd << " #(" << *rise_time()
+	       << "," << *fall_time()
+	       << "," << *decay_time() << ")";
+      else
+	    fd << " #(.,.,.)";
+      fd << " width=" << wid_ << " base=" << off_ <<endl;
+      dump_node_pins(fd, ind+4);
+      dump_obj_attr(fd, ind+4);
+}
+
 void NetReplicate::dump_node(ostream&o, unsigned ind) const
 {
      o << setw(ind) << "" << "NetReplicate: "
@@ -746,12 +929,13 @@ void NetUserFunc::dump_node(ostream&o, unsigned ind) const

 void NetTaskDef::dump(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "task " << scope_path(scope_) << ";" << endl;
+      o << setw(ind) << "" << "task " << scope_path(scope()) << ";" << endl;

-      for (unsigned idx = 0 ;  idx < ports_.size() ;  idx += 1) {
+      for (unsigned idx = 0 ;  idx < port_count() ;  idx += 1) {
+	    const NetNet*pnet = port(idx);
 	    o << setw(ind+4) << "";
-	    assert(ports_[idx]);
-	    switch (ports_[idx]->port_type()) {
+	    assert(pnet);
+	    switch (pnet->port_type()) {
 		case NetNet::PINPUT:
 		  o << "input ";
 		  break;
@@ -765,7 +949,7 @@ void NetTaskDef::dump(ostream&o, unsigned ind) const
 		  o << "NOT_A_PORT ";
 		  break;
 	    }
-	    o << ports_[idx]->name() << ";" << endl;
+	    o << pnet->name() << ";" << endl;
      }

      if (proc_)
@@ -818,6 +1002,18 @@ void NetProcTop::dump(ostream&o, unsigned ind) const
 	    o << "always  /* " << get_fileline() << " in "
 	      << scope_path(scope_) << " */" << endl;
 	    break;
+	  case IVL_PR_ALWAYS_COMB:
+	    o << "always_comb  /* " << get_fileline() << " in "
+	      << scope_path(scope_) << " */" << endl;
+	    break;
+	  case IVL_PR_ALWAYS_FF:
+	    o << "always_ff  /* " << get_fileline() << " in "
+	      << scope_path(scope_) << " */" << endl;
+	    break;
+	  case IVL_PR_ALWAYS_LATCH:
+	    o << "always_latch  /* " << get_fileline() << " in "
+	      << scope_path(scope_) << " */" << endl;
+	    break;
 	  case IVL_PR_FINAL:
 	    o << "final  /* " << get_fileline() << " in "
 	      << scope_path(scope_) << " */" << endl;
@@ -845,6 +1041,13 @@ void NetAnalogTop::dump(ostream&o, unsigned ind) const
 	      << scope_path(scope_) << " */" << endl;
 	    break;

+	    // These are not used in an analog context.
+	  case IVL_PR_ALWAYS_COMB:
+	  case IVL_PR_ALWAYS_FF:
+	  case IVL_PR_ALWAYS_LATCH:
+	    assert(0);
+	    break;
+
 	  case IVL_PR_FINAL:
 	    o << "analog final /* " << get_fileline() << " in "
 	      << scope_path(scope_) << " */" << endl;
@@ -861,19 +1064,22 @@ void NetAlloc::dump(ostream&o, unsigned ind) const

 void NetAssign_::dump_lval(ostream&o) const
 {
-      if (sig_) {
-	    o << sig_->name();
-	    if (! member_.nil()) {
-		  o << "." << member_;
-	    }
-	    if (word_) {
-		  o << "[word=" << *word_ << "]";
-	    }
-	    if (base_) {
-		  o << "[" << *base_ << " +: " << lwid_ << "]";
-	    }
-      } else {
-	    o << "";
+      if (sig_) o << sig_->name();
+      else if (nest_) {
+	    o << "(";
+	    nest_->dump_lval(o);
+	    o << ")";
+      }
+      else o << "<?>";
+
+      if (! member_.nil()) {
+	    o << "." << member_;
+      }
+      if (word_) {
+	    o << "[word=" << *word_ << "]";
+      }
+      if (base_) {
+	    o << "[" << *base_ << " +: " << lwid_ << "]";
      }
 }

@@ -956,19 +1162,33 @@ void NetBlock::dump(ostream&o, unsigned ind) const

 void NetCase::dump(ostream&o, unsigned ind) const
 {
+      o << setw(ind) << "";
+      switch (quality_) {
+	  case IVL_CASE_QUALITY_BASIC:
+	    break;
+	  case IVL_CASE_QUALITY_UNIQUE:
+	    o << "unique ";
+	    break;
+	  case IVL_CASE_QUALITY_UNIQUE0:
+	    o << "unique0 ";
+	    break;
+	  case IVL_CASE_QUALITY_PRIORITY:
+	    o << "priority ";
+	    break;
+      }
      switch (type_) {
 	  case EQ:
-	    o << setw(ind) << "" << "case (" << *expr_ << ")" << endl;
+	    o << "case (" << *expr_ << ")" << endl;
 	    break;
 	  case EQX:
-	    o << setw(ind) << "" << "casex (" << *expr_ << ")" << endl;
+	    o << "casex (" << *expr_ << ")" << endl;
 	    break;
 	  case EQZ:
-	    o << setw(ind) << "" << "casez (" << *expr_ << ")" << endl;
+	    o << "casez (" << *expr_ << ")" << endl;
 	    break;
      }

-      for (unsigned idx = 0 ;  idx < nitems_ ;  idx += 1) {
+      for (unsigned idx = 0 ;  idx < items_.size() ;  idx += 1) {
 	    o << setw(ind+2) << "";
 	    if (items_[idx].guard)
 		  o << *items_[idx].guard << ":";
@@ -1026,8 +1246,17 @@ void NetDeassign::dump(ostream&o, unsigned ind) const

 void NetDisable::dump(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "disable " << scope_path(target_) << "; "
-	<< "/* " << get_fileline() << " */" << endl;
+      o << setw(ind) << "" << "disable ";
+      if (target_) o << scope_path(target_);
+      else o << "fork";
+      o << "; " << "/* " << get_fileline() << " */" << endl;
+}
+
+void NetDoWhile::dump(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << "do" << endl;
+      proc_->dump(o, ind+3);
+      o << setw(ind) << "" << "while (" << *cond_ << ");" << endl;
 }

 void NetEvProbe::dump_node(ostream&o, unsigned ind) const
@@ -1058,7 +1287,15 @@ void NetEvTrig::dump(ostream&o, unsigned ind) const

 void NetEvWait::dump(ostream&o, unsigned ind) const
 {
-      o << setw(ind) <<"" << "@(";
+      o << setw(ind) << "";
+
+	/* Check for a wait fork. */
+      if ((nevents() == 1) && (event(0) == 0)) {
+	    o << "wait fork;";
+	    return;
+      }
+
+      o << "@(";

      if (nevents() > 0)
 	    o << event(0)->name();
@@ -1082,6 +1319,12 @@ ostream& operator << (ostream&out, const NetEvWait&obj)

 void NetEvWait::dump_inline(ostream&o) const
 {
+	/* Check for a wait fork. */
+      if ((nevents() == 1) && (event(0) == 0)) {
+	    o << "wait fork;";
+	    return;
+      }
+
      o << "@(";

      if (nevents() > 0)
@@ -1106,6 +1349,13 @@ void NetForever::dump(ostream&o, unsigned ind) const
      statement_->dump(o, ind+2);
 }

+void NetForLoop::dump(ostream&fd, unsigned ind) const
+{
+      fd << setw(ind) << "" << "FOR LOOP index=" << index_->name() << endl;
+      statement_->dump(fd, ind+4);
+      step_statement_->dump(fd, ind+4);
+}
+
 void NetFree::dump(ostream&o, unsigned ind) const
 {
      o << setw(ind) << "// free storage : " << scope_path(scope_) << endl;
@@ -1113,7 +1363,7 @@ void NetFree::dump(ostream&o, unsigned ind) const

 void NetFuncDef::dump(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "function definition for " << scope_path(scope_) << endl;
+      o << setw(ind) << "" << "function definition for " << scope_path(scope()) << endl;
      if (result_sig_) {
 	    o << setw(ind+2) << "" << "Return signal: ";
 	    if (result_sig_->get_signed()) o << "+";
@@ -1141,8 +1391,8 @@ void NetFuncDef::dump(ostream&o, unsigned ind) const
 	    if (port(idx)->get_signed()) o << "+";
 	    o << port(idx)->name() << endl;
      }
-      if (statement_)
-	    statement_->dump(o, ind+2);
+      if (proc_)
+	    proc_->dump(o, ind+2);
      else
 	    o << setw(ind+2) << "" << "MISSING PROCEDURAL CODE" << endl;
 }
@@ -1192,8 +1442,11 @@ void NetScope::dump(ostream&o) const
      if (is_cell()) o << " (cell)";
      if (nested_module()) o << " (nested)";
      if (program_block()) o << " (program)";
+      if (is_interface()) o << " (interface)";
      o << " " << children_.size() << " children, "
 	<< classes_.size() << " classes" << endl;
+      if (unit() && !is_unit())
+	    o << "    in compilation unit " << unit()->basename() << endl;

      for (unsigned idx = 0 ;  idx < attr_cnt() ;  idx += 1)
 	    o << "    (* " << attr_key(idx) << " = "
@@ -1281,9 +1534,9 @@ void NetScope::dump(ostream&o) const
      o << "    enum sets {" << endl;

 	/* Dump the enumerations and enum names in this scope. */
-      for (list<netenum_t*>::const_iterator cur = enum_sets_.begin()
+      for (map<const enum_type_t*,netenum_t*>::const_iterator cur = enum_sets_.begin()
 		 ; cur != enum_sets_.end() ; ++ cur) {
-	    o << "      " << *cur << endl;
+	    o << "      " << cur->second << endl;
      }
      o << "    }" << endl;

@@ -1391,6 +1644,19 @@ void NetEAccess::dump(ostream&o) const
      o << ")";
 }

+void NetEArrayPattern::dump(ostream&fd) const
+{
+      fd << "'{";
+      if (items_.size() >= 1) {
+	    if (items_[0]) fd << *items_[0];
+      }
+      for (size_t idx = 1 ; idx < items_.size() ; idx += 1) {
+	    fd << ", ";
+	    if (items_[idx]) fd << *items_[idx];
+      }
+      fd << "}";
+}
+
 void NetEBinary::dump(ostream&o) const
 {
      if (op_ == 'm' || op_ == 'M') {
@@ -1420,11 +1686,14 @@ void NetEBinary::dump(ostream&o) const
 	  case 'A':
 	    o << "~&";
 	    break;
+	  case 'e':
+	    o << "==";
+	    break;
 	  case 'E':
 	    o << "===";
 	    break;
-	  case 'e':
-	    o << "==";
+	  case 'w':
+	    o << "==?";
 	    break;
 	  case 'G':
 	    o << ">=";
@@ -1441,6 +1710,9 @@ void NetEBinary::dump(ostream&o) const
 	  case 'N':
 	    o << "!==";
 	    break;
+	  case 'W':
+	    o << "!=?";
+	    break;
 	  case 'o':
 	    o << "||";
 	    break;
@@ -1450,6 +1722,12 @@ void NetEBinary::dump(ostream&o) const
 	  case 'p':
 	    o << "**";
 	    break;
+	  case 'q':
+	    o << "->";
+	    break;
+	  case 'Q':
+	    o << "<->";
+	    break;
 	  case 'r':
 	    o << ">>";
 	    break;
@@ -1465,6 +1743,16 @@ void NetEBinary::dump(ostream&o) const
      o << ")";
 }

+void NetECast::dump(ostream&fd) const
+{
+      if (op_=='2')
+	    fd << "bool<" << expr_width() << ">(" << *expr_ << ")";
+      else if (op_=='v')
+	    fd << "logic<" << expr_width() << ">(" << *expr_ << ")";
+      else
+	    NetEUnary::dump(fd);
+}
+
 void NetEConcat::dump(ostream&o) const
 {
      if (repeat_ != 1)
@@ -1523,6 +1811,11 @@ void NetEEvent::dump(ostream&o) const
      o << "<event=" << event_->name() << ">";
 }

+void NetELast::dump(ostream&fd) const
+{
+      fd << "<last of " << sig_->name() << ">";
+}
+
 void NetENetenum::dump(ostream&o) const
 {
      o << "<netenum=" << netenum_ << ">";
@@ -1530,7 +1823,14 @@ void NetENetenum::dump(ostream&o) const

 void NetENew::dump(ostream&o) const
 {
-      o << "new <type>";
+      o << "new <type> [";
+      if (size_) size_->dump(o);
+      o << "]";
+      if (init_val_) {
+	    o << "(";
+	    init_val_->dump(o);
+	    o << ")";
+      }
 }

 void NetENull::dump(ostream&o) const
@@ -1541,6 +1841,8 @@ void NetENull::dump(ostream&o) const
 void NetEProperty::dump(ostream&o) const
 {
      o << net_->name() << ".<" << pidx_ << ">";
+      if (index_)
+	    o << "[" << *index_ << "]";
 }

 void NetEScope::dump(ostream&o) const
@@ -1,7 +1,7 @@
-#ifndef __discipline_H
-#define __discipline_H
+#ifndef IVL_discipline_H
+#define IVL_discipline_H
 /*
- * Copyright (c) 2008-2010 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2008-2014 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -74,4 +74,4 @@ extern map<perm_string,ivl_discipline_t> disciplines;
  // Map access function name to the nature that it accesses.
 extern map<perm_string,ivl_nature_t> access_function_nature;

-#endif
+#endif /* IVL_discipline_H */
@@ -19,7 +19,7 @@

 /*
 * This is a simple program to make a dosified copy of the
- * original. That is, it converts unix style line ends to DOS
+ * original. That is, it converts Unix style line ends to DOS
 * style. This is useful for installing text files.
 *
 * The exact substitution is to replace \n with \r\n. If the line
@@ -36,6 +36,7 @@ mandir = @mandir@
 dllib=@DLLIB@

 CC = @CC@
+HOSTCC := @CC@
 WINDRES = @WINDRES@
 INSTALL = @INSTALL@
 INSTALL_PROGRAM = @INSTALL_PROGRAM@
@@ -48,7 +49,8 @@ INCLUDE_PATH = -I. -I.. -I$(srcdir) -I$(srcdir)/..
 endif

 CPPFLAGS = $(INCLUDE_PATH) @CPPFLAGS@ @DEFS@
-CFLAGS = @WARNING_FLAGS@ @CFLAGS@
+CFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CC@ @CFLAGS@
+CXXFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CXX@ @CXXFLAGS@
 LDFLAGS = @LDFLAGS@

 O = main.o res.o
@@ -64,7 +66,7 @@ distclean: clean
 	rm -f Makefile config.log

 cppcheck: main.c
-	cppcheck --enable=all -f $(INCLUDE_PATH) $^
+	cppcheck --enable=all --std=posix --std=c99 --std=c++03 -f $(INCLUDE_PATH) $^

 Makefile: $(srcdir)/Makefile.in ../config.status
 	cd ..; ./config.status --file=driver-vpi/$@
@@ -80,21 +82,31 @@ config.h: $(srcdir)/config.h.in Makefile
 	sed -e 's;@IVLCC@;@CC@;' -e 's;@IVLCXX@;@CXX@;' \
 	    -e 's;@SUFFIX@;$(suffix);g' \
 	    -e 's;@IVLCFLAGS@;$(CFLAGS);' \
+	    -e 's;@IVLCXXFLAGS@;$(CXXFLAGS);' \
 	    -e 's;@SHARED@;@shared@;' $< > $@

 # Windows specific...
 res.rc: $(srcdir)/res.rc.in ../version.exe
-	sed -e 's;@PRODUCTVERSION@;'`../version.exe '%M,%m,%n,0'`';' \
+	sed -e 's;@PRODUCTVERSION@;'`../version.exe '%M,%n,0,0'`';' \
 	$(srcdir)/res.rc.in > $@

 res.o: res.rc
 	$(WINDRES) -i res.rc -o res.o
 #

-install: all installdirs $(bindir)/iverilog-vpi$(suffix)@EXEEXT@
+install: all installdirs installfiles

-$(bindir)/iverilog-vpi$(suffix)@EXEEXT@: ./iverilog-vpi@EXEEXT@
+F = ./iverilog-vpi@EXEEXT@
+
+installfiles: $(F) | installdirs
 	$(INSTALL_PROGRAM) ./iverilog-vpi@EXEEXT@ "$(bindir)/iverilog-vpi$(suffix)@EXEEXT@"
+ifeq (@WIN32@,yes)
+ifneq ($(HOSTCC),$(CC))
+	$(INSTALL_PROGRAM) $(shell $(HOSTCC) --print-file-name=libwinpthread-1.dll) "$(DESTDIR)$(bindir)"
+	$(INSTALL_PROGRAM) $(shell $(HOSTCC) --print-file-name=libgcc_s_sjlj-1.dll) "$(DESTDIR)$(bindir)"
+	$(INSTALL_PROGRAM) $(shell $(HOSTCC) --print-file-name=libstdc++-6.dll) "$(DESTDIR)$(bindir)"
+endif
+endif

 installdirs: $(srcdir)/../mkinstalldirs
 	$(srcdir)/../mkinstalldirs "$(bindir)"
@@ -4,6 +4,7 @@
 #define IVERILOG_VPI_CC        "@IVLCC@"
 #define IVERILOG_VPI_CXX       "@IVLCXX@"
 #define IVERILOG_VPI_CFLAGS    " @IVLCFLAGS@"
+#define IVERILOG_VPI_CXXFLAGS  " @IVLCXXFLAGS@"
 #define IVERILOG_VPI_LDFLAGS   "@SHARED@"
 #define IVERILOG_VPI_LDLIBS    "-lveriuser@SUFFIX@ -lvpi@SUFFIX@"
 #define IVERILOG_SUFFIX        "@SUFFIX@"
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2002 Gus Baldauf (gus@picturel.com)
+ * Copyright (c) 2015 Martin Whitaker
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -20,7 +21,7 @@
 /*
 *	iverilog-vpi.c
 *
- *	this program provides the functionality of iverilog-vpi.sh under Win32
+ *	this program provides the functionality of iverilog-vpi.sh under Windows
 */

 #include <stdio.h>
@@ -32,7 +33,7 @@

 #include <windows.h>

-static void setup_ivl_environment();
+static void setup_ivl_environment(void);
 static void assign(char **ptr, char *str);

 /* The compile options: compiler, flags, etc. are in here */
@@ -43,16 +44,17 @@ static void assign(char **ptr, char *str);
 static struct global_strings {
 	char *pCCSRC;		/* list of C source files (*.c) */
 	char *pCXSRC;		/* list of C++ source files (*.cc, *.cpp) */
-	char *pOBJ;			/* list of object files */
-	char *pLIB;			/* list of library files */
-	char *pINCS;			/* list of include directories */
-	char *pDEFS;			/* list of definitions */
-	char *pOUT;			/* output file name (.vpi extension), if 0 length then no source files specified */
+	char *pOBJ;		/* list of object files */
+	char *pLIB;		/* list of library files */
+	char *pINCS;		/* list of include directories */
+	char *pDEFS;		/* list of definitions */
+	char *pOUT;		/* output file name (.vpi extension), if 0 length then no source files specified */
 	char *pMINGW;		/* path to MinGW directory */
-	char *pIVL;			/* path to IVL directory */
-	char *pCFLAGS;		/* CFLAGS option */
-	char *pLDLIBS;		/* LDLIBS option */
-	char *pNewPath;		/* new PATH environment variable setting */
+	char *pIVL;		/* path to IVL directory */
+	char *pCCFLAGS;		/* compiler flags for compiling C source files */
+	char *pCXFLAGS;		/* compiler flags for compiling C++ source files */
+	char *pLDLIBS;		/* linker flags for final linking stage */
+	char *pCCNAME;		/* base name of compiler */
 	char *pLD;		/* what to use for a linker */
 } gstr;

@@ -75,21 +77,21 @@ static void myExit(int exitVal)
 	deInitDynString(gstr.pOUT);
 	deInitDynString(gstr.pMINGW);
 	deInitDynString(gstr.pIVL);
-	deInitDynString(gstr.pCFLAGS);
+	deInitDynString(gstr.pCCFLAGS);
+	deInitDynString(gstr.pCXFLAGS);
 	deInitDynString(gstr.pLDLIBS);
-	deInitDynString(gstr.pNewPath);
-	free(gstr.pLD);
+	deInitDynString(gstr.pCCNAME);
+	deInitDynString(gstr.pLD);

 	exit(exitVal);
 }

 /* display usage summary and exit */

-static void usage()
+static void usage(void)
 {
-	fprintf(stderr,"usage: iverilog-vpi" IVERILOG_SUFFIX " [src and obj files]...\n");
-	fprintf(stderr,"   or  iverilog-vpi" IVERILOG_SUFFIX " -mingw=dir\n");
-	fprintf(stderr,"   or  iverilog-vpi" IVERILOG_SUFFIX " -ivl=dir\n");
+	fprintf(stderr, "usage: iverilog-vpi" IVERILOG_SUFFIX " [options] [src and obj files]...\n");
+	fprintf(stderr, "   or  iverilog-vpi" IVERILOG_SUFFIX " -mingw=dir\n");
 	myExit(1);
 }

@@ -98,7 +100,7 @@ static void initDynString(char **str)
 	*str = (char *) malloc(1);

 	if (!*str) {
-		fprintf(stderr,"error: out of memory\n");
+		fprintf(stderr, "error: out of memory\n");
 		myExit(4);
 	}

@@ -107,8 +109,10 @@ static void initDynString(char **str)

 /* initialize dynamic memory buffers */

-static void init()
+static void init(void)
 {
+	char *ptr;
+
 	initDynString(&gstr.pCCSRC);
 	initDynString(&gstr.pCXSRC);
 	initDynString(&gstr.pOBJ);
@@ -118,9 +122,17 @@ static void init()
 	initDynString(&gstr.pOUT);
 	initDynString(&gstr.pMINGW);
 	initDynString(&gstr.pIVL);
-	initDynString(&gstr.pCFLAGS);
+	initDynString(&gstr.pCCFLAGS);
+	initDynString(&gstr.pCXFLAGS);
 	initDynString(&gstr.pLDLIBS);
-	initDynString(&gstr.pNewPath);
+	initDynString(&gstr.pCCNAME);
+	initDynString(&gstr.pLD);
+
+	  /* Get the base name of the C compiler. */
+	assign(&gstr.pCCNAME, IVERILOG_VPI_CC);
+	ptr = strchr(gstr.pCCNAME, ' ');
+	if (ptr != NULL) *ptr = '\0';
+
 	  /* By default use the C compiler to link the programs. */
 	assign(&gstr.pLD, IVERILOG_VPI_CC);
 }
@@ -136,7 +148,7 @@ static int endsIn (char *end, char *str)

 	ext = str + (strlen(str) - strlen(end));

-	return stricmp(end,ext) ? 0 : 1;
+	return stricmp(end, ext) ? 0 : 1;
 }

 /* return true if "str" begins with "prefix", case insensitive */
@@ -146,35 +158,35 @@ static int startsWith (char *prefix, char *str)
 	if (strlen(prefix) >= strlen(str))
 		return 0;

-	return strnicmp(prefix,str,strlen(prefix)) ? 0 : 1;
+	return strnicmp(prefix, str, strlen(prefix)) ? 0 : 1;
 }

 /* append "app" to "ptr", allocating memory as needed    */
 /*   if count is zero, then copy all characters of "app" */

-static void appendn (char **ptr, char *app, int count)
+static void appendn (char **ptr, char *app, size_t count)
 {
 	char *nptr = (char *) realloc(*ptr, strlen(*ptr) +
-                                            (count?count:strlen(app)) + 1);
+                                            (count ? count : strlen(app)) + 1);

 	if (nptr == NULL) {
-		fprintf(stderr,"error: out of memory\n");
+		fprintf(stderr, "error: out of memory\n");
 		free(*ptr);
 		myExit(4);
 	}
 	*ptr = nptr;

 	if (count)
-		strncat(*ptr,app,count);
+		strncat(*ptr, app, count);
 	else
-		strcat(*ptr,app);
+		strcat(*ptr, app);
 }

 /* append "app" to "ptr", allocating memory as needed    */

 static void append (char **ptr, char *app)
 {
-	appendn(ptr,app,0);
+	appendn(ptr, app, 0);
 }

 /* if the string does not end with a backslash, add one */
@@ -182,36 +194,36 @@ static void append (char **ptr, char *app)
 static void appendBackSlash(char **str)
 {
 	if ((*str)[strlen(*str)-1] != '\\')
-		append(str,"\\");
+		append(str, "\\");
 }

 /* copy count characters of "str" to "ptr", allocating memory as needed */
 /*   if count is zero, then copy all characters of "str"                */

-static void assignn (char **ptr, char *str, int count)
+static void assignn (char **ptr, char *str, size_t count)
 {
-	char *nptr = (char *) realloc(*ptr, (count?count:strlen(str)) + 1);
+	char *nptr = (char *) realloc(*ptr, (count ? count : strlen(str)) + 1);

 	if (nptr == NULL) {
-		fprintf(stderr,"error: out of memory\n");
+		fprintf(stderr, "error: out of memory\n");
 		free(*ptr);
 		myExit(4);
 	}
 	*ptr = nptr;

 	if (count) {
-		strncpy(*ptr,str,count);
+		strncpy(*ptr, str, count);
 		(*ptr)[count] = 0;
 	}
 	else
-		strcpy(*ptr,str);
+		strcpy(*ptr, str);
 }

 /* copy count characters of "str" to "ptr", allocating memory as needed */

 static void assign (char **ptr, char *str)
 {
-	assignn(ptr,str,0);
+	assignn(ptr, str, 0);
 }

 /* get a copy of a Icarus Verilog registry string key */
@@ -223,11 +235,11 @@ static int GetRegistryKey(char *key, char **value)
 	char *regKeyBuffer;
 	DWORD regKeyType, regKeySize;

-	lrv = RegOpenKeyEx(HKEY_LOCAL_MACHINE,"Software\\Icarus Verilog",0,KEY_QUERY_VALUE,&hkKey);
+	lrv = RegOpenKeyEx(HKEY_LOCAL_MACHINE, "Software\\Icarus Verilog", 0, KEY_QUERY_VALUE, &hkKey);
 	if (lrv != ERROR_SUCCESS)
 		return 0;

-	lrv = RegQueryValueEx(hkKey,key,NULL,&regKeyType,NULL,&regKeySize);
+	lrv = RegQueryValueEx(hkKey, key, NULL, &regKeyType, NULL, &regKeySize);
 	if ((lrv != ERROR_SUCCESS) || (regKeyType != REG_SZ) || (!regKeySize)) {
 		lrv = RegCloseKey(hkKey);
 		return 0;
@@ -236,7 +248,7 @@ static int GetRegistryKey(char *key, char **value)
 	regKeyBuffer = (char *) malloc(regKeySize+1);
 	if (!regKeyBuffer) {
 		lrv = RegCloseKey(hkKey);
-		fprintf(stderr,"error: out of memory\n");
+		fprintf(stderr, "error: out of memory\n");
 		myExit(4);
 	}
 	regKeyBuffer[regKeySize] = 0;		/* makes sure there is a trailing NULL */
@@ -252,7 +264,7 @@ static int GetRegistryKey(char *key, char **value)

 	RegCloseKey(hkKey);

-	assign(value,regKeyBuffer);
+	assign(value, regKeyBuffer);
 	free(regKeyBuffer);

 	return 1;
@@ -262,27 +274,30 @@ static int GetRegistryKey(char *key, char **value)

 static void SetRegistryKey(char *key, char *value)
 {
+	long lrv;
 	HKEY hkKey;
 	DWORD res;

-	if (RegCreateKeyEx(
-		HKEY_LOCAL_MACHINE,
-		"Software\\Icarus Verilog",
-		0,
-		"",
-		REG_OPTION_NON_VOLATILE,
-		KEY_ALL_ACCESS,NULL,
-		&hkKey,
-		&res) != ERROR_SUCCESS)
-			return;
+	lrv = RegCreateKeyEx(HKEY_LOCAL_MACHINE, "Software\\Icarus Verilog", 0, "",
+			     REG_OPTION_NON_VOLATILE, KEY_ALL_ACCESS, NULL, &hkKey, &res);
+	if (lrv != ERROR_SUCCESS) {
+		char message[1024];
+		FormatMessage(FORMAT_MESSAGE_FROM_SYSTEM, NULL, lrv, LANG_USER_DEFAULT,
+			      message, sizeof(message), NULL);
+		fprintf(stderr, "error: couldn't write to registry - %s\n", message);
+		if (lrv == ERROR_ACCESS_DENIED) {
+			fprintf(stderr, "       try running as administrator\n");
+		}
+		return;
+	}

 	/* This needs an unsigned char *, but for MinGW the char is signed. */
 	RegSetValueEx(hkKey, key, 0, REG_SZ, (unsigned char *) value,
 	              strlen(value)+1);
 	RegCloseKey(hkKey);

-	printf("info:  storing %s in Windows' registry entry\n",value);
-	printf("       HKEY_LOCAL_MACHINE\\Software\\Icarus Verilog\\%s\n",key);
+	printf("info:  storing %s in Windows' registry entry\n", value);
+	printf("       HKEY_LOCAL_MACHINE\\Software\\Icarus Verilog\\%s\n", key);
 }

 /* parse the command line, assign results to global variable strings */
@@ -299,7 +314,6 @@ static int parse(int argc, char *argv[])
 	char lib_option[]   = "-l";
 	char inc_option[]   = "-I";
 	char mingw_option[] = "-mingw=";
-	char ivl_option[]   = "-ivl=";
 	char def_option[]   = "-D";

 	if (argc == 1) return 0;
@@ -339,7 +353,7 @@ static int parse(int argc, char *argv[])
 		  /* Check for compiled object files */
 		else if (endsIn(dot_o_ext, argv[idx])) {
 			++srcFileCnt;
-			append(&gstr.pOBJ," ");
+			append(&gstr.pOBJ, " ");
 			append(&gstr.pOBJ, argv[idx]);
 			if (!*gstr.pOUT)
 			   assignn(&gstr.pOUT, argv[idx],
@@ -349,10 +363,6 @@ static int parse(int argc, char *argv[])
 		else if (startsWith(mingw_option, argv[idx]))
 			assignn(&gstr.pMINGW, argv[idx]+sizeof(mingw_option)-1,
 			        strlen(argv[idx])-(sizeof(mingw_option)-1));
-		  /* Check for the -ivl   option */
-		else if (startsWith(ivl_option, argv[idx]))
-			assignn(&gstr.pIVL, argv[idx]+sizeof(ivl_option)-1,
-			        strlen(argv[idx])-(sizeof(ivl_option)-1));
 		  /* Check for the --name option */
 		else if (startsWith(name_option, argv[idx])) {
 			assignn(&gstr.pOUT, argv[idx]+sizeof(name_option)-1,
@@ -376,7 +386,7 @@ static int parse(int argc, char *argv[])
 		  /* Check for the --cflags option */
 		else if (stricmp("--cflags", argv[idx]) == 0) {
 			setup_ivl_environment();
-			printf("%s\n", gstr.pCFLAGS);
+			printf("%s\n", gstr.pCCFLAGS);
 			myExit(0);
 		}
 		  /* Check for the --ldflags option */
@@ -393,7 +403,7 @@ static int parse(int argc, char *argv[])
 		  /* Check for the --install-dir option */
 		else if (stricmp("--install-dir", argv[idx]) == 0) {
 			setup_ivl_environment();
-			printf("%s\\\\lib\\\\ivl" IVERILOG_SUFFIX "\\\\.\n", gstr.pIVL);
+			printf("%s\\lib\\ivl" IVERILOG_SUFFIX "\\.\n", gstr.pIVL);
 			myExit(0);
 		}
 		  /* This is different than iverilog-vpi.sh, we don't
@@ -402,15 +412,16 @@ static int parse(int argc, char *argv[])
 	}

 	  /* In case there is a --name without source/object files */
-	if (0 == srcFileCnt) assign(&gstr.pOUT,"");
+	if (0 == srcFileCnt) assign(&gstr.pOUT, "");

-	  /* Normally it's an error if there are no source or object files */
-	  /* Unless we are setting the IVL or MinGW registry entries */
-	if (!*gstr.pOUT) {
-		if (!*gstr.pMINGW && !*gstr.pIVL) return 0;
-	} else
+	if (*gstr.pOUT) {
 		  /* We have a valid result file so add the .vpi extension */
 		append(&gstr.pOUT, ".vpi");
+	} else {
+		  /* Unless we are setting the MinGW registry entry, it's
+		     an error if there are no source or object files */
+		if (!*gstr.pMINGW) return 0;
+	}

 	return 1;
 }
@@ -421,58 +432,27 @@ static void checkMingwDir(char *root)
 {
 	int irv;
 	struct _stat stat_buf;
-
-	char *path, *comp, *cp;
-	initDynString(&path);
-	assign(&path,gstr.pMINGW);
-	appendBackSlash(&path);
-	append(&path,"bin\\");
-	/* Get just the compiler name (the first word) */
-	comp = strdup(IVERILOG_VPI_CC);
-	cp = strchr(comp, ' ');
-	if (cp != NULL) *cp = '\0';
-        append(&path, comp);
-	append(&path,".exe");
-        free(comp);
-
-	irv = _stat(path,&stat_buf);
-	deInitDynString(path);
-
-	if (irv) {
-		fprintf(stderr,"error: %s does not appear to be the valid root directory\n",root);
-		fprintf(stderr,"       of MinGW.  Use the -mingw option of iverilog-vpi.exe to\n");
-		fprintf(stderr,"       point to the MinGW root directory.  For a Windows command\n");
-		fprintf(stderr,"       shell the option would be something like -mingw=c:\\mingw\n");
-		fprintf(stderr,"       For a Cygwin shell the option would be something like\n");
-		fprintf(stderr,"       -mingw=c:\\\\mingw\n");
-		myExit(5);
-	}
-}
-
-/* do minimal check that the Icarus Verilog root directory looks valid */
-
-static void checkIvlDir(char *root)
-{
-	int irv;
-	struct _stat stat_buf;
-
 	char *path;
+
 	initDynString(&path);
-	assign(&path,gstr.pIVL);
+	assign(&path, gstr.pMINGW);
 	appendBackSlash(&path);
-	append(&path,"bin\\vvp" IVERILOG_SUFFIX ".exe");
+	append(&path, "bin\\");
+        append(&path, gstr.pCCNAME);
+	append(&path, ".exe");

 	irv = _stat(path,&stat_buf);
 	deInitDynString(path);

 	if (irv) {
-		fprintf(stderr,"error: %s does not appear to be the valid root directory of\n",root);
-		fprintf(stderr,"       Icarus Verilog.  Use the -ivl option of iverilog-vpi" IVERILOG_SUFFIX " to\n");
-		fprintf(stderr,"       point to the Icarus Verilog root directory.  For a Windows\n");
-		fprintf(stderr,"       command shell the option would be something like -ivl=c:\\iverilog\n");
-		fprintf(stderr,"       For a Cygwin shell the option would be something like\n");
-		fprintf(stderr,"       -ivl=c:\\\\iverilog\n");
-		myExit(6);
+		fprintf(stderr, "error: %s\n", root);
+		fprintf(stderr, "       does not appear to be the valid root directory of\n");
+		fprintf(stderr, "       MinGW.  Use the -mingw option of iverilog-vpi.exe to\n");
+		fprintf(stderr, "       point to the MinGW root directory.  For a Windows command\n");
+		fprintf(stderr, "       shell the option would be something like -mingw=c:\\mingw\n");
+		fprintf(stderr, "       For a Cygwin shell the option would be something like\n");
+		fprintf(stderr, "       -mingw=c:\\\\mingw\n");
+		myExit(5);
 	}
 }

@@ -480,68 +460,98 @@ static void checkIvlDir(char *root)

 #define IVL_REGKEY_MINGW "MingwDir"

-static void setup_mingw_environment()
+static void setup_mingw_environment(void)
 {
-	char *pOldPATH = getenv("PATH");		/* get current path */
+	char buffer[1];		/* doesn't matter how big this is, as we don't use the result */
+	char *path;

 	if (*gstr.pMINGW) {
 		checkMingwDir(gstr.pMINGW);
-		SetRegistryKey(IVL_REGKEY_MINGW,gstr.pMINGW);
-	} else if (!GetRegistryKey(IVL_REGKEY_MINGW,&gstr.pMINGW)) {
-			fprintf(stderr,"error: can not locate the MinGW root directory, use the -mingw option of\n");
-			fprintf(stderr,"       iverilog-vpi.exe to point to the MinGW root directory.  For\n");
-			fprintf(stderr,"       a Windows command shell the option would be something like\n");
-			fprintf(stderr,"       -mingw=c:\\mingw  For a Cygwin shell the option would be\n");
-			fprintf(stderr,"       something like -mingw=c:\\\\mingw\n");
-			myExit(5);
-		}
+		if (!*gstr.pOUT) SetRegistryKey(IVL_REGKEY_MINGW, gstr.pMINGW);
+
+	} else if (GetRegistryKey(IVL_REGKEY_MINGW, &gstr.pMINGW)) {
+		checkMingwDir(gstr.pMINGW);
+
+	} else if (SearchPath(NULL, gstr.pCCNAME, ".exe", sizeof(buffer), buffer, NULL)) {
+		return;
+
+	} else {
+		fprintf(stderr, "error: cannot locate the MinGW C compiler - either add its location\n");
+		fprintf(stderr, "       to the PATH environment variable or use the -mingw option of\n");
+		fprintf(stderr, "       iverilog-vpi.exe to point to the MinGW root directory.  For\n");
+		fprintf(stderr, "       a Windows command shell the option would be something like\n");
+		fprintf(stderr, "       -mingw=c:\\mingw  For a Cygwin shell the option would be\n");
+		fprintf(stderr, "       something like -mingw=c:\\\\mingw\n");
+		myExit(5);
+	}

 	  /* Create new path with MinGW in it */
-	assign(&gstr.pNewPath,"PATH=");
-	append(&gstr.pNewPath,gstr.pMINGW);
-	appendBackSlash(&gstr.pNewPath);
-	append(&gstr.pNewPath, "\\");
-	append(&gstr.pNewPath,"bin;");
-	append(&gstr.pNewPath,pOldPATH);
+	initDynString(&path);
+	assign(&path, "PATH=");
+	append(&path, gstr.pMINGW);
+	appendBackSlash(&path);
+	append(&path, "bin;");
+	append(&path, getenv("PATH"));

 	  /* Place new path in environment */
-	_putenv(gstr.pNewPath);
+	_putenv(path);
+	deInitDynString(path);
 }

-/* see if we can find iverilog root */
+/* find the iverilog root and initialise the compiler options */

-#define IVL_REGKEY_IVL   "InstallDir"
-
-static void setup_ivl_environment()
+static void setup_ivl_environment(void)
 {
-	if (*gstr.pIVL) {
-		checkIvlDir(gstr.pIVL);
-		SetRegistryKey(IVL_REGKEY_IVL,gstr.pIVL);
-	} else if (!GetRegistryKey(IVL_REGKEY_IVL,&gstr.pIVL)) {
-			fprintf(stderr,"error: can not locate the Icarus Verilog root directory, use the -ivl option\n");
-			fprintf(stderr,"       of iverilog-vpi" IVERILOG_SUFFIX " to point to the Icarus Verilog root directory.\n");
-			fprintf(stderr,"       For a Windows command shell the option would be something like\n");
-			fprintf(stderr,"       -ivl=c:\\iverilog  For a Cygwin shell the option would be something\n");
-			fprintf(stderr,"       like -ivl=c:\\\\iverilog\n");
-			myExit(6);
-		}
+	char path[4096];
+	char *ptr;

-	  /* Build up the CFLAGS option string */
-	assign(&gstr.pCFLAGS,IVERILOG_VPI_CFLAGS " -I\"");
-	append(&gstr.pCFLAGS,gstr.pIVL);
-	appendBackSlash(&gstr.pCFLAGS);
-	append(&gstr.pCFLAGS,"\\include\\\\iverilog\"" IVERILOG_SUFFIX);
+	  /* Extract the Icarus Verilog root directory from the path to the
+	     command. The command path will look something like this:
+
+		C:\iverilog\bin\iverilog-vpi.exe
+
+	     The corresponding root directory is
+
+		C:\iverilog
+
+	     so we chop off the file name and the last directory. */
+	GetModuleFileName(NULL, path, sizeof(path));
+	ptr = strrchr(path, '\\');
+	if (!ptr) {
+		fprintf(stderr, "error: couldn't find start of program name in command path '%s'\n", path);
+		myExit(6);
+	}
+	*ptr = 0;
+	ptr = strrchr(path, '\\');
+	if (!ptr) {
+		fprintf(stderr, "error: couldn't find start of bin directory in command path '%s'\n", path);
+		myExit(6);
+	}
+	*ptr = 0;
+	assign(&gstr.pIVL, path);
+
+	  /* Build up the CCFLAGS option string */
+	assign(&gstr.pCCFLAGS, IVERILOG_VPI_CFLAGS " -I\"");
+	append(&gstr.pCCFLAGS, gstr.pIVL);
+	appendBackSlash(&gstr.pCCFLAGS);
+	append(&gstr.pCCFLAGS, "include\\iverilog\"" IVERILOG_SUFFIX);
+
+	  /* Build up the CXFLAGS option string */
+	assign(&gstr.pCXFLAGS, IVERILOG_VPI_CXXFLAGS " -I\"");
+	append(&gstr.pCXFLAGS, gstr.pIVL);
+	appendBackSlash(&gstr.pCXFLAGS);
+	append(&gstr.pCXFLAGS, "include\\iverilog\"" IVERILOG_SUFFIX);

 	  /* Build up the LDFLAGS option string */
-	assign(&gstr.pLDLIBS,"-L\"");
-	append(&gstr.pLDLIBS,gstr.pIVL);
+	assign(&gstr.pLDLIBS, "-L\"");
+	append(&gstr.pLDLIBS, gstr.pIVL);
 	appendBackSlash(&gstr.pLDLIBS);
-	append(&gstr.pLDLIBS,"\\lib\" " IVERILOG_VPI_LDLIBS);
+	append(&gstr.pLDLIBS, "lib\" " IVERILOG_VPI_LDLIBS);
 }

 /* compile source modules */

-static void compile(char *pSource, char **pObject, int *compile_errors, char *compiler)
+static void compile(char *pSource, char *pFlags, char **pObject, int *compile_errors, char *compiler)
 {
 	char *ptr1 = pSource;
 	char *ptr2 = strchr(ptr1, ' ');
@@ -568,7 +578,7 @@ static void compile(char *pSource, char **pObject, int *compile_errors, char *co
 		append(&buf, " ");
 		append(&buf, gstr.pDEFS);
 		append(&buf, " ");
-		append(&buf, gstr.pCFLAGS);
+		append(&buf, pFlags);
 		append(&buf, " ");
 		append(&buf, gstr.pINCS);
 		append(&buf, " ");
@@ -593,27 +603,22 @@ static void compile(char *pSource, char **pObject, int *compile_errors, char *co

 /* using the global strings, compile and link */

-static void compile_and_link()
+static void compile_and_link(void)
 {
 	char *buf=0;
 	int iRet, compile_errors = 0;

 	  /* To make the output match iverilog-vpi.sh do not print out the
 	   * root directories */
-
 //	printf("MinGW root directory:  %s.\n", gstr.pMINGW);
-	checkMingwDir(gstr.pMINGW);
-
-//	printf("Icarus Verilog root directory:  %s.\n", gstr.pIVL);
-	checkIvlDir(gstr.pIVL);

 	  /* compile the C source files (*.c) */
-	compile(gstr.pCCSRC, &gstr.pOBJ, &compile_errors, IVERILOG_VPI_CC );
+	compile(gstr.pCCSRC, gstr.pCCFLAGS, &gstr.pOBJ, &compile_errors, IVERILOG_VPI_CC );
 	  /* compile the C++ source files (*.cc, *.cpp) */
-	compile(gstr.pCXSRC, &gstr.pOBJ, &compile_errors, IVERILOG_VPI_CXX);
+	compile(gstr.pCXSRC, gstr.pCXFLAGS, &gstr.pOBJ, &compile_errors, IVERILOG_VPI_CXX);

 	if (compile_errors) {
-		fprintf(stderr,"iverilog-vpi: %d file(s) failed to compile.\n",
+		fprintf(stderr, "iverilog-vpi: %d file(s) failed to compile.\n",
 		        compile_errors);
 		myExit(2);
 	}
@@ -644,7 +649,7 @@ int main(int argc, char *argv[])
 {
 	init();

-	if (!parse(argc,argv)) usage();
+	if (!parse(argc, argv)) usage();

 	setup_mingw_environment();
 	setup_ivl_environment();
@@ -49,7 +49,7 @@ INCLUDE_PATH = -I. -I.. -I$(srcdir) -I$(srcdir)/..
 endif

 CPPFLAGS = $(INCLUDE_PATH) @CPPFLAGS@ @DEFS@
-CFLAGS = @WARNING_FLAGS@ @CFLAGS@
+CFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CC@ @CFLAGS@
 LDFLAGS = @LDFLAGS@

 O = main.o substit.o cflexor.o cfparse.o
@@ -67,7 +67,11 @@ distclean: clean
 	rm -f Makefile config.log

 cppcheck: $(O:.o=.c)
-	cppcheck --enable=all -f $(INCLUDE_PATH) $^
+	cppcheck --enable=all --std=posix --std=c99 --std=c++03 -f \
+	         -UYY_USER_INIT \
+	         -UYYPARSE_PARAM -UYYPRINT -Ushort -Uyyoverflow \
+	         -UYYTYPE_INT8 -UYYTYPE_INT16 -UYYTYPE_UINT8 -UYYTYPE_UINT16 \
+	         $(INCLUDE_PATH) $^

 Makefile: $(srcdir)/Makefile.in ../config.status
 	cd ..; ./config.status --file=driver/$@
@@ -81,10 +85,9 @@ iverilog@EXEEXT@: $O
 cflexor.c: $(srcdir)/cflexor.lex
 	$(LEX) -s -t $< > $@

-# Build this in two steps to avoid parallel build issues (see pr3462585)
-cfparse.c: $(srcdir)/cfparse.y
-	$(YACC) --verbose -t -p cf -d -o $@ $<
-cfparse.h: cfparse.c
+# Use pattern rules to avoid parallel build issues (see pr3462585)
+cfparse%c cfparse%h: $(srcdir)/cfparse%y
+	$(YACC) --verbose -t -p cf -d -o cfparse.c $<

 %.o: %.c
 	$(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c $< -o $*.o
@@ -108,32 +111,35 @@ iverilog.pdf: iverilog.ps

 ifeq (@MINGW32@,yes)
 ifeq ($(MAN),none)
-INSTALL_DOC = $(mandir)/man1/iverilog$(suffix).1
+INSTALL_DOC = installman
 else
 ifeq ($(PS2PDF),none)
-INSTALL_DOC = $(mandir)/man1/iverilog$(suffix).1
+INSTALL_DOC = installman
 else
-INSTALL_DOC = $(prefix)/iverilog$(suffix).pdf $(mandir)/man1/iverilog$(suffix).1
+INSTALL_DOC = installpdf installman
 all: iverilog.pdf
 endif
 endif
 INSTALL_DOCDIR = $(mandir)/man1
 else
-INSTALL_DOC = $(mandir)/man1/iverilog$(suffix).1
+INSTALL_DOC = installman
 INSTALL_DOCDIR = $(mandir)/man1
 endif

-install: all installdirs $(bindir)/iverilog$(suffix)@EXEEXT@ $(INSTALL_DOC)
+install: all installdirs installfiles

-$(bindir)/iverilog$(suffix)@EXEEXT@: ./iverilog@EXEEXT@
-	$(INSTALL_PROGRAM) ./iverilog@EXEEXT@ "$(DESTDIR)$(bindir)/iverilog$(suffix)@EXEEXT@"
+F = ./iverilog@EXEEXT@ \
+	$(INSTALL_DOC)

-$(mandir)/man1/iverilog$(suffix).1: iverilog.man
+installman: iverilog.man installdirs
 	$(INSTALL_DATA) iverilog.man "$(DESTDIR)$(mandir)/man1/iverilog$(suffix).1"

-$(prefix)/iverilog$(suffix).pdf: iverilog.pdf
+installpdf: iverilog.pdf installdirs
 	$(INSTALL_DATA) iverilog.pdf "$(DESTDIR)$(prefix)/iverilog$(suffix).pdf"

+installfiles: $(F) | installdirs
+	$(INSTALL_PROGRAM) ./iverilog@EXEEXT@ "$(DESTDIR)$(bindir)/iverilog$(suffix)@EXEEXT@"
+
 installdirs: $(srcdir)/../mkinstalldirs
 	$(srcdir)/../mkinstalldirs "$(DESTDIR)$(bindir)" "$(DESTDIR)$(INSTALL_DOCDIR)"

@@ -4,7 +4,7 @@

 %{
 /*
- * Copyright (c) 2001-2009 Stephen Williams ([email protected])
+ * Copyright (c) 2001-2017 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -22,11 +22,13 @@
 *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 */

-# include  "cfparse.h"
 # include  "cfparse_misc.h"
+# include  "cfparse.h"
 # include  "globals.h"
 # include  <string.h>

+char *current_file = NULL;
+
 static int comment_enter;
 static char* trim_trailing_white(char*txt, int trim);

@@ -92,6 +94,8 @@ int cmdfile_stack_ptr = 0;

 "+vhdl-libdir+" { BEGIN(PLUS_ARGS); return TOK_VHDL_LIBDIR; }

+"+width-cap+" { BEGIN(PLUS_ARGS); return TOK_WIDTH_CAP; }
+
  /* If it is not any known plus-flag, return the generic form. */
 "+"[^\n \t\b\f\r+]* {
      cflval.text = strdup(yytext);
@@ -122,7 +126,8 @@ int cmdfile_stack_ptr = 0;
 "-c" { return TOK_Dc; }
 "-f" { return TOK_Dc; }

-  /* Notice the -v flag. */
+  /* Notice the -l or -v flag. */
+"-l" { return TOK_Dv; }
 "-v" { return TOK_Dv; }

  /* Notice the -y flag. */
@@ -245,11 +250,11 @@ void cfreset(FILE*fd, const char*path)
 /*
 * Modern version of flex (>=2.5.9) can clean up the scanner data.
 */
-void destroy_lexor()
+void destroy_lexor(void)
 {
 # ifdef FLEX_SCANNER
 #   if YY_FLEX_MAJOR_VERSION >= 2 && YY_FLEX_MINOR_VERSION >= 5
-#     if defined(YY_FLEX_SUBMINOR_VERSION) && YY_FLEX_SUBMINOR_VERSION >= 9
+#     if YY_FLEX_MINOR_VERSION > 5 || defined(YY_FLEX_SUBMINOR_VERSION) && YY_FLEX_SUBMINOR_VERSION >= 9
    yylex_destroy();
 #     endif
 #   endif
@@ -1,6 +1,6 @@
 %{
 /*
- * Copyright (c) 2001-2011 Stephen Williams ([email protected])
+ * Copyright (c) 2001-2014 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -61,6 +61,7 @@ static void translate_file_name(char*text)
 %token TOK_Da TOK_Dc TOK_Dv TOK_Dy
 %token TOK_DEFINE TOK_INCDIR TOK_INTEGER_WIDTH TOK_LIBDIR TOK_LIBDIR_NOCASE
 %token TOK_LIBEXT TOK_PARAMETER TOK_TIMESCALE TOK_VHDL_WORK TOK_VHDL_LIBDIR
+%token TOK_WIDTH_CAP
 %token <text> TOK_PLUSARG TOK_PLUSWORD TOK_STRING

 %%
@@ -191,6 +192,13 @@ item
 		  free(tmp);
 		}

+	| TOK_WIDTH_CAP TOK_PLUSARG
+                { char*tmp = substitutions($2);
+		  free($2);
+		  width_cap = strtoul(tmp,0,10);
+		  free(tmp);
+		}
+
  /* The +<word> tokens that are not otherwise matched, are
     ignored. The skip_args rule arranges for all the argument words
     to be consumed. */
@@ -213,7 +221,7 @@ item
 		}

 	| error
-		{ fprintf(stderr, "Error: unable to parse line %d in "
+		{ fprintf(stderr, "Error: unable to parse line %u in "
 		          "%s.\n", cflloc.first_line, current_file);
 		  return 1;
 		}
@@ -262,5 +270,6 @@ skip_arg : TOK_PLUSARG

 int yyerror(const char*msg)
 {
+	(void)msg; /* Parameter is not used. */
 	return 0;
 }
@@ -1,7 +1,7 @@
-#ifndef __cfparse_misc_H
-#define __cfparse_misc_H
+#ifndef IVL_cfparse_misc_H
+#define IVL_cfparse_misc_H
 /*
- * Copyright (c) 2001-2009 Picture Elements, Inc.
+ * Copyright (c) 2001-2014 Picture Elements, Inc.
 *    Stephen Williams (steve@picturel.com)
 *
 *    This source code is free software; you can redistribute it
@@ -38,7 +38,7 @@ int cflex(void);
 int cferror(const char *);
 int cfparse(void);
 void switch_to_command_file(const char *);
-void destroy_lexor();
-char *current_file;
+void destroy_lexor(void);
+extern char *current_file;

-#endif
+#endif /* IVL_cfparse_misc_H */
@@ -1,7 +1,7 @@
-#ifndef __globals_H
-#define __globals_H
+#ifndef IVL_globals_H
+#define IVL_globals_H
 /*
- * Copyright (c) 2000-2009 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -24,6 +24,9 @@
  /* This is the integer-width argument that will be passed to ivl. */
 extern unsigned integer_width;

+  /* This is the width-cap argument that will be passed to ivl. */
+extern unsigned width_cap;
+
 extern const char*vhdlpp_work;
 extern const char**vhdlpp_libdir;
 extern unsigned vhdlpp_libdir_cnt;
@@ -51,4 +54,4 @@ extern void process_parameter(const char*name);
  /* Set the default timescale for the simulator. */
 extern void process_timescale(const char*ts_string);

-#endif
+#endif /* IVL_globals_H */
@@ -1,14 +1,16 @@
-.TH iverilog 1 "April 2nd, 2013" "" "Version %M.%m.%n %E"
+.TH iverilog 1 "Aug 10th, 2020" "" "Version %M.%n%E"
 .SH NAME
 iverilog - Icarus Verilog compiler

 .SH SYNOPSIS
 .B iverilog
-[\-ESVv] [\-Bpath] [\-ccmdfile|\-fcmdfile] [\-Dmacro[=defn]]
-[\-Pparameter=value] [\-pflag=value]
-[\-dname] [\-g1995|\-g2001|\-g2005|\-g2005-sv|\-g2009|\-g2012|\-g<feature>]
-[\-Iincludedir] [\-mmodule] [\-M[mode=]file] [\-Nfile] [\-ooutputfilename]
-[\-stopmodule] [\-ttype] [\-Tmin/typ/max] [\-Wclass] [\-ypath] sourcefile
+[\-EiSuVv] [\-Bpath] [\-ccmdfile|\-fcmdfile] [\-Dmacro[=defn]]
+[\-Pparameter=value] [\-pflag=value] [\-dname]
+[\-g1995\:|\-g2001\:|\-g2005\:|\-g2005-sv\:|\-g2009\:|\-g2012\:|\-g<feature>]
+[\-Iincludedir] [\-Lmoduledir] [\-mmodule] [\-M[mode=]file] [\-Nfile]
+[\-ooutputfilename] [\-stopmodule] [\-ttype] [\-Tmin/typ/max] [\-Wclass]
+[\-ypath] [\-lfile]
+sourcefile

 .SH DESCRIPTION
 .PP
@@ -30,7 +32,7 @@ different set of programs. The path given is used to locate
 \fIivlpp\fP, \fIivl\fP, code generators and the VPI modules.
 .TP 8
 .B -c\fIfile\fP -f\fIfile\fP
-These flags specifies an input file that contains a list of Verilog
+These flags specify an input file that contains a list of Verilog
 source files. This is similar to the \fIcommand file\fP of other
 Verilog simulators, in that it is a file that contains the file names
 instead of taking them on the command line. See \fBCommand Files\fP below.
@@ -79,6 +81,12 @@ use any of the new \fIIEEE1800\fP keywords.
 Enable or disable (default) support for Verilog\-AMS.
 Very little Verilog\-AMS specific functionality is currently supported.
 .TP 8
+.B -gassertions\fI|\fP-gsupported-assertions\fI|\fP-gno-assertions
+Enable (default) or disable SystemVerilog assertions. When enabled,
+assertion statements are elaborated. When disabled, assertion statements
+are parsed but ignored. The \fB\-gsupported-assertions\fP option only
+enables assertions that are currently supported by the compiler.
+.TP 8
 .B -gspecify\fI|\fP-gno-specify
 Enable or disable (default) specify block support. When enabled,
 specify block code is elaborated. When disabled, specify blocks are
@@ -123,13 +131,26 @@ default, parts of the expression that do not depend on the changed
 input value(s) are not re-evaluated. If an expression contains a call
 to a function that doesn't depend solely on its input values or that
 has side effects, the resulting behavior will differ from that
-required by the standard. Using \fI\-gstrict\-ca\-eval\fP will force
+required by the standard. Using \fB\-gstrict\-ca\-eval\fP will force
 standard compliant behavior (with some loss in performance).
 .TP 8
 .B -gstrict-expr-width\fI|\fP-gno-strict-expr-width
 Enable or disable (default) strict compliance with the standard rules
 for determining expression bit lengths. When disabled, the RHS of a
-parameter assignment is evaluated as a lossless expression.
+parameter assignment is evaluated as a lossless expression, as is any
+expression containing an unsized constant number, and unsized constant
+numbers are not truncated to integer width.
+.TP 8
+.B -gshared-loop-index\fI|\fP-gno-shared-loop-index
+Enable (default) or disable the exclusion of for-loop control variables
+from implicit event_expression lists. When enabled, if a for-loop control
+variable (loop index) is only used inside the for-loop statement, the
+compiler will not include it in an implicit event_expression list it
+calculates for that statement or any enclosing statement. This allows
+the same control variable to be used in multiple processes without risk
+of entering an infinite loop caused by each process triggering all other
+processes that use the same varaible. For strict compliance with the
+standards, this behaviour should be disabled.
 .TP 8
 .B -I\fIincludedir\fP
 Append directory \fIincludedir\fP to list of directories searched
@@ -137,6 +158,25 @@ for Verilog include files. The \fB\-I\fP switch may be used many times
 to specify several directories to search, the directories are searched
 in the order they appear on the command line.
 .TP 8
+.B -i
+Ignore missing modules. Normally it is an error if a module instantiation
+refers to an undefined module. This option causes the compiler to skip
+over that instantiation. It will also stop the compiler returning an
+error if there are no top level modules. This allows the compiler to be
+used to check incomplete designs for errors.
+.TP 8
+.B -L\fIpath\fP
+This flag adds a directory to the path list used to locate VPI
+modules. The default path includes only the install directory for the
+system.vpi module, but this flag can add other directories. Multiple
+paths are allowed, and the paths will be searched in order.
+.TP 8
+.B -l\fIfile\fP
+Add the specified file to the list of source files to be compiled,
+but mark it as a library file. All modules contained within that
+file will be treated as library modules, and only elaborated if
+they are instantiated by other modules in the design.
+.TP 8
 .B -M\fIpath\fP
 This is equivalent to \fB\-Mall=path\fP. Preserved for backwards
 compatibility.
@@ -157,9 +197,13 @@ prefixed by "I " and other files are prefixed by "M ".
 .B -m\fImodule\fP
 Add this module to the list of VPI modules to be loaded by the
 simulation. Many modules can be specified, and all will be loaded, in
-the order specified. The system module is implicit and always included.
-If a System Function Table file (<module>.sft) exists for the module it
-will be loaded automatically.
+the order specified. The system module is implicit and always included
+(and loaded last).
+
+If the specified name includes at least one directory character, it is
+assumed to be prefixed by the path to the module, otherwise the module
+is searched for in the paths specified by preceding \fB-L\fP options,
+and if not found there, in the \fIiverilog\fP base directory.
 .TP 8
 .B -N\fIpath\fP
 This is used for debugging the compiler proper. Dump the final netlist
@@ -202,6 +246,12 @@ will suppress the warning that the compiler is making a choice.
 Use this switch to specify the target output format. See the
 \fBTARGETS\fP section below for a list of valid output formats.
 .TP 8
+.B -u
+Treat each source file as a separate compilation unit (as defined in
+SystemVerilog). If compiling for an \fIIEEE1364\fP generation, this
+will just reset all compiler directives (including macro definitions)
+before each new file is processed.
+.TP 8
 .B -v
 Turn on verbose messages. This will print the command lines that are
 executed to perform the actual compilation, along with version
@@ -211,6 +261,12 @@ a reference to a key temporary file that passes information to the
 compiler proper.  To keep that file from being deleted at the end
 of the process, provide a file name of your own in the environment
 variable \fBIVERILOG_ICONFIG\fP.
+
+If the selected target is \fIvvp\fP, the \fB\-v\fP switch is appended
+to the shebang line in the compiler output file, so directly executing
+the compiler output file will turn on verbose messages in \fIvvp\fP.
+This extra verbosity can be avoided by using the \fIvvp\fP command to
+indirectly execute the compiler output file.
 .TP 8
 .B -V
 Print the version of the compiler, and exit.
@@ -238,7 +294,7 @@ that contain Verilog source files.  During elaboration, the compiler
 notices the instantiation of undefined module types. If the user
 specifies library search directories, the compiler will search the
 directory for files with the name of the missing module type. If it
-finds such a file, it loads it as a Verilog source file, they tries
+finds such a file, it loads it as a Verilog source file, then tries
 again to elaborate the module.

 Library module files should contain only a single module, but this is
@@ -261,7 +317,10 @@ This is the default. The vvp target generates code for the vvp
 runtime. The output is a complete program that simulates the design
 but must be run by the \fBvvp\fP command. The -pfileline=1 option
 can be used to add procedural statement debugging opcodes to the
-generated code.
+generated code. These opcodes are also used to generate file and
+line information for procedural warning/error messages. To enable
+the debug command tracing us the trace command (trace on) from
+the vvp interactive prompt.
 .TP 8
 .B fpga
 This is a synthesis target that supports a variety of fpga devices,
@@ -284,8 +343,14 @@ after a \fB\-Wall\fP argument to suppress isolated warning types.

 .TP 8
 .B all
-This enables the implicit, portbind, select\-range, timescale, and
-sensitivity\-entire\-array warning categories.
+This enables the anachronisms, implicit, macro-replacement, portbind,
+select\-range, timescale, and sensitivity\-entire\-array warning
+categories.
+
+.TP 8
+.B anachronisms
+This enables warnings for use of features that have been deprecated
+or removed in the selected generation of the Verilog language.

 .TP 8
 .B implicit
@@ -293,6 +358,13 @@ This enables warnings for creation of implicit declarations. For
 example, if a scalar wire X is used but not declared in the Verilog
 source, this will print a warning at its first use.

+.TP 8
+.B macro-redefinition\fI | \fPmacro-replacement
+This enables preprocessor warnings when a macro is being redefined.
+The first variant prints a warning any time a macro is redefined.
+The second variant only prints a warning if the macro text changes.
+Use \fBno-macro-redefinition\fP to turn off all warnings of this type.
+
 .TP 8
 .B portbind
 This enables warnings for ports of module instantiations that are not
@@ -344,13 +416,23 @@ sensitivity list. Although this behaviour is prescribed by the IEEE
 standard, it is not what might be expected and can have performance
 implications if the array is large.

-.SH "SYSTEM FUNCTION TABLE FILES"
-If the source file name as a \fB.sft\fP suffix, then it is taken to be
-a system function table file. A System function table file is used to
-describe to the compiler the return types for system functions. This
+.SH "VPI MODULES"
+If the source file name has a \fB.vpi\fP or \fB.vpl\fP suffix, then it
+is taken to be a VPI module. VPI modules supplied by the user are scanned
+to determine the return types of any system functions they provide. This
 is necessary because the compiler needs this information to elaborate
-expressions that contain these system functions, but cannot run the
-sizetf functions since it has no run-time.
+expressions that contain these system functions. The module path/name is
+passed on to the target to allow the VPI module to be automatically loaded
+at the start of simulation.
+
+VPI modules may also be supplied using the \fB-L\fP and \fB-m\fP options.
+
+.SH "SYSTEM FUNCTION TABLE FILES [deprecated]"
+If the source file name has a \fB.sft\fP suffix, then it is taken to be a
+system function table file. A system function table file is the old method
+used to describe to the compiler the return types for system functions.
+Users are encouraged to switch to the new method of simply supplying the
+VPI module.

 The format of the table is ASCII, one function per line. Empty lines
 are ignored, and lines that start with the '\fI#\fP' character are
@@ -371,6 +453,11 @@ The function returns an integer.
 The function returns a vector with the given width, and is signed or
 unsigned according to the flag.

+.TP 8
+.B vpiSysFuncString
+The function returns a string. This is an Icarus-specific extension, not
+available in the VPI standard.
+
 .SH "COMMAND FILES"
 The command file allows the user to place source file names and
 certain command line switches into a text file instead of on a long
@@ -389,6 +476,15 @@ A \fB\-c\fP or \fB\-f\fP token prefixes a command file, exactly like it
 does on the command line. The cmdfile may be on the same line or the
 next non-comment line.

+.TP 8
+.B -l\ \fIfile\fP -v\ \fIfile\fP
+A \fB\-l\fP token prefixes a library file in the command file,
+exactly like it does on the command line. The parameter to the \fB\-l\fP
+flag may be on the same line or the next non-comment line. \fB\-v\fP is
+an alias for \fB\-l\fP, provided for compatibility with other simulators.
+
+Variables in the \fIfile\fP are substituted.
+
 .TP 8
 .B -y\ \fIlibdir\fP
 A \fB\-y\fP token prefixes a library directory in the command file,
@@ -409,7 +505,7 @@ Variables in the \fIincludedir\fP are substituted.

 .TP 8
 .B +libext+\fIext\fP
-The \fB+libext\fP token in command files fives file extensions to try
+The \fB+libext\fP token in command files lists file extensions to try
 when looking for a library file. This is useful in conjunction with
 \fB\-y\fP flags to list suffixes to try in each directory before moving
 on to the next library directory.
@@ -460,6 +556,12 @@ This allows the programmer to select the width for integer variables
 in the Verilog source. The default is 32, the value can be any desired
 integer value.

+.TP 8
+.B +width-cap+\fIvalue\fP
+This allows the programmer to select the width cap for unsized expressions.
+If the calculated width for an unsized expression exceeds this value, the
+compiler will issue a warning and limit the expression width to this value.
+
 .SH "VARIABLES IN COMMAND FILES"

 In certain cases, iverilog supports variables in command files. These
@@ -484,6 +586,24 @@ This is always defined when compiling with Icarus Verilog.
 .B __VAMS_ENABLE__ = 1
 This is defined if Verilog\-AMS is enabled.

+.SH ENVIRONMENT
+.PP
+\fIiverilog\fP also accepts some environment variables that control
+its behavior. These can be used to make semi-permanent changes.
+
+.TP 8
+.B IVERILOG_ICONFIG=\fIfile-name\fP
+This sets the name used for the temporary file that passes parameters
+to the compiler proper, and prevents that file being deleted after the
+compiler has exited.
+
+.TP 8
+.B IVERILOG_VPI_MODULE_PATH=\fI/some/path:/some/other/path\fP
+This adds additional components to the VPI module search path. Paths
+specified in this way are searched after paths specified with \fB-L\fP,
+but before the default search path. Multiple paths can be separated with
+colons (semicolons if using Windows).
+
 .SH EXAMPLES
 These examples assume that you have a Verilog source file called hello.v in
 the current directory
@@ -506,14 +626,14 @@ Steve Williams ([email protected])

 .SH SEE ALSO
 vvp(1),
-.BR "<http://www.icarus.com/eda/verilog/>"
+.BR "<http://iverilog.icarus.com/>"

 Tips on using, debugging, and developing the compiler can be found at
 .BR "<http://iverilog.wikia.com/>"

 .SH COPYRIGHT
 .nf
-Copyright \(co  2002\-2011 Stephen Williams
+Copyright \(co  2002\-2020 Stephen Williams

 This document can be freely redistributed according to the terms of the
 GNU General Public License version 2.0
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000-2013 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2020 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -38,13 +38,13 @@ const char NOTICE[] =
 ;

 const char HELP[] =
-"Usage: iverilog [-ESvV] [-B base] [-c cmdfile|-f cmdfile]\n"
+"Usage: iverilog [-EiSuvV] [-B base] [-c cmdfile|-f cmdfile]\n"
 "                [-g1995|-g2001|-g2005|-g2005-sv|-g2009|-g2012] [-g<feature>]\n"
-"                [-D macro[=defn]] [-I includedir]\n"
+"                [-D macro[=defn]] [-I includedir] [-L moduledir]\n"
 "                [-M [mode=]depfile] [-m module]\n"
 "                [-N file] [-o filename] [-p flag=value]\n"
 "                [-s topmodule] [-t target] [-T min|typ|max]\n"
-"                [-W class] [-y dir] [-Y suf] source_file(s)\n"
+"                [-W class] [-y dir] [-Y suf] [-l file] source_file(s)\n"
 "\n"
 "See the man page for details.";

@@ -71,7 +71,7 @@ const char HELP[] =
 #endif
 #include  <fcntl.h>

-#if HAVE_GETOPT_H
+#ifdef HAVE_GETOPT_H
 #include <getopt.h>
 #endif

@@ -99,13 +99,16 @@ extern const char*optarg;

 #ifdef __MINGW32__
 const char sep = '\\';
+const char path_sep = ';';
 #else
 const char sep = '/';
+const char path_sep = ':';
 #endif

 extern void cfreset(FILE*fd, const char*path);

 const char*base = 0;
+const char*vpi_dir = 0;
 const char*ivlpp_dir = 0;
 const char*vhdlpp_dir= 0;
 const char*vhdlpp_work = 0;
@@ -122,11 +125,13 @@ char depmode = 'a';

 const char*generation = "2005";
 const char*gen_specify = "no-specify";
+const char*gen_assertions = "assertions";
 const char*gen_xtypes = "xtypes";
 const char*gen_icarus = "icarus-misc";
 const char*gen_io_range_error = "io-range-error";
 const char*gen_strict_ca_eval = "no-strict-ca-eval";
 const char*gen_strict_expr_width = "no-strict-expr-width";
+const char*gen_shared_loop_index = "shared-loop-index";
 const char*gen_verilog_ams = "no-verilog-ams";

 /* Boolean: true means use a default include dir, false means don't */
@@ -136,10 +141,17 @@ int gen_std_include = 1;
   of the include list. */
 int gen_relative_include = 0;

-char warning_flags[16] = "n";
+char warning_flags[17] = "n";
+
+int separate_compilation_flag = 0;
+
+/* Boolean: true means ignore errors about missing modules */
+int ignore_missing_modules = 0;

 unsigned integer_width = 32;

+unsigned width_cap = 65536;
+
 char*mod_list = 0;
 char*command_filename = 0;

@@ -160,6 +172,12 @@ char*compiled_defines_path = 0;

 static char iconfig_common_path[4096] = "";

+static const char**vpi_path_list = 0;
+static unsigned vpi_path_list_size = 0;
+
+static const char**env_vpi_path_list = 0;
+static unsigned env_vpi_path_list_size = 0;
+
 int synth_flag = 0;
 int verbose_flag = 0;

@@ -185,7 +203,7 @@ static const char** defparm_base = 0;
 static int defparm_size = 0;

 /* Function to add a command file name to the FIFO. */
-void add_cmd_file(const char* filename)
+static void add_cmd_file(const char* filename)
 {
      p_command_file new;

@@ -202,7 +220,7 @@ void add_cmd_file(const char* filename)
 }

 /* Function to return the top command file name from the FIFO. */
-char *get_cmd_file()
+static char *get_cmd_file(void)
 {
      char *filename;

@@ -337,10 +355,15 @@ static int t_version_only(void)

 static void build_preprocess_command(int e_flag)
 {
-      snprintf(tmp, sizeof tmp, "%s%civlpp %s%s -F\"%s\" -f\"%s\" -p\"%s\" ",
-	       ivlpp_dir, sep, verbose_flag?" -v":"",
-	       e_flag?"":" -L", defines_path, source_path,
-	       compiled_defines_path);
+      snprintf(tmp, sizeof tmp, "%s%civlpp %s%s%s -F\"%s\" -f\"%s\" -p\"%s\"%s",
+	       ivlpp_dir, sep,
+               verbose_flag ? " -v" : "",
+	       e_flag ? "" : " -L",
+               strchr(warning_flags, 'r') ? " -Wredef-all " :
+               strchr(warning_flags, 'R') ? " -Wredef-chg " : "",
+               defines_path, source_path,
+	       compiled_defines_path,
+	       e_flag ? "" : " | ");
 }

 static int t_preprocess_only(void)
@@ -399,12 +422,16 @@ static int t_preprocess_only(void)
 * needed to run the command from the configuration file (which is
 * already parsed for us) so we can handle must of the generic cases.
 */
-static int t_compile()
+static int t_compile(void)
 {
      unsigned rc;

-	/* Start by building the preprocess command line. */
-      build_preprocess_command(0);
+	/* Start by building the preprocess command line, if required.
+	   This pipes into the main ivl command. */
+      if (!separate_compilation_flag)
+	    build_preprocess_command(0);
+      else
+	    strcpy(tmp, "");

      size_t ncmd = strlen(tmp);
      char*cmd = malloc(ncmd + 1);
@@ -414,8 +441,8 @@ static int t_compile()
      int rtn;
 #endif

-	/* Build the ivl command and pipe it to the preprocessor. */
-      snprintf(tmp, sizeof tmp, " | %s%civl", base, sep);
+	/* Build the ivl command. */
+      snprintf(tmp, sizeof tmp, "%s%civl", base, sep);
      rc = strlen(tmp);
      cmd = realloc(cmd, ncmd+rc+1);
      strcpy(cmd+ncmd, tmp);
@@ -443,7 +470,16 @@ static int t_compile()
      strcpy(cmd+ncmd, tmp);
      ncmd += rc;

-      snprintf(tmp, sizeof tmp, " -C\"%s\" -- -", iconfig_common_path);
+      snprintf(tmp, sizeof tmp, " -C\"%s\"", iconfig_common_path);
+      rc = strlen(tmp);
+      cmd = realloc(cmd, ncmd+rc+1);
+      strcpy(cmd+ncmd, tmp);
+      ncmd += rc;
+
+      if (separate_compilation_flag)
+	    snprintf(tmp, sizeof tmp, " -F\"%s\"", source_path);
+      else
+	    snprintf(tmp, sizeof tmp, " -- -");
      rc = strlen(tmp);
      cmd = realloc(cmd, ncmd+rc+1);
      strcpy(cmd+ncmd, tmp);
@@ -493,6 +529,8 @@ static void process_warning_switch(const char*name)
      if (strcmp(name,"all") == 0) {
 	    process_warning_switch("anachronisms");
 	    process_warning_switch("implicit");
+	    process_warning_switch("implicit-dimensions");
+	    process_warning_switch("macro-replacement");
 	    process_warning_switch("portbind");
 	    process_warning_switch("select-range");
 	    process_warning_switch("timescale");
@@ -500,9 +538,21 @@ static void process_warning_switch(const char*name)
      } else if (strcmp(name,"anachronisms") == 0) {
 	    if (! strchr(warning_flags, 'n'))
 		  strcat(warning_flags, "n");
+      } else if (strcmp(name,"floating-nets") == 0) {
+	    if (! strchr(warning_flags, 'f'))
+		  strcat(warning_flags, "f");
      } else if (strcmp(name,"implicit") == 0) {
 	    if (! strchr(warning_flags, 'i'))
 		  strcat(warning_flags, "i");
+      } else if (strcmp(name,"implicit-dimensions") == 0) {
+	    if (! strchr(warning_flags, 'd'))
+		  strcat(warning_flags, "d");
+      } else if (strcmp(name,"macro-redefinition") == 0) {
+	  if (! strchr(warning_flags, 'r'))
+		  strcat(warning_flags, "r");
+      } else if (strcmp(name,"macro-replacement") == 0) {
+	  if (! strchr(warning_flags, 'R'))
+		  strcat(warning_flags, "R");
      } else if (strcmp(name,"portbind") == 0) {
 	    if (! strchr(warning_flags, 'p'))
 		  strcat(warning_flags, "p");
@@ -529,12 +579,35 @@ static void process_warning_switch(const char*name)
 		  cp[0] = cp[1];
 		  cp += 1;
 	    }
+      } else if (strcmp(name,"no-floating-nets") == 0) {
+	    char*cp = strchr(warning_flags, 'f');
+	    if (cp) while (*cp) {
+		  cp[0] = cp[1];
+		  cp += 1;
+	    }
      } else if (strcmp(name,"no-implicit") == 0) {
 	    char*cp = strchr(warning_flags, 'i');
 	    if (cp) while (*cp) {
 		  cp[0] = cp[1];
 		  cp += 1;
 	    }
+      } else if (strcmp(name,"no-implicit-dimensions") == 0) {
+	    char*cp = strchr(warning_flags, 'd');
+	    if (cp) while (*cp) {
+		  cp[0] = cp[1];
+		  cp += 1;
+	    }
+      } else if (strcmp(name,"no-macro-redefinition") == 0) {
+	    char*cp = strchr(warning_flags, 'r');
+	    if (cp) while (*cp) {
+		  cp[0] = cp[1];
+		  cp += 1;
+	    }
+	    cp = strchr(warning_flags, 'R');
+	    if (cp) while (*cp) {
+		  cp[0] = cp[1];
+		  cp += 1;
+	    }
      } else if (strcmp(name,"no-portbind") == 0) {
 	    char*cp = strchr(warning_flags, 'p');
 	    if (cp) while (*cp) {
@@ -565,6 +638,9 @@ static void process_warning_switch(const char*name)
 		  cp[0] = cp[1];
 		  cp += 1;
 	    }
+      } else {
+	    fprintf(stderr, "Ignoring unknown warning class "
+		    "%s\n", name);
      }
 }

@@ -606,14 +682,19 @@ void process_timescale(const char*ts_string)
 /*
 * This function is called while processing a file name in a command
 * file, or a file name on the command line. Look to see if there is a
- * .sft suffix, and if so pass that as a sys_func file. Otherwise, it
- * is a Verilog source file to be written into the file list.
+ * .sft or .vpi suffix, and if so pass that as a sys_func or module
+ * file. Otherwise, it is a Verilog source file to be written into the
+ * file list.
 */
 void process_file_name(const char*name, int lib_flag)
 {
      if (strlen(name) > 4 && strcasecmp(".sft", name+strlen(name)-4) == 0) {
+	    fprintf(stderr, "SFT files are deprecated. Please pass the VPI module instead.\n");
 	    fprintf(iconfig_file,"sys_func:%s\n", name);

+      } else if (strlen(name) > 4 && strcasecmp(".vpi", name+strlen(name)-4) == 0) {
+	    fprintf(iconfig_file,"module:%s\n", name);
+
      } else {
 	    fprintf(source_file, "%s\n", name);
 	    source_count += 1;
@@ -622,7 +703,7 @@ void process_file_name(const char*name, int lib_flag)
      }
 }

-int process_generation(const char*name)
+static int process_generation(const char*name)
 {
      if (strcmp(name,"1995") == 0)
 	    generation = "1995";
@@ -678,6 +759,15 @@ int process_generation(const char*name)
      else if (strcmp(name,"no-specify") == 0)
 	    gen_specify = "no-specify";

+      else if (strcmp(name,"assertions") == 0)
+	    gen_assertions = "assertions";
+
+      else if (strcmp(name,"supported-assertions") == 0)
+	    gen_assertions = "supported-assertions";
+
+      else if (strcmp(name,"no-assertions") == 0)
+	    gen_assertions = "no-assertions";
+
      else if (strcmp(name,"std-include") == 0)
 	     gen_std_include = 1;

@@ -708,6 +798,12 @@ int process_generation(const char*name)
      else if (strcmp(name,"no-strict-expr-width") == 0)
 	    gen_strict_expr_width = "no-strict-expr-width";

+      else if (strcmp(name,"shared-loop-index") == 0)
+	    gen_shared_loop_index = "shared-loop-index";
+
+      else if (strcmp(name,"no-shared-loop-index") == 0)
+	    gen_shared_loop_index = "no-shared-loop-index";
+
      else if (strcmp(name,"verilog-ams") == 0)
 	    gen_verilog_ams = "verilog-ams";

@@ -725,6 +821,7 @@ int process_generation(const char*name)
 		            "    2009    -- IEEE1800-2009\n"
 		            "    2012    -- IEEE1800-2012\n"
 		            "Other generation flags:\n"
+		            "    assertions | supported-assertions | no-assertions\n"
 		            "    specify | no-specify\n"
 		            "    verilog-ams | no-verilog-ams\n"
 		            "    std-include | no-std-include\n"
@@ -733,7 +830,8 @@ int process_generation(const char*name)
 		            "    icarus-misc | no-icarus-misc\n"
 		            "    io-range-error | no-io-range-error\n"
 		            "    strict-ca-eval | no-strict-ca-eval\n"
-		            "    strict-expr-width | no-strict-expr-width\n");
+		            "    strict-expr-width | no-strict-expr-width\n"
+		            "    shared-loop-index | no-shared-loop-index\n");

 	    return 1;
      }
@@ -741,7 +839,7 @@ int process_generation(const char*name)
      return 0;
 }

-int process_depfile(const char*name)
+static int process_depfile(const char*name)
 {
      const char*cp = strchr(name, '=');
      if (cp) {
@@ -772,71 +870,229 @@ int process_depfile(const char*name)
      return 0;
 }

-/*
- * If it exists add the SFT file for the given module.
- */
-void add_sft_file(const char *module)
+static void add_env_vpi_module_path(const char*path)
 {
-      char *file;
+      env_vpi_path_list_size += 1;
+      env_vpi_path_list = (const char**)realloc(env_vpi_path_list,
+					  env_vpi_path_list_size*sizeof(char*));
+      env_vpi_path_list[env_vpi_path_list_size-1] = path;
+}

-      file = (char *) malloc(strlen(base)+1+strlen(module)+4+1);
-      sprintf(file, "%s%c%s.sft", base, sep, module);
-      if (access(file, R_OK) == 0)
-            fprintf(iconfig_file, "sys_func:%s\n", file);
-      free(file);
+static void get_env_vpi_module_paths(void)
+{
+      char *var = getenv("IVERILOG_VPI_MODULE_PATH");
+      char *ptr, *end;
+
+      if (!var)
+	    return;
+
+      var = strdup(var);
+#ifdef __MINGW32__
+      convert_to_MS_path(var);
+#endif
+      ptr = var;
+      end = var+strlen(var);
+      int len = 0;
+      while (ptr <= end) {
+	    if (*ptr == 0 || *ptr == path_sep) {
+		  *ptr = 0;
+		  if (len > 0) {
+		       add_env_vpi_module_path(var);
+		  }
+		  len = 0;
+		  var = ptr+1;
+	    } else {
+		  len++;
+	    }
+	    ptr++;
+      }
+}
+
+static void add_vpi_module_path(const char*path)
+{
+#ifdef __MINGW32__
+      char*tmp_path = strdup(path);
+      convert_to_MS_path(tmp_path);
+      path = tmp_path;
+#endif
+      vpi_path_list_size += 1;
+      vpi_path_list = (const char**)realloc(vpi_path_list,
+				      vpi_path_list_size*sizeof(char*));
+      vpi_path_list[vpi_path_list_size-1] = path;
+}
+
+static int probe_for_vpi_module(const char*base_path, const char*name,
+				char*path, unsigned path_size)
+{
+      snprintf(path, path_size, "%s%c%s.vpi", base_path, sep, name);
+      if (access(path, R_OK) == 0)
+	    return 1;
+
+      snprintf(path, path_size, "%s%c%s.vpl", base_path, sep, name);
+      if (access(path, R_OK) == 0)
+	    return 1;
+
+      return 0;
+}
+
+/*
+ * If it exists add the VPI file for the given module.
+ */
+static void add_vpi_file(const char *name)
+{
+      const char*base_dir = vpi_dir ? vpi_dir : base;
+
+      char path[4096];
+
+#ifdef __MINGW32__
+      char*tmp_name = strdup(name);
+      convert_to_MS_path(tmp_name);
+      name = tmp_name;
+#endif
+
+      int found = 0;
+      if (strchr(name, sep)) {
+	      /* If the name has at least one directory character in it
+		 then assume it is a complete name, maybe including any
+		 possible .vpi or .vpl suffix. */
+	    found = access(name, R_OK) == 0;
+	    if (!found) {
+		  snprintf(path, sizeof(path), "%s.vpi", name);
+		  found = access(path, R_OK) == 0;
+		  if (!found) {
+			snprintf(path, sizeof(path), "%s.vpl", name);
+			found = access(path, R_OK) == 0;
+		  }
+	    } else {
+		  strncpy(path, name, sizeof(path) - 1);
+	    }
+      } else {
+	    for (unsigned idx = 0; !found && (idx < vpi_path_list_size); idx += 1) {
+		  found = probe_for_vpi_module(vpi_path_list[idx], name,
+					       path, sizeof(path));
+	    }
+	    for (unsigned idx = 0; !found && (idx < env_vpi_path_list_size); idx += 1) {
+		  found = probe_for_vpi_module(env_vpi_path_list[idx], name,
+					       path, sizeof(path));
+	    }
+	    if (!found) {
+		  found = probe_for_vpi_module(base_dir, name,
+					       path, sizeof(path));
+	    }
+      }
+      if (found) {
+	    fprintf(iconfig_file, "module:%s\n", path);
+      } else {
+	    fprintf(stderr, "Unable to find VPI module '%s'\n", name);
+      }
+#ifdef __MINGW32__
+      free(tmp_name);
+#endif
+}
+
+static void find_ivl_root_failed(const char *reason)
+{
+      fprintf(stderr, "Cannot locate IVL modules : %s\n", reason);
+      exit(1);
+}
+
+static void find_ivl_root(void)
+{
+#ifdef __MINGW32__
+      const char *ivl_lib_prefix = "\\lib";
+      const char *ivl_lib_suffix = "\\ivl" IVL_SUFFIX;
+#else
+      const char *ivl_lib_prefix = IVL_LIB;
+      const char *ivl_lib_suffix = "/ivl" IVL_SUFFIX;
+#endif
+      ssize_t len = 0;
+      char *s;
+
+#ifndef __MINGW32__
+	/* First try the location specified in the build process. */
+      if (access(IVL_ROOT, F_OK) != -1) {
+	    assert(strlen(IVL_ROOT) < sizeof ivl_root);
+	    strcpy(ivl_root, IVL_ROOT);
+	    return;
+      }
+#endif
+	/* If that fails, calculate the ivl_root from the path to the
+	   command. This is always necessary on Windows because of the
+	   installation process, but may also be necessary on other OSs
+	   if the package has been relocated.
+
+	   On Windows we know the command path is formed like this:
+
+		$(prefix)\bin\iverilog.exe
+
+	   The module path in a Windows installation is the path:
+
+		$(prefix)\lib\ivl$(suffix)
+
+	   so we chop the file name and the last directory by
+	   turning the last two \ characters to null. Then we append
+	   the lib\ivl$(suffix) to finish.
+
+	   On other OSs, we expect the command path to be:
+
+		$(prefix)/bin/iverilog
+
+	   and the module path to be:
+
+		$(prefix)/$(lib)/ivl$(suffix)
+
+	   so we extract the $(prefix) from the command location as for
+	   Windows and the $(lib) from IVL_LIB. This will of course fail
+	   if the user has overridden $(bindir) or $(libdir), but there's
+	   not a lot we can do in that case.
+ */
+#ifdef __MINGW32__
+      char tmppath[MAXSIZE];
+      len = GetModuleFileName(NULL, tmppath, sizeof tmppath);
+      if (len >= (ssize_t) sizeof ivl_root) {
+	    find_ivl_root_failed("command path exceeds size of string buffer.");
+      }
+	/* Convert to a short name to remove any embedded spaces. */
+      len = GetShortPathName(tmppath, ivl_root, sizeof ivl_root);
+#else
+      len = readlink("/proc/self/exe", ivl_root, sizeof ivl_root);
+#endif
+      if (len >= (ssize_t) sizeof ivl_root) {
+	    find_ivl_root_failed("command path exceeds size of string buffer.");
+      }
+      if (len <= 0) {
+	    find_ivl_root_failed("couldn't get command path from OS.");
+      }
+      s = strrchr(ivl_root, sep);
+      if (s == 0) {
+	    find_ivl_root_failed("missing first separator in command path.");
+      }
+      *s = 0;
+      s = strrchr(ivl_root, sep);
+      if (s == 0) {
+	    find_ivl_root_failed("missing second separator in command path.");
+      }
+      *s = 0;
+      len = s - ivl_root;
+      s = strrchr(ivl_lib_prefix, sep);
+      assert(s);
+      if (len + strlen(s) + strlen(ivl_lib_suffix) >= (ssize_t) sizeof ivl_root) {
+	    find_ivl_root_failed("module path exceeds size of string buffer.");
+      }
+      strcat(ivl_root, s);
+      strcat(ivl_root, ivl_lib_suffix);
 }

 int main(int argc, char **argv)
 {
      int e_flag = 0;
      int version_flag = 0;
-      int opt, idx;
-
-#ifdef __MINGW32__
-	/* Calculate the ivl_root from the path to the command. This
-	   is necessary because of the installation process on
-	   Windows. Mostly, it is those darn drive letters, but oh
-	   well. We know the command path is formed like this:
-
-		D:\iverilog\bin\iverilog.exe
-
-	   The module path in a Windows installation is the path:
-
-		D:\iverilog\lib\ivl$(suffix)
-
-	   so we chop the file name and the last directory by
-	   turning the last two \ characters to null. Then we append
-	   the lib\ivl$(suffix) to finish. */
-      char *s;
-      char tmppath[MAXSIZE];
-      GetModuleFileName(NULL, tmppath, sizeof tmppath);
-	/* Convert to a short name to remove any embedded spaces. */
-      GetShortPathName(tmppath, ivl_root, sizeof ivl_root);
-      s = strrchr(ivl_root, sep);
-      if (s) *s = 0;
-      else {
-	    fprintf(stderr, "%s: Missing first %c in exe path!\n",
-	                    argv[0], sep);
-	    exit(1);
-      }
-      s = strrchr(ivl_root, sep);
-      if (s) *s = 0;
-      else {
-	    fprintf(stderr, "%s: Missing second %c in exe path!\n",
-	                    argv[0], sep);
-	    exit(1);
-      }
-      strcat(ivl_root, "\\lib\\ivl" IVL_SUFFIX);
+      int opt;

+      find_ivl_root();
      base = ivl_root;

-#else
-        /* In a UNIX environment, the IVL_ROOT from the Makefile is
-	   dependable. It points to the $prefix/lib/ivl directory,
-	   where the sub-parts are installed. */
-      strcpy(ivl_root, IVL_ROOT);
-      base = ivl_root;
-#endif
+      get_env_vpi_module_paths();

 	/* Create a temporary file for communicating input parameters
 	   to the preprocessor. */
@@ -898,7 +1154,7 @@ int main(int argc, char **argv)
 	}
      }

-      while ((opt = getopt(argc, argv, "B:c:D:d:Ef:g:hI:M:m:N::o:P:p:Ss:T:t:vVW:y:Y:")) != EOF) {
+      while ((opt = getopt(argc, argv, "B:c:D:d:Ef:g:hl:I:iL:M:m:N:o:P:p:Ss:T:t:uvVW:y:Y:")) != EOF) {

 	    switch (opt) {
 		case 'B':
@@ -907,6 +1163,9 @@ int main(int argc, char **argv)
 		       character of the path indicates which path the
 		       user is specifying. */
 		  switch (optarg[0]) {
+		      case 'M': /* Path for the VPI modules */
+			vpi_dir = optarg+1;
+			break;
 		      case 'P': /* Path for the ivlpp preprocessor */
 			ivlpp_dir = optarg+1;
 			break;
@@ -953,14 +1212,25 @@ int main(int argc, char **argv)
 		  process_include_dir(optarg);
 		  break;

+		case 'i':
+		  ignore_missing_modules = 1;
+		  break;
+
+		case 'L':
+		  add_vpi_module_path(optarg);
+		  break;
+
+		case 'l':
+		  process_file_name(optarg, 1);
+		  break;
+
 		case 'M':
 		  if (process_depfile(optarg) != 0)
                        return -1;
 		  break;

 		case 'm':
-		  fprintf(iconfig_file, "module:%s\n", optarg);
-		  add_sft_file(optarg);
+		  add_vpi_file(optarg);
 		  break;

 		case 'N':
@@ -993,6 +1263,9 @@ int main(int argc, char **argv)
 		case 't':
 		  targ = optarg;
 		  break;
+		case 'u':
+		  separate_compilation_flag = 1;
+		  break;
 		case 'v':
 		  verbose_flag = 1;
 		  break;
@@ -1028,6 +1301,8 @@ int main(int argc, char **argv)
 	    }
      }

+      if (vpi_dir == 0)
+	    vpi_dir = base;
      if (ivlpp_dir == 0)
 	    ivlpp_dir = base;
      if (vhdlpp_dir == 0)
@@ -1035,19 +1310,10 @@ int main(int argc, char **argv)

      if (version_flag || verbose_flag) {
 	    printf("Icarus Verilog version " VERSION " (" VERSION_TAG ")\n\n");
-	    printf("Copyright 1998-2013 Stephen Williams\n\n");
+	    printf("Copyright 1998-2020 Stephen Williams\n\n");
 	    puts(NOTICE);
      }

-      if (synth_flag) {
-	    fprintf(stderr, "Warning: Synthesis is not currently being "
-	                    "maintained and may not\n");
-	    fprintf(stderr, "         function correctly. V0.8 was the "
-	                    "last release branch to\n");
-	    fprintf(stderr, "         have active synthesis development "
-	                    "and support!\n");
-      }
-
 	/* Make a common conf file path to reflect the target. */
      snprintf(iconfig_common_path, sizeof iconfig_common_path, "%s%c%s%s.conf",
 	      base, sep, targ, synth_flag? "-s" : "");
@@ -1055,11 +1321,10 @@ int main(int argc, char **argv)
 	/* Write values to the iconfig file. */
      fprintf(iconfig_file, "basedir:%s\n", base);

-	/* Tell the core where to find the system.sft. This file
-	   describes the system functions so that elaboration knows
-	   how to handle them. */
-      fprintf(iconfig_file, "sys_func:%s%csystem.sft\n", base, sep);
-      fprintf(iconfig_file, "sys_func:%s%cvhdl_sys.sft\n", base, sep);
+	/* Tell the core where to find the system VPI modules. */
+      fprintf(iconfig_file, "module:%s%csystem.vpi\n", vpi_dir, sep);
+      fprintf(iconfig_file, "module:%s%cvhdl_sys.vpi\n", vpi_dir, sep);
+      fprintf(iconfig_file, "module:%s%cvhdl_textio.vpi\n", vpi_dir, sep);

 	/* If verilog-2005/09/12 is enabled or icarus-misc or verilog-ams,
 	 * then include the v2005_math library. */
@@ -1068,35 +1333,35 @@ int main(int argc, char **argv)
          strcmp(generation, "2012") == 0 ||
          strcmp(gen_icarus, "icarus-misc") == 0 ||
          strcmp(gen_verilog_ams, "verilog-ams") == 0) {
-	    fprintf(iconfig_file, "sys_func:%s%cv2005_math.sft\n", base, sep);
-	    fprintf(iconfig_file, "module:v2005_math\n");
+	    fprintf(iconfig_file, "module:%s%cv2005_math.vpi\n", vpi_dir, sep);
      }
 	/* If verilog-ams or icarus_misc is enabled, then include the
 	 * va_math module as well. */
      if (strcmp(gen_verilog_ams,"verilog-ams") == 0 ||
          strcmp(gen_icarus, "icarus-misc") == 0) {
-	    fprintf(iconfig_file, "sys_func:%s%cva_math.sft\n", base, sep);
-	    fprintf(iconfig_file, "module:va_math\n");
+	    fprintf(iconfig_file, "module:%s%cva_math.vpi\n", vpi_dir, sep);
      }
      /* If verilog-2009 (SystemVerilog) is enabled, then include the
         v2009 module. */
      if (strcmp(generation, "2005-sv") == 0 ||
          strcmp(generation, "2009") == 0 ||
          strcmp(generation, "2012") == 0) {
-	    fprintf(iconfig_file, "sys_func:%s%cv2009.sft\n", base, sep);
-	    fprintf(iconfig_file, "module:v2009\n");
+	    fprintf(iconfig_file, "module:%s%cv2009.vpi\n", vpi_dir, sep);
      }

      if (mtm != 0) fprintf(iconfig_file, "-T:%s\n", mtm);
      fprintf(iconfig_file, "generation:%s\n", generation);
      fprintf(iconfig_file, "generation:%s\n", gen_specify);
+      fprintf(iconfig_file, "generation:%s\n", gen_assertions);
      fprintf(iconfig_file, "generation:%s\n", gen_xtypes);
      fprintf(iconfig_file, "generation:%s\n", gen_io_range_error);
      fprintf(iconfig_file, "generation:%s\n", gen_strict_ca_eval);
      fprintf(iconfig_file, "generation:%s\n", gen_strict_expr_width);
+      fprintf(iconfig_file, "generation:%s\n", gen_shared_loop_index);
      fprintf(iconfig_file, "generation:%s\n", gen_verilog_ams);
      fprintf(iconfig_file, "generation:%s\n", gen_icarus);
      fprintf(iconfig_file, "warnings:%s\n", warning_flags);
+      fprintf(iconfig_file, "ignore_missing_modules:%s\n", ignore_missing_modules ? "true" : "false");
      fprintf(iconfig_file, "out:%s\n", opath);
      if (depfile) {
            fprintf(iconfig_file, "depfile:%s\n", depfile);
@@ -1132,7 +1397,7 @@ int main(int argc, char **argv)
 	    vhdlpp_work = "ivl_vhdl_work";
      fprintf(defines_file, "vhdlpp:%s%cvhdlpp\n", vhdlpp_dir, sep);
      fprintf(defines_file, "vhdlpp-work:%s\n", vhdlpp_work);
-      for (idx = 0 ; idx < vhdlpp_libdir_cnt ; idx += 1)
+      for (unsigned idx = 0 ; idx < vhdlpp_libdir_cnt ; idx += 1)
 	    fprintf(defines_file, "vhdlpp-libdir:%s\n", vhdlpp_libdir[idx]);

    /* Process parameter definition from command line. The last
@@ -1146,7 +1411,7 @@ int main(int argc, char **argv)

 	/* Finally, process all the remaining words on the command
 	   line as file names. */
-      for (idx = optind ;  idx < argc ;  idx += 1)
+      for (int idx = optind ;  idx < argc ;  idx += 1)
 	    process_file_name(argv[idx], 0);

 	/* If the use of a default include directory is not
@@ -1173,8 +1438,12 @@ int main(int argc, char **argv)
 	   will append to the file, so this is necessary to make sure
 	   it starts out empty. */
      if (depfile) {
-	    FILE*fd = fopen(depfile, "w");
-	    fclose(fd);
+            FILE *fd = fopen(depfile, "w");
+            if (!fd) {
+                  fprintf(stderr, "%s: can't open %s file.\n\n%s\n", argv[0], depfile, HELP);
+                  return 1;
+            }
+            fclose(fd);
      }

      if (source_count == 0 && !version_flag) {
@@ -1184,11 +1453,17 @@ int main(int argc, char **argv)

      fprintf(iconfig_file, "iwidth:%u\n", integer_width);

+      fprintf(iconfig_file, "widthcap:%u\n", width_cap);
+
 	/* Write the preprocessor command needed to preprocess a
 	   single file. This may be used to preprocess library
 	   files. */
-      fprintf(iconfig_file, "ivlpp:%s%civlpp -L -F\"%s\" -P\"%s\"\n",
-	      ivlpp_dir, sep, defines_path, compiled_defines_path);
+      fprintf(iconfig_file, "ivlpp:%s%civlpp %s -L -F\"%s\" -P\"%s\"\n",
+	      ivlpp_dir, sep,
+              strchr(warning_flags, 'r') ? "-Wredef-all" :
+              strchr(warning_flags, 'R') ? "-Wredef-chg" : "",
+              defines_path, compiled_defines_path
+      );

 	/* Done writing to the iconfig file. Close it now. */
      fclose(iconfig_file);
@@ -21,6 +21,7 @@
 # include  <stdlib.h>
 # include  <stdio.h>
 # include  "ivl_alloc.h"
+# include  "globals.h"


 char* substitutions(const char*str)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2013 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2019 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -32,6 +32,17 @@ NetEAccess* NetEAccess::dup_expr() const
      return tmp;
 }

+NetEArrayPattern*NetEArrayPattern::dup_expr() const
+{
+      vector<NetExpr*>tmp (items_.size());
+      for (size_t idx = 0 ; idx < tmp.size() ; idx += 1)
+	    tmp[idx] = items_[idx]->dup_expr();
+
+      NetEArrayPattern*res = new NetEArrayPattern(net_type(), tmp);
+      res->set_line(*this);
+      return res;
+}
+
 NetEBinary* NetEBinary::dup_expr() const
 {
      ivl_assert(*this, 0);
@@ -171,6 +182,14 @@ NetEEvent* NetEEvent::dup_expr() const
      return 0;
 }

+NetELast* NetELast::dup_expr() const
+{
+      NetELast*tmp = new NetELast(sig_);
+      ivl_assert(*this, tmp);
+      tmp->set_line(*this);
+      return tmp;
+}
+
 NetENetenum* NetENetenum::dup_expr() const
 {
      ivl_assert(*this, 0);
@@ -214,7 +233,7 @@ NetESelect* NetESelect::dup_expr() const

 NetESFunc* NetESFunc::dup_expr() const
 {
-      NetESFunc*tmp = new NetESFunc(name_, type_, expr_width(), nparms());
+      NetESFunc*tmp = new NetESFunc(name_, type_, expr_width(), nparms(), is_overridden_);
      ivl_assert(*this, tmp);

      tmp->cast_signed(has_sign());
@@ -238,6 +257,7 @@ NetESignal* NetESignal::dup_expr() const
      NetESignal*tmp = new NetESignal(net_, word_);
      ivl_assert(*this, tmp);
      tmp->expr_width(expr_width());
+      tmp->cast_signed(has_sign());
      tmp->set_line(*this);
      return tmp;
 }
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2012 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2014 Stephen Williams (steve@icarus.com)
 * Copyright CERN 2012 / Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
@@ -328,39 +328,66 @@ bool PEIdent::eval_part_select_(Design*des, NetScope*scope, NetNet*sig,
 		      return false;
 		}

-		long lidx_tmp = sig->sb_to_idx(prefix_indices, lsb);
-		long midx_tmp = sig->sb_to_idx(prefix_indices, msb);
-		  /* Detect reversed indices of a part select. */
-		if (lidx_tmp > midx_tmp) {
-		      cerr << get_fileline() << ": error: Part select "
-			   << sig->name() << "[" << msb << ":"
-			   << lsb << "] indices reversed." << endl;
-		      cerr << get_fileline() << ":      : Did you mean "
-			   << sig->name() << "[" << lsb << ":"
-			   << msb << "]?" << endl;
-		      long tmp = midx_tmp;
-		      midx_tmp = lidx_tmp;
-		      lidx_tmp = tmp;
-		      des->errors += 1;
-		}
+		if (prefix_indices.size()+1 < sig->packed_dims().size()) {
+		      // Here we have a slice that doesn't have enough indices
+		      // to get to a single slice. For example:
+		      //    wire [9:0][5:1] foo
+		      //      ... foo[4:3] ...
+		      // Make this work by finding the indexed slices and
+		      // creating a generated slice that spans the whole
+		      // range.
+		      long loff, moff;
+		      unsigned long lwid, mwid;
+		      bool lrc;
+		      lrc = sig->sb_to_slice(prefix_indices, lsb, loff, lwid);
+		      ivl_assert(*this, lrc);
+		      lrc = sig->sb_to_slice(prefix_indices, msb, moff, mwid);
+		      ivl_assert(*this, lrc);
+		      ivl_assert(*this, lwid == mwid);

-		  /* Warn about a part select that is out of range. */
-		if (midx_tmp >= (long)sig->vector_width() || lidx_tmp < 0) {
-		      cerr << get_fileline() << ": warning: Part select "
-			   << sig->name();
-		      if (sig->unpacked_dimensions() > 0) {
-			    cerr << "[]";
+		      if (moff > loff) {
+			    lidx = loff;
+			    midx = moff + mwid - 1;
+		      } else {
+			    lidx = moff;
+			    midx = loff + lwid - 1;
 		      }
-		      cerr << "[" << msb << ":" << lsb
-			   << "] is out of range." << endl;
-		}
-		  /* This is completely out side the signal so just skip it. */
-		if (lidx_tmp >= (long)sig->vector_width() || midx_tmp < 0) {
-		      return false;
-		}
+		} else {
+		      long lidx_tmp = sig->sb_to_idx(prefix_indices, lsb);
+		      long midx_tmp = sig->sb_to_idx(prefix_indices, msb);

-		midx = midx_tmp;
-		lidx = lidx_tmp;
+		        /* Detect reversed indices of a part select. */
+		      if (lidx_tmp > midx_tmp) {
+			    cerr << get_fileline() << ": error: Part select "
+			        << sig->name() << "[" << msb << ":"
+			        << lsb << "] indices reversed." << endl;
+			    cerr << get_fileline() << ":      : Did you mean "
+			        << sig->name() << "[" << lsb << ":"
+			        << msb << "]?" << endl;
+			    long tmp = midx_tmp;
+			    midx_tmp = lidx_tmp;
+			    lidx_tmp = tmp;
+			    des->errors += 1;
+		      }
+
+		        /* Warn about a part select that is out of range. */
+		      if (midx_tmp >= (long)sig->vector_width() || lidx_tmp < 0) {
+			    cerr << get_fileline() << ": warning: Part select "
+			         << sig->name();
+			    if (sig->unpacked_dimensions() > 0) {
+				cerr << "[]";
+			    }
+			    cerr << "[" << msb << ":" << lsb
+			         << "] is out of range." << endl;
+		}
+		        /* This is completely out side the signal so just skip it. */
+		      if (lidx_tmp >= (long)sig->vector_width() || midx_tmp < 0) {
+			    return false;
+		      }
+
+		      midx = midx_tmp;
+		      lidx = lidx_tmp;
+		}
 		break;
 	  }

@@ -501,6 +528,10 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
      unsigned midx = sig->vector_width()-1, lidx = 0;
 	// The default word select is the first.
      long widx = 0;
+	// Set this to true if we calculate the word index. This is
+	// used to distinguish between unpacked array assignment and
+	// array word assignment.
+      bool widx_flag = false;

      list<long> unpacked_indices_const;

@@ -524,7 +555,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
 	    if (debug_elaborate) {
 		  cerr << get_fileline() << ": PEIdent::elaborate_lnet_common_: "
 		       << "Member " << method_name
-		       << " has packed dimensions " << member->packed_dims << "." << endl;
+		       << " has type " << *member->net_type << "." << endl;
 		  cerr << get_fileline() << ":                                : "
 		       << "Tail name has " << path_tail.index.size() << " indices." << endl;
 	    }
@@ -532,13 +563,13 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
 	      // Rewrite a member select of a packed structure as a
 	      // part select of the base variable.
 	    lidx = member_off;
-	    midx = lidx + member->width() - 1;
+	    midx = lidx + member->net_type->packed_width() - 1;

 	      // The dimensions of the tail of the prefix must match
 	      // the dimensions of the signal at this point. (The sig
 	      // has a packed dimension for the packed struct size.)
 	      // For example, if the path_=a[<m>][<n>].member, then
-	      // sig must have 3 packed dimenions: one for the struct
+	      // sig must have 3 packed dimensions: one for the struct
 	      // members and two actual packed dimensions.
 	    ivl_assert(*this, path_prefix.back().index.size()+1 == sig->packed_dimensions());

@@ -555,15 +586,16 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
 		  packed_base = collapse_array_indices(des, scope, sig, tmp_index);

 		  if (debug_elaborate) {
-			cerr << get_fileline() << ": debug: "
-			     << "packed_base expression = " << *packed_base << endl;
+			cerr << get_fileline() << ": PEIdent::elaborate_lnet_common_: "
+			     << "packed_base=" << *packed_base
+			     << ", member_off=" << member_off << endl;
 		  }
 	    }

 	    long tmp;
 	    if (packed_base && eval_as_long(tmp, packed_base)) {
 		  lidx = tmp;
-		  midx = lidx + member->width() - 1;
+		  midx = lidx + member->net_type->packed_width() - 1;
 		  delete packed_base;
 		  packed_base = 0;
 	    }
@@ -574,7 +606,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
 	      // Now the lidx/midx values get us to the member. Next
 	      // up, deal with bit/part selects from the member
 	      // itself.
-	    ivl_assert(*this, member->packed_dims.size() <= 1);
+	      //XXXXivl_assert(*this, member->packed_dims.size() <= 1);
 	    ivl_assert(*this, path_tail.index.size() <= 1);
 	    if (! path_tail.index.empty()) {
 		  long tmp_off;
@@ -590,13 +622,31 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
 		  midx = lidx + tmp_wid - 1;
 	    }

+      } else if (gn_system_verilog() && sig->unpacked_dimensions() > 0 && path_tail.index.empty()) {
+
+	      // In this case, we are doing a continuous assignment to
+	      // an unpacked array. The NetNet representation is a
+	      // NetNet with a pin for each array element, so there is
+	      // nothing more needed here.
+	      //
+	      // This can come up from code like this:
+	      //   logic [...] data [0:3];
+	      //   assign data = ...;
+	      // In this case, "sig" is "data", and sig->pin_count()
+	      // is 4 to account for the unpacked size.
+	    if (debug_elaborate) {
+		  cerr << get_fileline() << ": PEIdent::elaborate_lnet_common_: "
+		       << "Net assign to unpacked array \"" << sig->name()
+		       << "\" with " << sig->pin_count() << " elements." << endl;
+	    }
+
      } else if (sig->unpacked_dimensions() > 0) {

 	      // Make sure there are enough indices to address an array element.
 	    if (path_tail.index.size() < sig->unpacked_dimensions()) {
 		  cerr << get_fileline() << ": error: Array " << path()
 		       << " needs " << sig->unpacked_dimensions() << " indices,"
-		       << " but got only " << path_tail.index.size() << "." << endl;
+		       << " but got only " << path_tail.index.size() << ". (net)" << endl;
 		  des->errors += 1;
 		  return 0;
 	    }
@@ -627,6 +677,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
 		       << sig->name() << as_indices(unpacked_indices)
 		       << "." << endl;
 		  widx = -1;
+		  widx_flag = true;

 	    } else {
 		  NetExpr*canon_index = 0;
@@ -639,12 +690,14 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
 			     << sig->name() << as_indices(unpacked_indices_const)
 			     << "." << endl;
 			widx = -1;
+			widx_flag = true;

 		  } else {
 			NetEConst*canon_const = dynamic_cast<NetEConst*>(canon_index);
 			ivl_assert(*this, canon_const);

 			widx = canon_const->value().as_long();
+			widx_flag = true;
 			delete canon_index;
 		  }
 	    }
@@ -682,6 +735,16 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
 	    }

      } else if (!path_tail.index.empty()) {
+	    if (debug_elaborate) {
+		  cerr << get_fileline() << ": PEIdent::elaborate_lnet_common_: "
+		       << "path_tail.index.size()=" << path_tail.index.size()
+		       << endl;
+	    }
+
+	      // There are index expressions on the name, so this is a
+	      // bit/slice select of the name. Calculate a canonical
+	      // part select.
+
 	    if (sig->get_scalar()) {
 		  cerr << get_fileline() << ": error: "
 		       << "can not select part of ";
@@ -710,14 +773,21 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
      unsigned subnet_wid = midx-lidx+1;

 	/* Check if the l-value bits are double-driven. */
-      if (sig->type() == NetNet::UNRESOLVED_WIRE && sig->test_part_lref(midx,lidx)) {
+      if (sig->type() == NetNet::UNRESOLVED_WIRE && sig->test_and_set_part_driver(midx,lidx, widx_flag? widx : 0)) {
 	    cerr << get_fileline() << ": error: Unresolved net/uwire "
 	         << sig->name() << " cannot have multiple drivers." << endl;
+	    if (debug_elaborate) {
+		  cerr << get_fileline() << ":      : Overlap in "
+		       << "[" << midx << ":" << lidx << "] (canonical)"
+		       << ", widx=" << (widx_flag? widx : 0)
+		       << ", vector width=" << sig->vector_width()
+		       << endl;
+	    }
 	    des->errors += 1;
 	    return 0;
      }

-      if (sig->pin_count() > 1) {
+      if (sig->pin_count() > 1 && widx_flag) {
 	    if (widx < 0 || widx >= (long) sig->pin_count())
 		  return 0;

@@ -729,6 +799,13 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
 	    tmp->local_flag(true);
 	    connect(sig->pin(widx), tmp->pin(0));
 	    sig = tmp;
+
+      } else if (sig->pin_count() > 1) {
+
+	      // If this turns out to be an l-value unpacked array,
+	      // then let the caller handle it. It will probably be
+	      // converted into an array of assignments.
+	    return sig;
      }

 	/* If the desired l-value vector is narrower than the
@@ -851,6 +928,33 @@ NetNet* PEIdent::elaborate_subport(Design*des, NetScope*scope) const
      long midx;
      long lidx;

+      if (debug_elaborate) {
+	    cerr << get_fileline() << ": PEIdent::elaborate_subport: "
+		 << "path_ = \"" << path_
+		 << "\", unpacked_dimensions=" << sig->unpacked_dimensions()
+		 << ", port_type()=" << sig->port_type() << endl;
+      }
+
+      if (sig->unpacked_dimensions() && !gn_system_verilog()) {
+	    cerr << get_fileline() << ": error: "
+		 << "Ports cannot be unpacked arrays. Try enabling SystemVerilog support." << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+	// There cannot be parts to an unpacked array, so process this
+	// simply as an unpacked array.
+      if (sig->unpacked_dimensions()) {
+	    if (debug_elaborate) {
+		  cerr << get_fileline() << ": PEIdent::elaborate_subport: "
+		       << "path_=\"" << path_
+		       << "\" is an unpacked array with " << sig->pin_count()
+		       << " elements." << endl;
+	    }
+	    scope->add_module_port_net(sig);
+	    return sig;
+      }
+
 	/* Evaluate the part/bit select expressions, to get the part
 	   select of the signal that attaches to the port. Also handle
 	   range and direction checking here. */
@@ -912,6 +1016,20 @@ NetNet* PEIdent::elaborate_subport(Design*des, NetScope*scope) const
      return sig;
 }

+NetNet*PEIdent::elaborate_unpacked_net(Design*des, NetScope*scope) const
+{
+      NetNet*       sig = 0;
+      const NetExpr*par = 0;
+      NetEvent*     eve = 0;
+      perm_string method_name;
+
+      symbol_search(this, des, scope, path_, sig, par, eve);
+
+      ivl_assert(*this, sig);
+
+      return sig;
+}
+
 bool PEIdent::is_collapsible_net(Design*des, NetScope*scope) const
 {
      assert(scope);
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000-2012 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2020 Stephen Williams (steve@icarus.com)
 * Copyright CERN 2012 / Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
@@ -38,15 +38,17 @@
 # include  "netmisc.h"
 # include  "netclass.h"
 # include  "netenum.h"
-# include  "netstruct.h"
 # include  "netvector.h"
 # include  "netdarray.h"
 # include  "netparray.h"
+# include  "netqueue.h"
 # include  "util.h"
 # include  "ivl_assert.h"

 using namespace std;

+#if 0
+/* These functions are not currently used. */
 static bool get_const_argument(NetExpr*exp, verinum&res)
 {
      switch (exp->expr_type()) {
@@ -73,8 +75,6 @@ static bool get_const_argument(NetExpr*exp, verinum&res)
      return true;
 }

-#if 0
-/* This function is not currently used. */
 static bool get_const_argument(NetExpr*exp, long&res)
 {
      verinum tmp;
@@ -207,6 +207,11 @@ bool PPackage::elaborate_sig(Design*des, NetScope*scope) const
 {
      bool flag = true;

+      if (debug_elaborate) {
+	    cerr << get_fileline() << ": PPackage::elaborate_sig: "
+		 << "Start package scope=" << scope_path(scope) << endl;
+      }
+
      flag = elaborate_sig_wires_(des, scope) && flag;

 	// After all the wires are elaborated, we are free to
@@ -215,6 +220,13 @@ bool PPackage::elaborate_sig(Design*des, NetScope*scope) const

      elaborate_sig_funcs(des, scope, funcs);
      elaborate_sig_tasks(des, scope, tasks);
+      elaborate_sig_classes(des, scope, classes);
+
+      if (debug_elaborate) {
+	    cerr << get_fileline() << ": PPackage::elaborate_sig: "
+		 << "Done package scope=" << scope_path(scope)
+		 << ", flag=" << flag << endl;
+      }

      return flag;
 }
@@ -566,10 +578,10 @@ void PFunction::elaborate_sig(Design*des, NetScope*scope) const
 	      // source code for the definition may be:
 	      //   function new(...);
 	      //   endfunction
-	      // In this case, the "@" port is the synthetic "this"
-	      // argument and we also use it as a return value at the
-	      // same time.
-	    ret_sig = scope->find_signal(perm_string::literal("@"));
+	      // In this case, the "@" port (THIS_TOKEN) is the synthetic
+	      // "this" argument and we also use it as a return value at
+	      // the same time.
+	    ret_sig = scope->find_signal(perm_string::literal(THIS_TOKEN));
 	    ivl_assert(*this, ret_sig);

 	    if (debug_elaborate)
@@ -582,30 +594,50 @@ void PFunction::elaborate_sig(Design*des, NetScope*scope) const
 	    ivl_type_t ret_type;

 	    if (return_type_) {
-		  ret_type = return_type_->elaborate_type(des, scope);
+		  if (dynamic_cast<const struct void_type_t*> (return_type_)) {
+			ret_type = 0;
+		  } else {
+			ret_type = return_type_->elaborate_type(des, scope->parent());
+			ivl_assert(*this, ret_type);
+		  }
 	    } else {
 		  netvector_t*tmp = new netvector_t(IVL_VT_LOGIC);
 		  tmp->set_scalar(true);
 		  ret_type = tmp;
 	    }
-	    list<netrange_t> ret_unpacked;
-	    ret_sig = new NetNet(scope, fname, NetNet::REG, ret_unpacked, ret_type);

-	    ret_sig->set_line(*this);
-	    ret_sig->port_type(NetNet::POUTPUT);
+	    if (ret_type) {
+		  if (debug_elaborate) {
+			cerr << get_fileline() << ": PFunction::elaborate_sig: "
+			     << "return type: " << *ret_type << endl;
+			if (return_type_)
+			      return_type_->pform_dump(cerr, 8);
+		  }
+		  list<netrange_t> ret_unpacked;
+		  ret_sig = new NetNet(scope, fname, NetNet::REG, ret_unpacked, ret_type);
+
+		  ret_sig->set_line(*this);
+		  ret_sig->port_type(NetNet::POUTPUT);
+	    } else {
+		  ret_sig = 0;
+		  if (debug_elaborate) {
+			cerr << get_fileline() << ": PFunction::elaborate_sig: "
+			     << "Detected that function is void." << endl;
+		  }
+	    }
      }

      vector<NetNet*>ports;
-      elaborate_sig_ports_(des, scope, ports);
+      vector<NetExpr*>pdef;
+      elaborate_sig_ports_(des, scope, ports, pdef);

-      NetFuncDef*def = 0;
-      if (ret_sig)  def = new NetFuncDef(scope, ret_sig, ports);
+      NetFuncDef*def = new NetFuncDef(scope, ret_sig, ports, pdef);

-      assert(def);
      if (debug_elaborate)
-	    cerr << get_fileline() << ": debug: "
-		 << "Attach function definition to scope "
-		 << scope_path(scope) << "." << endl;
+	    cerr << get_fileline() << ": PFunction::elaborate_sig: "
+		 << "Attach function definition " << scope_path(scope)
+		 << " with ret_sig width=" << (ret_sig? ret_sig->vector_width() : 0)
+		 << "." << endl;

      scope->set_func_def(def);

@@ -630,8 +662,9 @@ void PTask::elaborate_sig(Design*des, NetScope*scope) const
      elaborate_sig_wires_(des, scope);

      vector<NetNet*>ports;
-      elaborate_sig_ports_(des, scope, ports);
-      NetTaskDef*def = new NetTaskDef(scope, ports);
+      vector<NetExpr*>pdefs;
+      elaborate_sig_ports_(des, scope, ports, pdefs);
+      NetTaskDef*def = new NetTaskDef(scope, ports, pdefs);
      scope->set_task_def(def);

 	// Look for further signals in the sub-statement
@@ -640,10 +673,11 @@ void PTask::elaborate_sig(Design*des, NetScope*scope) const
 }

 void PTaskFunc::elaborate_sig_ports_(Design*des, NetScope*scope,
-				     vector<NetNet*>&ports) const
+				     vector<NetNet*>&ports, vector<NetExpr*>&pdefs) const
 {
      if (ports_ == 0) {
 	    ports.clear();
+	    pdefs.clear();

 	      /* Make sure the function has at least one input
 		 port. If it fails this test, print an error
@@ -661,13 +695,16 @@ void PTaskFunc::elaborate_sig_ports_(Design*des, NetScope*scope,
      }

      ports.resize(ports_->size());
+      pdefs.resize(ports_->size());

      for (size_t idx = 0 ; idx < ports_->size() ; idx += 1) {

-	    perm_string port_name = ports_->at(idx)->basename();
+	    perm_string port_name = ports_->at(idx).port->basename();

 	    ports[idx] = 0;
+	    pdefs[idx] = 0;
 	    NetNet*tmp = scope->find_signal(port_name);
+	    NetExpr*tmp_def = 0;
 	    if (tmp == 0) {
 		  cerr << get_fileline() << ": internal error: "
 		       << "task/function " << scope_path(scope)
@@ -678,6 +715,27 @@ void PTaskFunc::elaborate_sig_ports_(Design*des, NetScope*scope,
 		  continue;
 	    }

+	      // If the port has a default expression, elaborate
+	      // that expression here.
+	    if (ports_->at(idx).defe != 0) {
+		  if (tmp->port_type() == NetNet::PINPUT) {
+			tmp_def = elab_and_eval(des, scope, ports_->at(idx).defe,
+						-1, scope->need_const_func());
+			if (tmp_def == 0) {
+			      cerr << get_fileline()
+				   << ": error: Unable to evaluate "
+				   << *ports_->at(idx).defe
+				   << " as a port default expression." << endl;
+			      des->errors += 1;
+			}
+		  } else {
+			cerr << get_fileline() << ": sorry: Default arguments "
+			        "for subroutine output or inout ports are not "
+			        "yet supported." << endl;
+			des->errors += 1;
+		  }
+	    }
+
 	    if (tmp->port_type() == NetNet::NOT_A_PORT) {
 		  cerr << get_fileline() << ": internal error: "
 		       << "task/function " << scope_path(scope)
@@ -689,15 +747,21 @@ void PTaskFunc::elaborate_sig_ports_(Design*des, NetScope*scope,
 	    }

 	    ports[idx] = tmp;
+	    pdefs[idx] = tmp_def;
 	    if (scope->type()==NetScope::FUNC && tmp->port_type()!=NetNet::PINPUT) {
 		  cerr << tmp->get_fileline() << ": error: "
 		       << "Function " << scope_path(scope)
 		       << " port " << port_name
-		       << " is not an inputport." << endl;
+		       << " is not an input port." << endl;
 		  cerr << tmp->get_fileline() << ":      : "
 		       << "Function arguments must be input ports." << endl;
 		  des->errors += 1;
 	    }
+	    if (tmp->unpacked_dimensions() != 0) {
+		  cerr << get_fileline() << ": sorry: Subroutine ports with "
+			  "unpacked dimensions are not yet supported." << endl;
+		 des->errors += 1;
+	    }
      }
 }

@@ -755,12 +819,24 @@ void PDelayStatement::elaborate_sig(Design*des, NetScope*scope) const
 	    statement_->elaborate_sig(des, scope);
 }

+void PDoWhile::elaborate_sig(Design*des, NetScope*scope) const
+{
+      if (statement_)
+	    statement_->elaborate_sig(des, scope);
+}
+
 void PEventStatement::elaborate_sig(Design*des, NetScope*scope) const
 {
      if (statement_)
 	    statement_->elaborate_sig(des, scope);
 }

+void PForeach::elaborate_sig(Design*des, NetScope*scope) const
+{
+      if (statement_)
+	    statement_->elaborate_sig(des, scope);
+}
+
 void PForever::elaborate_sig(Design*des, NetScope*scope) const
 {
      if (statement_)
@@ -785,96 +861,11 @@ void PWhile::elaborate_sig(Design*des, NetScope*scope) const
 	    statement_->elaborate_sig(des, scope);
 }

-static bool evaluate_ranges(Design*des, NetScope*scope,
-			    vector<netrange_t>&llist,
-			    const list<pform_range_t>&rlist)
-{
-      bool bad_msb = false, bad_lsb = false;
-
-      for (list<pform_range_t>::const_iterator cur = rlist.begin()
-		 ; cur != rlist.end() ; ++cur) {
-	    long use_msb, use_lsb;
-
-	    NetExpr*texpr = elab_and_eval(des, scope, cur->first, -1, true);
-	    if (! eval_as_long(use_msb, texpr)) {
-		  cerr << cur->first->get_fileline() << ": error: "
-			"Range expressions must be constant." << endl;
-		  cerr << cur->first->get_fileline() << "       : "
-			"This MSB expression violates the rule: "
-		       << *cur->first << endl;
-		  des->errors += 1;
-		  bad_msb = true;
-	    }
-
-	    delete texpr;
-
-	    texpr = elab_and_eval(des, scope, cur->second, -1, true);
-	    if (! eval_as_long(use_lsb, texpr)) {
-		  cerr << cur->second->get_fileline() << ": error: "
-			"Range expressions must be constant." << endl;
-		  cerr << cur->second->get_fileline() << "       : "
-			"This LSB expression violates the rule: "
-		       << *cur->second << endl;
-		  des->errors += 1;
-		  bad_lsb = true;
-	    }
-
-	    delete texpr;
-
-	    llist.push_back(netrange_t(use_msb, use_lsb));
-      }
-
-      return bad_msb | bad_lsb;
-}
-
-static netclass_t* locate_class_type(Design*, NetScope*scope,
-				     class_type_t*class_type)
-{
-      netclass_t*use_class = scope->find_class(class_type->name);
-      return use_class;
-}
-
-static netstruct_t* elaborate_struct_type(Design*des, NetScope*scope,
-					  struct_type_t*struct_type)
-{
-      netstruct_t*res = new netstruct_t;
-
-      res->packed(struct_type->packed_flag);
-
-      for (list<struct_member_t*>::iterator cur = struct_type->members->begin()
-		 ; cur != struct_type->members->end() ; ++ cur) {
-
-	    vector<netrange_t>packed_dimensions;
-
-	    struct_member_t*curp = *cur;
-	    if (curp->range.get() && ! curp->range->empty()) {
-		  bool bad_range;
-		  bad_range = evaluate_ranges(des, scope, packed_dimensions, *curp->range);
-		  ivl_assert(*curp, !bad_range);
-	    } else {
-		  packed_dimensions.push_back(netrange_t(0,0));
-	    }
-
-	    for (list<decl_assignment_t*>::iterator name = curp->names->begin()
-		       ; name != curp->names->end() ;  ++ name) {
-		  decl_assignment_t*namep = *name;
-
-		  netstruct_t::member_t memb;
-		  memb.name = namep->name;
-		  memb.type = curp->type;
-		  memb.packed_dims = packed_dimensions;
-		  res->append_member(memb);
-	    }
-      }
-
-      return res;
-}
-
 static ivl_type_s*elaborate_type(Design*des, NetScope*scope,
 				 data_type_t*pform_type)
 {
      if (struct_type_t*struct_type = dynamic_cast<struct_type_t*>(pform_type)) {
-	    netstruct_t*use_type = elaborate_struct_type(des, scope, struct_type);
+	    ivl_type_s*use_type = struct_type->elaborate_type(des, scope);
 	    return use_type;
      }

@@ -885,13 +876,13 @@ static ivl_type_s*elaborate_type(Design*des, NetScope*scope,
      return 0;
 }

-static netparray_t* elaborate_parray_type(Design*des, NetScope*scope,
+static netparray_t* elaborate_parray_type(Design*des, NetScope*scope, const LineInfo*li,
 					  parray_type_t*data_type)
 {

      vector<netrange_t>packed_dimensions;
-      bool bad_range = evaluate_ranges(des, scope, packed_dimensions, * data_type->dims);
-      ivl_assert(*data_type, !bad_range);
+      bool dimensions_ok = evaluate_ranges(des, scope, li, packed_dimensions, * data_type->dims);
+      ivl_assert(*data_type, dimensions_ok);

      ivl_type_s*element_type = elaborate_type(des, scope, data_type->base_type);

@@ -930,59 +921,65 @@ bool test_ranges_eeq(const vector<netrange_t>&lef, const vector<netrange_t>&rig)
 */
 NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 {
+	// This sets the vector or array dimension size that will
+	// cause a warning. For now, these warnings are permanently
+	// enabled.
+      const long warn_dimension_size = 1 << 30;
+
      NetNet::Type wtype = type_;
      bool is_implicit_scalar = false;
      if (wtype == NetNet::IMPLICIT) {
 	    wtype = NetNet::WIRE;
 	    is_implicit_scalar = true;
      }
+	// Certain contexts, such as arguments to functions, presume
+	// "reg" instead of "wire". The parser reports these as
+	// IMPLICIT_REG. Also, certain cases, such as:
+	//   fun(string arg1) ...
+	// are implicitly NOT scalar, so detect that case here.
      if (wtype == NetNet::IMPLICIT_REG) {
 	    wtype = NetNet::REG;
-	    is_implicit_scalar = true;
+	    if (data_type_!=IVL_VT_STRING)
+		  is_implicit_scalar = true;
+      }
+
+      if (debug_elaborate) {
+	    cerr << get_fileline() << ": PWire::elaborate_sig: "
+		 << "Signal " << basename()
+		 << ", wtype=" << wtype
+		 << ", data_type_=" << data_type_
+		 << ", is_implicit_scalar=" << (is_implicit_scalar?"true":"false")
+		 << endl;
      }

      unsigned wid = 1;
      vector<netrange_t>packed_dimensions;

+      NetScope*base_type_scope = scope;
+      if (set_data_type_ && !set_data_type_->name.nil())
+            base_type_scope = scope->find_typedef_scope(des, set_data_type_);
+
      des->errors += error_cnt_;

-	// A signal can not have the same name as a scope object.
-      const NetScope *child = scope->child(hname_t(name_));
-      if (child) {
-	    cerr << get_fileline() << ": error: signal and ";
-	    child->print_type(cerr);
-	    cerr << " in '" << scope->fullname()
-	         << "' have the same name '" << name_ << "'." << endl;
-	    des->errors += 1;
-      }
-	// A signal can not have the same name as a genvar.
-      const LineInfo *genvar = scope->find_genvar(name_);
-      if (genvar) {
-	    cerr << get_fileline() << ": error: signal and genvar in '"
-	         << scope->fullname() << "' have the same name '" << name_
-	         << "'." << endl;
-	    des->errors += 1;
-      }
-	// A signal can not have the same name as a parameter.
-      const NetExpr *ex_msb, *ex_lsb;
-      const NetExpr *parm = scope->get_parameter(des, name_, ex_msb, ex_lsb);
-      if (parm) {
-	    cerr << get_fileline() << ": error: signal and parameter in '"
-	         << scope->fullname() << "' have the same name '" << name_
-	         << "'." << endl;
-	    des->errors += 1;
-      }
-	// A signal can not have the same name as a named event.
-      const NetEvent *event = scope->find_event(name_);
-      if (event) {
-	    cerr << get_fileline() << ": error: signal and named event in '"
-	         << scope->fullname() << "' have the same name '" << name_
-	         << "'." << endl;
-	    des->errors += 1;
-      }
-
      if (port_set_ || net_set_) {
-	    bool bad_range = false;
+
+	    if (warn_implicit_dimensions
+		&& port_set_ && net_set_
+		&& net_.empty() && !port_.empty()) {
+		  cerr << get_fileline() << ": warning: "
+		       << "var/net declaration of " << basename()
+		       << " inherits dimensions from port declaration." << endl;
+	    }
+
+	    if (warn_implicit_dimensions
+		&& port_set_ && net_set_
+		&& port_.empty() && !net_.empty()) {
+		  cerr << get_fileline() << ": warning: "
+		       << "Port declaration of " << basename()
+		       << " inherits dimensions from var/net." << endl;
+	    }
+
+	    bool dimensions_ok = true;
 	    vector<netrange_t> plist, nlist;
 	    /* If they exist get the port definition MSB and LSB */
 	    if (port_set_ && !port_.empty()) {
@@ -990,7 +987,7 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 			cerr << get_fileline() << ": PWire::elaborate_sig: "
 			     << "Evaluate ranges for port " << basename() << endl;
 		  }
-		  bad_range |= evaluate_ranges(des, scope, plist, port_);
+		  dimensions_ok &= evaluate_ranges(des, scope, this, plist, port_);
 		  nlist = plist;
 		    /* An implicit port can have a range so note that here. */
 		  is_implicit_scalar = false;
@@ -998,13 +995,13 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
            assert(port_set_ || port_.empty());

 	    /* If they exist get the net/etc. definition MSB and LSB */
-	    if (net_set_ && !net_.empty() && !bad_range) {
+	    if (net_set_ && !net_.empty() && dimensions_ok) {
 		  nlist.clear();
 		  if (debug_elaborate) {
 			cerr << get_fileline() << ": PWire::elaborate_sig: "
 			     << "Evaluate ranges for net " << basename() << endl;
 		  }
-		  bad_range |= evaluate_ranges(des, scope, nlist, net_);
+		  dimensions_ok &= evaluate_ranges(des, base_type_scope, this, nlist, net_);
 	    }
            assert(net_set_ || net_.empty());

@@ -1014,10 +1011,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 		       << ". Now check for consistency." << endl;
 	    }

-	    /* If we find errors here, then give up on this signal. */
-	    if (bad_range)
-		  return 0;
-
 	    /* We have a port size error */
            if (port_set_ && net_set_ && !test_ranges_eeq(plist, nlist)) {

@@ -1064,7 +1057,11 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const

 	    packed_dimensions = nlist;
 	    wid = netrange_width(packed_dimensions);
-
+	    if (wid > warn_dimension_size) {
+		  cerr << get_fileline() << ": warning: Vector size "
+		          "is greater than " << warn_dimension_size
+		       << "." << endl;
+	    }
      }

      unsigned nattrib = 0;
@@ -1073,7 +1070,11 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const


      list<netrange_t>unpacked_dimensions;
-      netdarray_t*netarray = 0;
+      netdarray_t*netdarray = 0;
+
+      NetScope*array_type_scope = scope;
+      if (uarray_type_ && !uarray_type_->name.nil())
+            array_type_scope = scope->find_typedef_scope(des, uarray_type_);

      for (list<pform_range_t>::const_iterator cur = unpacked_.begin()
 		 ; cur != unpacked_.end() ; ++cur) {
@@ -1085,46 +1086,63 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 	      // put all the packed dimensions there.
 	    if (use_lidx==0 && use_ridx==0) {
 		  netvector_t*vec = new netvector_t(packed_dimensions, data_type_);
+		  vec->set_signed(get_signed());
 		  packed_dimensions.clear();
-		  ivl_assert(*this, netarray==0);
-		  netarray = new netdarray_t(vec);
+		  ivl_assert(*this, netdarray==0);
+		  netdarray = new netdarray_t(vec);
+		  continue;
+	    }
+
+	      // Special case: Detect the mark for a QUEUE
+	      // declaration, which is the dimensions [null:max_idx].
+	    if (dynamic_cast<PENull*>(use_lidx)) {
+		  netvector_t*vec = new netvector_t(packed_dimensions, data_type_);
+		  vec->set_signed(get_signed());
+		  packed_dimensions.clear();
+		  ivl_assert(*this, netdarray==0);
+		  long max_idx;
+		  if (use_ridx) {
+			NetExpr*tmp = elab_and_eval(des, array_type_scope, use_ridx,
+			                            -1, true);
+			NetEConst*cv = dynamic_cast<NetEConst*>(tmp);
+			if (cv == 0) {
+			      cerr << get_fileline() << ": error: queue '" << name_
+			           << "' bound must be a constant!" << endl;
+			      des->errors += 1;
+			      max_idx = -1;
+			} else {
+			      verinum res = cv->value();
+			      if (res.is_defined()) {
+				    max_idx = res.as_long();
+				    if (max_idx < 0) {
+					  cerr << get_fileline() << ": error: queue '"
+					       << name_ << "' bound must be positive ("
+					       << max_idx << ")!" << endl;
+					  des->errors += 1;
+					  max_idx = -1;
+				    }
+			      } else {
+				    cerr << get_fileline() << ": error: queue '" << name_
+				         << "' bound is undefined!" << endl;
+				    des->errors += 1;
+				    max_idx = -1;
+			      }
+			}
+		  } else max_idx = -1;
+		  netdarray = new netqueue_t(vec, max_idx);
 		  continue;
 	    }

 	      // Cannot handle dynamic arrays of arrays yet.
-	    ivl_assert(*this, netarray==0);
-	    ivl_assert(*this, use_lidx && use_ridx);
-
-	    NetExpr*lexp = elab_and_eval(des, scope, use_lidx, -1, true);
-	    NetExpr*rexp = elab_and_eval(des, scope, use_ridx, -1, true);
-
-	    if ((lexp == 0) || (rexp == 0)) {
-		  cerr << get_fileline() << ": internal error: There is "
-		       << "a problem evaluating indices for ``"
-		       << name_ << "''." << endl;
-		  des->errors += 1;
-		  return 0;
-	    }
-
-	    bool const_flag = true;
-	    verinum lval, rval;
-	    const_flag &= get_const_argument(lexp, lval);
-	    const_flag &= get_const_argument(rexp, rval);
-	    delete rexp;
-	    delete lexp;
+	    ivl_assert(*this, netdarray==0);

 	    long index_l, index_r;
-	    if (! const_flag) {
-		  cerr << get_fileline() << ": error: The indices "
-		       << "are not constant for array ``"
-		       << name_ << "''." << endl;
-		  des->errors += 1;
-                    /* Attempt to recover from error, */
-	          index_l = 0;
-	          index_r = 0;
-	    } else {
-		  index_l = lval.as_long();
-		  index_r = rval.as_long();
+	    evaluate_range(des, array_type_scope, this, *cur, index_l, index_r);
+
+	    if (abs(index_r - index_l) > warn_dimension_size) {
+		  cerr << get_fileline() << ": warning: Array dimension "
+		          "is greater than " << warn_dimension_size
+		       << "." << endl;
 	    }

 	    unpacked_dimensions.push_back(netrange_t(index_l, index_r));
@@ -1157,6 +1175,14 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const

      NetLogic*pull = 0;
      if (wtype == NetNet::SUPPLY0 || wtype == NetNet::SUPPLY1) {
+	    if (debug_elaborate) {
+		  cerr << get_fileline() << ": debug: "
+		       << "Generate a SUPPLY pull for the ";
+		  if (wtype == NetNet::SUPPLY0) cerr << "supply0";
+		  else cerr << "supply1";
+		  cerr << " net." << endl;
+	    }
+
 	    NetLogic::TYPE pull_type = (wtype==NetNet::SUPPLY1)
 		  ? NetLogic::PULLUP
 		  : NetLogic::PULLDOWN;
@@ -1167,14 +1193,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 	    pull->pin(0).drive1(IVL_DR_SUPPLY);
 	    des->add_node(pull);
 	    wtype = NetNet::WIRE;
-
-	    if (debug_elaborate) {
-		  cerr << get_fileline() << ": debug: "
-		       << "Generate a SUPPLY pull for the ";
-		  if (wtype == NetNet::SUPPLY0) cerr << "supply0";
-		  else cerr << "supply1";
-		  cerr << " net." << endl;
-	    }
      }


@@ -1185,27 +1203,17 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 	      // should already have been elaborated. All we need to
 	      // do right now is locate the netclass_t object for the
 	      // class, and use that to build the net.
-	    netclass_t*use_type = locate_class_type(des, scope, class_type);
-	    if (use_type == 0) {
-		  cerr << get_fileline() << ": internal error: "
-		       << "Class " << class_type->name
-		       << " isn't elaborated in scope=" << scope_path(scope) << endl;
-		  des->errors += 1;
-	    }
-	    ivl_assert(*this, use_type);
-	    if (debug_elaborate) {
-		  cerr << get_fileline() << ": debug: "
-		       << "Create class instance signal " << wtype
-		       << " " << name_ << endl;
-	    }
-	      // (No arrays of classes)
-	    list<netrange_t> use_unpacked;
-	    sig = new NetNet(scope, name_, wtype, use_unpacked, use_type);
+
+	    ivl_assert(*this, class_type->save_elaborated_type);
+	    netclass_t*use_type = class_type->save_elaborated_type;
+
+	    sig = new NetNet(scope, name_, wtype, unpacked_dimensions, use_type);

      } else if (struct_type_t*struct_type = dynamic_cast<struct_type_t*>(set_data_type_)) {
 	      // If this is a struct type, then build the net with the
 	      // struct type.
-	    netstruct_t*use_type = elaborate_struct_type(des, scope, struct_type);
+	    ivl_type_s*tmp_type = struct_type->elaborate_type(des, scope);
+	    netstruct_t*use_type = dynamic_cast<netstruct_t*>(tmp_type);
 	    if (debug_elaborate) {
 		  cerr << get_fileline() << ": debug: Create signal " << wtype;
 		  if (use_type->packed())
@@ -1216,11 +1224,11 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 		  cerr << " in scope " << scope_path(scope) << endl;
 	    }

-	    sig = new NetNet(scope, name_, wtype, use_type);
+	    sig = new NetNet(scope, name_, wtype, unpacked_dimensions, use_type);

      } else if (enum_type_t*enum_type = dynamic_cast<enum_type_t*>(set_data_type_)) {
 	    list<named_pexpr_t>::const_iterator sample_name = enum_type->names->begin();
-	    const netenum_t*use_enum = scope->enumeration_for_name(sample_name->name);
+	    const netenum_t*use_enum = base_type_scope->find_enumeration_for_name(des, sample_name->name);

 	    if (debug_elaborate) {
 		  cerr << get_fileline() << ": debug: Create signal " << wtype
@@ -1234,7 +1242,7 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 	    sig = new NetNet(scope, name_, wtype, unpacked_dimensions, use_enum);


-      } else if (netarray) {
+      } else if (netdarray) {

 	    if (debug_elaborate) {
 		  cerr << get_fileline() << ": debug: Create signal " << wtype
@@ -1244,7 +1252,7 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const

 	    ivl_assert(*this, packed_dimensions.empty());
 	    ivl_assert(*this, unpacked_dimensions.empty());
-	    sig = new NetNet(scope, name_, wtype, netarray);
+	    sig = new NetNet(scope, name_, wtype, netdarray);

      } else if (parray_type_t*parray_type = dynamic_cast<parray_type_t*>(set_data_type_)) {
 	      // The pform gives us a parray_type_t for packed arrays
@@ -1253,14 +1261,14 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const

 	      // The trick here is that the parray type has an
 	      // arbitrary sub-type, and not just a scalar bit...
-	    netparray_t*use_type = elaborate_parray_type(des, scope, parray_type);
-	      // Should not be getting packed dimensions other then
+	    netparray_t*use_type = elaborate_parray_type(des, scope, this, parray_type);
+	      // Should not be getting packed dimensions other than
 	      // through the parray type declaration.
 	    ivl_assert(*this, packed_dimensions.empty());

 	    if (debug_elaborate) {
 		  cerr << get_fileline() << ": debug: Create signal " << wtype
-		       << " parray=" << use_type->packed_dimensions()
+		       << " parray=" << use_type->static_dimensions()
 		       << " " << name_ << unpacked_dimensions
 		       << " in scope " << scope_path(scope) << endl;
 	    }
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2012-2020 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,11 +17,16 @@
 *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 */

+# include  "PExpr.h"
 # include  "pform_types.h"
 # include  "netlist.h"
 # include  "netclass.h"
 # include  "netdarray.h"
+# include  "netenum.h"
+# include  "netqueue.h"
+# include  "netparray.h"
 # include  "netscalar.h"
+# include  "netstruct.h"
 # include  "netvector.h"
 # include  "netmisc.h"
 # include  <typeinfo>
@@ -29,7 +34,68 @@

 using namespace std;

-ivl_type_s* data_type_t::elaborate_type(Design*des, NetScope*) const
+/*
+ * Some types have a list of ranges that need to be elaborated. This
+ * function elaborates the ranges referenced by "dims" into the vector
+ * "ranges".
+ */
+static void elaborate_array_ranges(Design*des, NetScope*scope,
+				   vector<netrange_t>&ranges,
+				   const list<pform_range_t>*dims)
+{
+      if (dims == 0)
+	    return;
+
+      for (list<pform_range_t>::const_iterator cur = dims->begin()
+		 ; cur != dims->end() ; ++ cur) {
+
+	    NetExpr*me = elab_and_eval(des, scope, cur->first, 0, true);
+
+	    NetExpr*le = elab_and_eval(des, scope, cur->second, 0, true);
+
+	      /* If elaboration failed for either expression, we
+		 should have already reported the error, so just
+		 skip the following evaluation to recover. */
+
+	    long mnum = 0, lnum = 0;
+	    if ( me && ! eval_as_long(mnum, me) ) {
+		  assert(0);
+		  des->errors += 1;
+	    }
+
+	    if ( le && ! eval_as_long(lnum, le) ) {
+		  assert(0);
+		  des->errors += 1;
+	    }
+
+	    ranges.push_back(netrange_t(mnum, lnum));
+      }
+}
+
+/*
+ * Elaborations of types may vary depending on the scope that it is
+ * done in, so keep a per-scope cache of the results.
+ */
+ivl_type_s* data_type_t::elaborate_type(Design*des, NetScope*scope)
+{
+	// User-defined types must be elaborated in the context
+	// where they were defined.
+      if (!name.nil())
+	    scope = scope->find_typedef_scope(des, this);
+
+      ivl_assert(*this, scope);
+      Definitions*use_definitions = scope;
+
+      map<Definitions*,ivl_type_s*>::iterator pos = cache_type_elaborate_.lower_bound(use_definitions);
+	  if (pos != cache_type_elaborate_.end() && pos->first == use_definitions)
+	     return pos->second;
+
+      ivl_type_s*tmp = elaborate_type_raw(des, scope);
+      cache_type_elaborate_.insert(pos, pair<NetScope*,ivl_type_s*>(scope, tmp));
+      return tmp;
+}
+
+ivl_type_s* data_type_t::elaborate_type_raw(Design*des, NetScope*) const
 {
      cerr << get_fileline() << ": internal error: "
 	   << "Elaborate method not implemented for " << typeid(*this).name()
@@ -38,7 +104,7 @@ ivl_type_s* data_type_t::elaborate_type(Design*des, NetScope*) const
      return 0;
 }

-ivl_type_s* atom2_type_t::elaborate_type(Design*des, NetScope*) const
+ivl_type_s* atom2_type_t::elaborate_type_raw(Design*des, NetScope*) const
 {
      switch (type_code) {
 	  case 64:
@@ -73,39 +139,32 @@ ivl_type_s* atom2_type_t::elaborate_type(Design*des, NetScope*) const
      }
 }

-ivl_type_s* class_type_t::elaborate_type(Design*, NetScope*scope) const
+ivl_type_s* class_type_t::elaborate_type_raw(Design*, NetScope*) const
 {
-      return scope->find_class(name);
+      ivl_assert(*this, save_elaborated_type);
+      return save_elaborated_type;
 }

-ivl_type_s* vector_type_t::elaborate_type(Design*des, NetScope*scope) const
+/*
+ * elaborate_type_raw for enumerations is actually mostly performed
+ * during scope elaboration so that the enumeration literals are
+ * available at the right time. At that time, the netenum_t* object is
+ * stashed in the scope so that I can retrieve it here.
+ */
+ivl_type_s* enum_type_t::elaborate_type_raw(Design*, NetScope*scope) const
+{
+      ivl_assert(*this, scope);
+      ivl_type_s*tmp = scope->enumeration_for_key(this);
+      if (tmp == 0 && scope->unit()) {
+	    tmp = scope->unit()->enumeration_for_key(this);
+}
+      return tmp;
+}
+
+ivl_type_s* vector_type_t::elaborate_type_raw(Design*des, NetScope*scope) const
 {
      vector<netrange_t> packed;
-
-      if (pdims.get()) {
-	    for (list<pform_range_t>::const_iterator cur = pdims->begin()
-		       ; cur != pdims->end() ; ++ cur) {
-
-		  NetExpr*me = elab_and_eval(des, scope, cur->first, 0, true);
-		  assert(me);
-
-		  NetExpr*le = elab_and_eval(des, scope, cur->second, 0, true);
-		  assert(le);
-
-		  long mnum = 0, lnum = 0;
-		  if ( ! eval_as_long(mnum, me) ) {
-			assert(0);
-			des->errors += 1;
-		  }
-
-		  if ( ! eval_as_long(lnum, le) ) {
-			assert(0);
-			des->errors += 1;
-		  }
-
-		  packed.push_back(netrange_t(mnum, lnum));
-	    }
-      }
+      elaborate_array_ranges(des, scope, packed, pdims.get());

      netvector_t*tmp = new netvector_t(packed, base_type);
      tmp->set_signed(signed_flag);
@@ -114,7 +173,7 @@ ivl_type_s* vector_type_t::elaborate_type(Design*des, NetScope*scope) const
      return tmp;
 }

-ivl_type_s* real_type_t::elaborate_type(Design*, NetScope*) const
+ivl_type_s* real_type_t::elaborate_type_raw(Design*, NetScope*) const
 {
      switch (type_code) {
 	  case REAL:
@@ -125,19 +184,93 @@ ivl_type_s* real_type_t::elaborate_type(Design*, NetScope*) const
      return 0;
 }

-ivl_type_s* string_type_t::elaborate_type(Design*, NetScope*) const
+ivl_type_s* string_type_t::elaborate_type_raw(Design*, NetScope*) const
 {
      return &netstring_t::type_string;
 }

-ivl_type_s* uarray_type_t::elaborate_type(Design*des, NetScope*scope) const
+ivl_type_s* parray_type_t::elaborate_type_raw(Design*des, NetScope*scope) const
+{
+      vector<netrange_t>packed;
+      elaborate_array_ranges(des, scope, packed, dims.get());
+
+      ivl_type_t etype = base_type->elaborate_type(des, scope);
+
+      return new netparray_t(packed, etype);
+}
+
+netstruct_t* struct_type_t::elaborate_type_raw(Design*des, NetScope*scope) const
+{
+      netstruct_t*res = new netstruct_t;
+
+      res->packed(packed_flag);
+
+      if (union_flag)
+	    res->union_flag(true);
+
+      for (list<struct_member_t*>::iterator cur = members->begin()
+		 ; cur != members->end() ; ++ cur) {
+
+	      // Elaborate the type of the member.
+	    struct_member_t*curp = *cur;
+	    ivl_type_t mem_vec = curp->type->elaborate_type(des, scope);
+	    if (mem_vec == 0)
+		  continue;
+
+	      // There may be several names that are the same type:
+	      //   <data_type> name1, name2, ...;
+	      // Process all the member, and give them a type.
+	    for (list<decl_assignment_t*>::iterator cur_name = curp->names->begin()
+		       ; cur_name != curp->names->end() ;  ++ cur_name) {
+		  decl_assignment_t*namep = *cur_name;
+
+		  netstruct_t::member_t memb;
+		  memb.name = namep->name;
+		  memb.net_type = mem_vec;
+		  res->append_member(des, memb);
+	    }
+      }
+
+      return res;
+}
+
+ivl_type_s* uarray_type_t::elaborate_type_raw(Design*des, NetScope*scope) const
 {

      ivl_type_t btype = base_type->elaborate_type(des, scope);

-      assert(dims->size() == 1);
+      assert(dims->size() >= 1);
      list<pform_range_t>::const_iterator cur = dims->begin();
-      assert(cur->first == 0 && cur->second==0);
-      ivl_type_s*res = new netdarray_t(btype);
+
+	// Special case: if the dimension is nil:nil, this is a
+	// dynamic array. Note that we only know how to handle dynamic
+	// arrays with 1 dimension at a time.
+      if (cur->first==0 && cur->second==0) {
+	    assert(dims->size()==1);
+	    ivl_type_s*res = new netdarray_t(btype);
+	    return res;
+      }
+
+	// Special case: if the dimension is null:nil. this is a queue.
+      if (dynamic_cast<PENull*>(cur->first)) {
+	    cerr << get_fileline() << ": sorry: "
+		 << "SV queues inside classes are not yet supported." << endl;
+	    des->errors += 1;
+
+	      // FIXME: Need to set the max size if cur->second is defined
+	    ivl_type_s*res = new netqueue_t(btype, -1);
+	    return res;
+      }
+
+      vector<netrange_t> dimensions;
+      bool dimensions_ok = evaluate_ranges(des, scope, this, dimensions, *dims);
+
+      if (!dimensions_ok) {
+	    cerr << get_fileline() << " : warning: "
+		 << "Bad dimensions for type here." << endl;
+      }
+
+      ivl_assert(*this, btype);
+      ivl_type_s*res = new netuarray_t(dimensions, btype);
      return res;
 }
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2011 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2017 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -123,6 +123,12 @@ bool NetFF::emit_node(struct target_t*tgt) const
      return true;
 }

+bool NetLatch::emit_node(struct target_t*tgt) const
+{
+      tgt->lpm_latch(this);
+      return true;
+}
+
 bool NetLiteral::emit_node(struct target_t*tgt) const
 {
      return tgt->net_literal(this);
@@ -167,6 +173,11 @@ bool NetSignExtend::emit_node(struct target_t*tgt) const
      return tgt->sign_extend(this);
 }

+bool NetSubstitute::emit_node(struct target_t*tgt) const
+{
+      return tgt->substitute(this);
+}
+
 bool NetUReduce::emit_node(struct target_t*tgt) const
 {
      return tgt->ureduce(this);
@@ -261,6 +272,17 @@ bool NetDisable::emit_proc(struct target_t*tgt) const
      return tgt->proc_disable(this);
 }

+bool NetDoWhile::emit_proc(struct target_t*tgt) const
+{
+      tgt->proc_do_while(this);
+      return true;
+}
+
+void NetDoWhile::emit_proc_recurse(struct target_t*tgt) const
+{
+      proc_->emit_proc(tgt);
+}
+
 bool NetForce::emit_proc(struct target_t*tgt) const
 {
      return tgt->proc_force(this);
@@ -272,6 +294,11 @@ bool NetForever::emit_proc(struct target_t*tgt) const
      return true;
 }

+bool NetForLoop::emit_proc(struct target_t*tgt) const
+{
+      return tgt->proc_block(as_block_);
+}
+
 bool NetFree::emit_proc(struct target_t*tgt) const
 {
      tgt->proc_free(this);
@@ -318,6 +345,11 @@ bool NetWhile::emit_proc(struct target_t*tgt) const
      return true;
 }

+void NetWhile::emit_proc_recurse(struct target_t*tgt) const
+{
+      proc_->emit_proc(tgt);
+}
+
 void NetBlock::emit_recurse(struct target_t*tgt) const
 {
      if (last_ == 0)
@@ -383,14 +415,13 @@ void NetRepeat::emit_recurse(struct target_t*tgt) const
 void netclass_t::emit_scope(struct target_t*tgt) const
 {
      class_scope_->emit_scope(tgt);
-      class_scope_->emit_defs(tgt);
 }

 void NetScope::emit_scope(struct target_t*tgt) const
 {
      if (debug_emit) {
 	    cerr << "NetScope::emit_scope: "
-		 << "Emit scope basename=" << basename() << endl;
+		 << "Emit scope " << scope_path(this) << endl;
      }

      tgt->scope(this);
@@ -404,9 +435,9 @@ void NetScope::emit_scope(struct target_t*tgt) const
 	    tgt->class_type(this, cur->second);
      }

-      for (list<netenum_t*>::const_iterator cur = enum_sets_.begin()
+      for (map<const enum_type_t*,netenum_t*>::const_iterator cur = enum_sets_.begin()
 		 ; cur != enum_sets_.end() ;  ++cur)
-	    tgt->enumeration(this, *cur);
+	    tgt->enumeration(this, cur->second);

      for (map<hname_t,NetScope*>::const_iterator cur = children_.begin()
 		 ; cur != children_.end() ; ++ cur )
@@ -435,12 +466,20 @@ bool NetScope::emit_defs(struct target_t*tgt) const
 {
      bool flag = true;

+      if (debug_emit) {
+	    cerr << "NetScope::emit_defs: "
+		 << "Emit definitions for " << scope_path(this) << endl;
+      }
+
      switch (type_) {
 	  case PACKAGE:
 	  case MODULE:
 	    for (map<hname_t,NetScope*>::const_iterator cur = children_.begin()
 		       ; cur != children_.end() ; ++ cur )
 		  flag &= cur->second->emit_defs(tgt);
+	    for (map<perm_string,netclass_t*>::const_iterator cur = classes_.begin()
+		       ; cur != classes_.end() ; ++ cur)
+		  flag &= cur->second->emit_defs(tgt);
 	    break;

 	  case FUNC:
@@ -459,9 +498,9 @@ bool NetScope::emit_defs(struct target_t*tgt) const
      return flag;
 }

-void NetWhile::emit_proc_recurse(struct target_t*tgt) const
+bool netclass_t::emit_defs(struct target_t*tgt) const
 {
-      proc_->emit_proc(tgt);
+      return class_scope_->emit_defs(tgt);
 }

 int Design::emit(struct target_t*tgt) const
@@ -516,6 +555,15 @@ int Design::emit(struct target_t*tgt) const
      for (const NetAnalogTop*idx = aprocs_ ;  idx ;  idx = idx->next_)
 	    proc_rc &= idx->emit(tgt);

+      if (nodes_rc == false)
+	    tgt->errors += 1;
+      if (tasks_rc == false)
+	    tgt->errors += 1;
+      if (proc_rc == false)
+	    tgt->errors += 1;
+      if (branches_rc == false)
+	    tgt->errors += 1;
+
      rc = tgt->end_design(this);

      if (nodes_rc == false)
@@ -523,7 +571,7 @@ int Design::emit(struct target_t*tgt) const
      if (tasks_rc == false)
 	    return -2;
      if (proc_rc == false)
-	  return -3;
+	    return -3;
      if (branches_rc == false)
 	    return -4;

@@ -535,6 +583,11 @@ void NetEAccess::expr_scan(struct expr_scan_t*tgt) const
      tgt->expr_access_func(this);
 }

+void NetEArrayPattern::expr_scan(struct expr_scan_t*tgt) const
+{
+      tgt->expr_array_pattern(this);
+}
+
 void NetEBinary::expr_scan(struct expr_scan_t*tgt) const
 {
      tgt->expr_binary(this);
@@ -575,6 +628,11 @@ void NetEEvent::expr_scan(struct expr_scan_t*tgt) const
      tgt->expr_event(this);
 }

+void NetELast::expr_scan(struct expr_scan_t*tgt) const
+{
+      tgt->expr_last(this);
+}
+
 void NetENetenum::expr_scan(struct expr_scan_t*tgt) const
 {
      tgt->expr_netenum(this);
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-1999 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2014 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -44,6 +44,14 @@ verinum* PEBinary::eval_const(Design*des, NetScope*scope) const
      verinum*res;

      switch (op_) {
+	  case 'p': {
+		if (l->is_defined() && r->is_defined()) {
+		      res = new verinum(pow(*l, *r));
+		} else {
+		      res = new verinum(verinum::Vx, l->len());
+		}
+		break;
+	  }
 	  case '+': {
 		if (l->is_defined() && r->is_defined()) {
 		      res = new verinum(*l + *r);
@@ -261,7 +269,7 @@ verinum* PEUnary::eval_const(Design*des, NetScope*scope) const
 		for (unsigned idx = 0 ;  idx < val->len() ;  idx += 1)
 		      tmp.set(idx, val->get(idx));

-		*val = v_not(tmp) + verinum(verinum::V1, 1);
+		*val = -tmp;
 		val->has_sign(true);
 		return val;
 	  }
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2016 Martin Whitaker (icarus@martin-whitaker.me.uk)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+# include "config.h"
+
+# include  <cstdlib>
+# include  <sstream>
+# include  "netlist.h"
+# include  "functor.h"
+# include  "compiler.h"
+# include  "ivl_assert.h"
+
+
+/*
+ * The exposenodes functor is primarily provided for use by the vlog95
+ * target. To implement some LPM objects, it needs to take a bit or part
+ * of one of the LPM inputs. If that input is not connected to a real
+ * net in the design, we need to create a net at that point so that
+ * there is something to which we can apply a bit or part select. This
+ * has the effect of splitting the synthesised structure at that point.
+ * Rather than creating a new net, we just look for a temporary net
+ * created by the synthesis process (there should be at least one) and
+ * reset its "local" flag. We also prepend another '_' to the synthetic
+ * name to avoid name collisions when we recompile the vlog95 output
+ * (because NetScope::local_symbol() doesn't actually check that the
+ * name it generates is unique).
+ */
+
+struct exposenodes_functor  : public functor_t {
+
+      unsigned count;
+
+      virtual void lpm_mux(Design*des, NetMux*obj);
+      virtual void lpm_part_select(Design*des, NetPartSelect*obj);
+      virtual void lpm_substitute(Design*des, NetSubstitute*obj);
+};
+
+static bool expose_nexus(Nexus*nex)
+{
+      NetNet*sig = 0;
+      for (Link*cur = nex->first_nlink() ; cur ; cur = cur->next_nlink()) {
+
+	      // Don't expose nodes that are attached to constants
+	    if (dynamic_cast<NetConst*> (cur->get_obj()))
+		  return false;
+	    if (dynamic_cast<NetLiteral*> (cur->get_obj()))
+		  return false;
+
+	    NetNet*cur_sig = dynamic_cast<NetNet*> (cur->get_obj());
+	    if (cur_sig == 0)
+		  continue;
+
+	    if (!cur_sig->local_flag())
+		  return false;
+
+	    sig = cur_sig;
+      }
+      assert(sig);
+      ostringstream res;
+      res << "_" << sig->name();
+      sig->rename(lex_strings.make(res.str()));
+      sig->local_flag(false);
+      return true;
+}
+
+/*
+ * The vlog95 target implements a wide mux as a hierarchy of 2:1 muxes,
+ * picking off one bit of the select input at each level of the hierarchy.
+ */
+void exposenodes_functor::lpm_mux(Design*, NetMux*obj)
+{
+      if (obj->sel_width() == 1)
+	    return;
+
+      if (expose_nexus(obj->pin_Sel().nexus()))
+	    count += 1;
+}
+
+/*
+ * A VP part select is going to select a part from its input.
+ */
+void exposenodes_functor::lpm_part_select(Design*, NetPartSelect*obj)
+{
+      if (obj->dir() != NetPartSelect::VP)
+	    return;
+
+      if (expose_nexus(obj->pin(1).nexus()))
+	    count += 1;
+}
+
+/*
+ * A substitute is going to select one or two parts from the wider input signal.
+ */
+void exposenodes_functor::lpm_substitute(Design*, NetSubstitute*obj)
+{
+      if (expose_nexus(obj->pin(1).nexus()))
+	    count += 1;
+}
+
+void exposenodes(Design*des)
+{
+      exposenodes_functor exposenodes;
+      exposenodes.count = 0;
+      if (verbose_flag) {
+	    cout << " ... Look for intermediate nodes" << endl << flush;
+      }
+      des->functor(&exposenodes);
+      if (verbose_flag) {
+	    cout << " ... Exposed " << exposenodes.count
+		 << " intermediate signals." << endl << flush;
+      }
+}
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2013 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2020 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -274,7 +274,18 @@ NetNet* NetEBComp::synthesize(Design*des, NetScope*scope, NetExpr*root)

      if (op_ == 'E' || op_ == 'N') {
 	    NetCaseCmp*gate = new NetCaseCmp(scope, scope->local_symbol(),
-					     width, op_=='E'?true:false);
+					     width, op_=='E' ? NetCaseCmp::EEQ : NetCaseCmp::NEQ);
+	    gate->set_line(*this);
+	    connect(gate->pin(0), osig->pin(0));
+	    connect(gate->pin(1), lsig->pin(0));
+	    connect(gate->pin(2), rsig->pin(0));
+	    des->add_node(gate);
+	    return osig;
+      }
+
+      if (op_ == 'w' || op_ == 'W') {
+	    NetCaseCmp*gate = new NetCaseCmp(scope, scope->local_symbol(),
+					     width, op_=='w' ? NetCaseCmp::WEQ : NetCaseCmp::WNE);
 	    gate->set_line(*this);
 	    connect(gate->pin(0), osig->pin(0));
 	    connect(gate->pin(1), lsig->pin(0));
@@ -335,6 +346,7 @@ NetNet* NetEBComp::synthesize(Design*des, NetScope*scope, NetExpr*root)
 		  des->errors += 1;
 		  return 0;
 	    }
+	    // fallthrough
 	  case 'e': // ==
 	    connect(dev->pin_AEB(), osig->pin(0));
 	    break;
@@ -353,6 +365,7 @@ NetNet* NetEBComp::synthesize(Design*des, NetScope*scope, NetExpr*root)
 		  des->errors += 1;
 		  return 0;
 	    }
+	    // fallthrough
 	  case 'n': // !=
 	    connect(dev->pin_ANEB(), osig->pin(0));
 	    break;
@@ -386,7 +399,8 @@ NetNet* NetEBPow::synthesize(Design*des, NetScope*scope, NetExpr*root)
      powr->set_line(*this);
      des->add_node(powr);

-      powr->set_signed( has_sign() );
+        // The lpm_pwr object only cares about the signedness of the exponent.
+      powr->set_signed( right_->has_sign() );

      connect(powr->pin_DataA(), lsig->pin(0));
      connect(powr->pin_DataB(), rsig->pin(0));
@@ -531,27 +545,40 @@ NetNet* NetEBLogic::synthesize(Design*des, NetScope*scope, NetExpr*root)
 	    return 0;
      }

-      netvector_t*osig_tmp = new netvector_t(expr_type());
-      NetNet*osig = new NetNet(scope, scope->local_symbol(),
-			       NetNet::IMPLICIT, osig_tmp);
-      osig->set_line(*this);
-      osig->local_flag(true);
-
      NetLogic*olog;
      perm_string oname = scope->local_symbol();

 	/* Create the logic OR/AND gate. This has a single bit output,
 	 * with single bit inputs for the two operands. */
-      if (op() == 'o') {
-	    olog = new NetLogic(scope, oname, 3, NetLogic::OR, 1, true);
-      } else {
-	    assert(op() == 'a');
+      switch (op()) {
+	case 'a':
 	    olog = new NetLogic(scope, oname, 3, NetLogic::AND, 1, true);
+	    break;
+	case 'o':
+	    olog = new NetLogic(scope, oname, 3, NetLogic::OR, 1, true);
+	    break;
+	case 'q':
+	    olog = new NetLogic(scope, oname, 3, NetLogic::IMPL, 1, true);
+	    break;
+	case 'Q':
+	    olog = new NetLogic(scope, oname, 3, NetLogic::EQUIV, 1, true);
+	    break;
+	default:
+	    cerr << get_fileline() << ": sorry: "
+	         << human_readable_op(op_)
+	         << " is not currently supported." << endl;
+	    des->errors += 1;
+	    return 0;
      }
-
      olog->set_line(*this);
      des->add_node(olog);

+      netvector_t*osig_tmp = new netvector_t(expr_type());
+      NetNet*osig = new NetNet(scope, scope->local_symbol(),
+			       NetNet::IMPLICIT, osig_tmp);
+      osig->set_line(*this);
+      osig->local_flag(true);
+
      connect(osig->pin(0), olog->pin(0));

 	/* The left and right operands have already been reduced to a
@@ -733,12 +760,18 @@ NetNet* NetEConcat::synthesize(Design*des, NetScope*scope, NetExpr*root)
 	    }
      }

-      if (flag == false) return 0;
+      if (flag == false) {
+	    delete[]tmp;
+	    return 0;
+      }

      ivl_assert(*this, data_type != IVL_VT_NO_TYPE);

 	/* If this is a replication of zero just return 0. */
-      if (expr_width() == 0) return 0;
+      if (expr_width() == 0) {
+	    delete[]tmp;
+	    return 0;
+      }

 	/* Make a NetNet object to carry the output vector. */
      perm_string path = scope->local_symbol();
@@ -1138,18 +1171,29 @@ NetNet* NetESelect::synthesize(Design *des, NetScope*scope, NetExpr*root)
      if (sub->vector_width() == expr_width())
 	    return sub;

-	// The vector_width is not exactly right, so the source is
-	// probably asking for padding. Create nodes to do sign
-	// extension or 0 extension, depending on the has_sign() mode
-	// of the expression.
-
      netvector_t*net_vec = new netvector_t(expr_type(), expr_width()-1, 0);
      net_vec->set_signed(has_sign());
      NetNet*net = new NetNet(scope, scope->local_symbol(),
 			      NetNet::IMPLICIT, net_vec);
      net->set_line(*this);
      net->local_flag(true);
-      if (has_sign()) {
+
+	// It may still happen that the expression is wider than the selection,
+	// and there was no part select created earlier (size casting).
+      if(expr_width() < sub->vector_width()) {
+	    NetPartSelect*sel = new NetPartSelect(sub, 0, expr_width(),
+                                                  NetPartSelect::VP, has_sign());
+	    sel->set_line(*this);
+	    des->add_node(sel);
+
+	    connect(net->pin(0), sel->pin(0));
+
+	// The vector_width is not exactly right, so the source is
+	// probably asking for padding. Create nodes to do sign
+	// extension or 0 extension, depending on the has_sign() mode
+	// of the expression.
+
+      } else if (has_sign()) {
 	    NetSignExtend*pad = new NetSignExtend(scope,
 						  scope->local_symbol(),
 						  expr_width());
@@ -1166,7 +1210,6 @@ NetNet* NetESelect::synthesize(Design *des, NetScope*scope, NetExpr*root)
 	    cat->set_line(*this);
 	    des->add_node(cat);

-	    assert(expr_width() > sub->vector_width());
 	    unsigned pad_width = expr_width() - sub->vector_width();
 	    verinum pad((uint64_t)0, pad_width);
 	    NetConst*con = new NetConst(scope, scope->local_symbol(),
@@ -1271,6 +1314,24 @@ NetNet* NetETernary::synthesize(Design *des, NetScope*scope, NetExpr*root)
 */
 NetNet* NetESignal::synthesize(Design*des, NetScope*scope, NetExpr*root)
 {
+	// If this is a synthesis with a specific value for the
+	// signal, then replace it (here) with a constant value.
+      if (net_->scope()==scope && net_->name()==scope->genvar_tmp) {
+	    netvector_t*tmp_vec = new netvector_t(net_->data_type(),
+						  net_->vector_width()-1, 0);
+	    NetNet*tmp = new NetNet(scope, scope->local_symbol(),
+				    NetNet::IMPLICIT, tmp_vec);
+	    tmp->set_line(*this);
+	    tmp->local_flag(true);
+	    verinum tmp_val ((uint64_t)scope->genvar_tmp_val, net_->vector_width());
+	    NetConst*tmp_const = new NetConst(scope, scope->local_symbol(), tmp_val);
+	    tmp_const->set_line(*this);
+	    des->add_node(tmp_const);
+
+	    connect(tmp->pin(0), tmp_const->pin(0));
+	    return tmp;
+      }
+
      if (word_ == 0)
 	    return net_;

@@ -1310,16 +1371,17 @@ static NetEvWait* make_func_trigger(Design*des, NetScope*scope, NetExpr*root)
      NetEvWait*trigger = 0;

      NexusSet*nset = root->nex_input(false);
-      if (nset && (nset->count() > 0)) {
+      if (nset && (nset->size() > 0)) {
            NetEvent*ev = new NetEvent(scope->local_symbol());
            ev->set_line(*root);
+            ev->local_flag(true);

            NetEvProbe*pr = new NetEvProbe(scope, scope->local_symbol(),
                                           ev, NetEvProbe::ANYEDGE,
-                                           nset->count());
+                                           nset->size());
            pr->set_line(*root);
-            for (unsigned idx = 0 ;  idx < nset->count() ;  idx += 1)
-                  connect(nset[0][idx], pr->pin(idx));
+            for (unsigned idx = 0 ;  idx < nset->size() ;  idx += 1)
+                  connect(nset->at(idx).lnk, pr->pin(idx));

            des->add_node(pr);

@@ -1440,6 +1502,12 @@ NetNet* NetEUFunc::synthesize(Design*des, NetScope*scope, NetExpr*root)
      osig->local_flag(true);
      connect(net->pin(0), osig->pin(0));

+      if (debug_synth2) {
+	    cerr << get_fileline() << ": NetEUFunc::synthesize: "
+		 << "result_sig_->vector_width()=" << result_sig_->vector_width()
+		 << ", osig->vector_width()=" << osig->vector_width() << endl;
+      }
+
        /* Connect the pins to the arguments. */
      NetFuncDef*def = func_->func_def();
      for (unsigned idx = 0; idx < eparms.size(); idx += 1) {
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2012 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2016 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -78,6 +78,10 @@ void functor_t::lpm_ff(Design*, NetFF*)
 {
 }

+void functor_t::lpm_latch(Design*, NetLatch*)
+{
+}
+
 void functor_t::lpm_logic(Design*, NetLogic*)
 {
 }
@@ -102,6 +106,10 @@ void functor_t::sign_extend(Design*, NetSignExtend*)
 {
 }

+void functor_t::lpm_substitute(Design*, NetSubstitute*)
+{
+}
+
 void functor_t::lpm_ureduce(Design*, NetUReduce*)
 {
 }
@@ -215,6 +223,11 @@ void NetFF::functor_node(Design*des, functor_t*fun)
      fun->lpm_ff(des, this);
 }

+void NetLatch::functor_node(Design*des, functor_t*fun)
+{
+      fun->lpm_latch(des, this);
+}
+
 void NetLiteral::functor_node(Design*des, functor_t*fun)
 {
      fun->lpm_literal(des, this);
@@ -255,6 +268,11 @@ void NetSignExtend::functor_node(Design*des, functor_t*fun)
      fun->sign_extend(des, this);
 }

+void NetSubstitute::functor_node(Design*des, functor_t*fun)
+{
+      fun->lpm_substitute(des, this);
+}
+
 void NetUReduce::functor_node(Design*des, functor_t*fun)
 {
      fun->lpm_ureduce(des, this);
@@ -1,7 +1,7 @@
-#ifndef __functor_H
-#define __functor_H
+#ifndef IVL_functor_H
+#define IVL_functor_H
 /*
- * Copyright (c) 1999-2008,2012 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2016 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -75,6 +75,9 @@ struct functor_t {
 	/* This method is called for each FF in the design. */
      virtual void lpm_ff(class Design*des, class NetFF*);

+	/* This method is called for each LATCH in the design. */
+      virtual void lpm_latch(class Design*des, class NetLatch*);
+
 	/* Handle LPM combinational logic devices. */
      virtual void lpm_logic(class Design*des, class NetLogic*);

@@ -89,6 +92,9 @@ struct functor_t {
 	/* This method is called for each power. */
      virtual void lpm_pow(class Design*des, class NetPow*);

+	/* This method is called for each part substitute. */
+      virtual void lpm_substitute(class Design*des, class NetSubstitute*);
+
 	/* This method is called for each unary reduction gate. */
      virtual void lpm_ureduce(class Design*des, class NetUReduce*);

@@ -105,4 +111,4 @@ struct proc_match_t {
      virtual int block(class NetBlock*);
 };

-#endif
+#endif /* IVL_functor_H */
@@ -1,10 +1,10 @@
-.TH iverilog-vpi 1 "April 17th, 2009" "" "Version %M.%m.%n %E"
+.TH iverilog-vpi 1 "Jan 29th, 2017" "" "Version %M.%n%E"
 .SH NAME
 iverilog-vpi - Compile front end for VPI modules

 .SH SYNOPSIS
 .B iverilog-vpi
-[\-\-name=\fIname\fP]
+[options]
 \fIsourcefile\fP...

 .SH DESCRIPTION
@@ -15,9 +15,9 @@ list of C or C++ source files, and generates as output a linked VPI
 module. See the \fBvvp\fP(1) man page for a description of how the
 linked module is loaded by a simulation.

-The output is named after the first source file. For example, if the
-first source file is named \fIfoo.c\fP, the output becomes
-\fIfoo.vpi\fP.
+By default the output is named after the first source file. For
+example, if the first source file is named \fIfoo.c\fP, the output
+becomes \fIfoo.vpi\fP.

 .SH OPTIONS
 \fIiverilog\-vpi\fP accepts the following options:
@@ -26,10 +26,15 @@ first source file is named \fIfoo.c\fP, the output becomes
 Include the named library in the link of the VPI module. This allows
 VPI modules to further reference external libraries.

+.TP 8
+.B -L\fIdirectory\fP
+Add \fIdirectory\fP to the list of directories that will be searched
+for library files.
+
 .TP 8
 .B -I\fIdirectory\fP
-Add \fIdirectory\fP to the list of directories that will be search for
-header files.
+Add \fIdirectory\fP to the list of directories that will be searched
+for header files.

 .TP 8
 .B -D\fIdefine\fP
@@ -41,46 +46,38 @@ Normally, the output VPI module will be named after the first source
 file passed to the command. This flag sets the name (without the .vpi
 suffix) of the output vpi module.

-.TP 8
-.B --install-dir
-This flag causes the program to print the install directory for VPI
-modules, then exit. It is a convenience for makefiles or automated
-plug-in installers.
-
-.TP 8
-.B --cflags, --ldflags and --ldlibs
-These flags provide compile time information.
-
 .SH "PC-ONLY OPTIONS"

-The PC port of \fIiverilog\-vpi\fP includes two special flags needed to
-support the more intractable development environment. These flags help
-the program locate parts that it needs.
+When built as a native Windows program (using the MinGW toolchain),
+by default \fIiverilog\-vpi\fP will attempt to locate the MinGW tools
+needed to compile a VPI module on the system path (as set by the PATH
+environment variable). As an alternative, the user may specify the
+location of the MinGW tools via the following option.

 .TP 8
 .B -mingw=\fIpath\fP
-Tell the program the root of the Mingw compiler tool suite. The
+Tell the program the root of the MinGW compiler tool suite. The
 \fBvvp\fP runtime is compiled with this compiler, and this is the
-compiler that \fIiverilog\-vpi\fP expects to use to compile your source
-code. This is normally not needed, and if you do use it, it is only
-needed once. The compiler will save the \fIpath\fP in the registry for
-use later.
+compiler that \fIiverilog\-vpi\fP expects to use to compile your
+source code. If this option accompanies a list of files, it will
+apply to the current build only. If this option is provided on its
+own, \fIiverilog\-vpi\fP will save the \fIpath\fP in the registry
+and use that path in preference to the system path for subsequent
+operations, avoiding the need to specify it on the command line
+every time.
+
+.SH "INFORMATIONAL OPTIONS"
+
+\fIiverilog\-vpi\fP includes additional flags to let Makefile gurus
+peek at the configuration of the \fIiverilog\fP installation.  This way,
+Makefiles can be written that handle complex VPI builds natively, and
+without hard-coding values that depend on the system and installation.
+If used at all, these options must be used one at a time, and without
+any other options or directives.

 .TP 8
-.B -ivl=\fIpath\fP
-Set for the use during compilation the root if the Icarus Verilog
-install. This is the place where you installed Icarus Verilog when you
-ran the installer. This flag is also only needed once, and the path is
-stored in the registry for future use.
-
-.SH "UNIX-ONLY OPTIONS"
-
-The UNIX version of \fIiverilog\-vpi\fP includes additional flags to
-let Makefile gurus peek at the configuration of the \fIiverilog\fP
-installation.  This way, Makefiles can be written that handle complex VPI
-builds natively, and without hard-coding values that depend on the
-system and installation.  If used at all, these options must be
-used one at a time, and without any other options or directives.
+.B --install-dir
+Print the install directory for VPI modules.

 .TP 8
 .B --cflags
@@ -95,11 +92,6 @@ Print the linker flags (LDFLAGS) needed to link a VPI module.
 .B --ldlibs
 Print the libraries (LDLIBS) needed to link a VPI module.

-.TP 8
-.B -m32
-On 64bit systems that support it (and support vvp32) this flag
-requests a 32bit vpi binary instead of the default 64bit binary.
-
 .P
 Example GNU makefile that takes advantage of these flags:
 .IP "" 4
@@ -123,12 +115,12 @@ Steve Williams ([email protected])

 .SH SEE ALSO
 iverilog(1), vvp(1),
-.BR "<http://www.icarus.com/eda/verilog/>",
-.BR "<http://www.mingw.org>",
+.BR "<http://iverilog.icarus.com/>",
+.BR "<http://mingw-w64.yaxm.org/>",

 .SH COPYRIGHT
 .nf
-Copyright \(co  2002\-2009 Stephen Williams
+Copyright \(co  2002\-2017 Stephen Williams

 This document can be freely redistributed according to the terms of the
 GNU General Public License version 2.0
@@ -35,6 +35,7 @@ CCSRC=
 CXSRC=
 OBJ=
 LIB=
+LIBDIR=
 OUT=
 INCOPT=
 DEFS=
@@ -81,6 +82,9 @@ do
    -l*) LIB="$LIB $parm"
 	 ;;

+    -L*) LIBDIR="$LIBDIR $parm"
+	 ;;
+
    -I*) INCOPT="$INCOPT $parm"
 	 ;;

@@ -92,6 +96,11 @@ do
 	 exit;
 	 ;;

+    --ccflags)
+	 echo "$CXXFLAGS"
+	 exit;
+	 ;;
+
    --ldflags)
 	 echo "$LDFLAGS"
 	 exit;
@@ -148,4 +157,4 @@ then
 fi

 echo "Making $OUT from $OBJ..."
-exec $LD -o $OUT $LDFLAGS $OBJ $LIB $LDLIBS
+exec $LD -o $OUT $LDFLAGS $LIBDIR $OBJ $LIB $LDLIBS
@@ -125,6 +125,7 @@ ivl_lpm_enable
 ivl_lpm_file
 ivl_lpm_lineno
 ivl_lpm_name
+ivl_lpm_negedge
 ivl_lpm_q
 ivl_lpm_scope
 ivl_lpm_select
@@ -141,6 +142,7 @@ ivl_lpm_width

 ivl_lval_idx
 ivl_lval_mux
+ivl_lval_nest
 ivl_lval_part_off
 ivl_lval_property_idx
 ivl_lval_sel_type
@@ -179,6 +181,7 @@ ivl_parameter_width
 ivl_path_condit
 ivl_path_delay
 ivl_path_is_condit
+ivl_path_is_parallel
 ivl_path_scope
 ivl_path_source
 ivl_path_source_negedge
@@ -209,6 +212,9 @@ ivl_scope_enumerates
 ivl_scope_event
 ivl_scope_events
 ivl_scope_file
+ivl_scope_func_type
+ivl_scope_func_signed
+ivl_scope_func_width
 ivl_scope_is_auto
 ivl_scope_is_cell
 ivl_scope_lineno
@@ -275,6 +281,7 @@ ivl_stmt_block_stmt
 ivl_stmt_call
 ivl_stmt_case_count
 ivl_stmt_case_expr
+ivl_stmt_case_quality
 ivl_stmt_case_stmt
 ivl_stmt_cond_expr
 ivl_stmt_cond_false
@@ -289,6 +296,7 @@ ivl_stmt_lval
 ivl_stmt_lvals
 ivl_stmt_lwidth
 ivl_stmt_name
+ivl_stmt_needs_t0_trigger
 ivl_stmt_nevent
 ivl_stmt_opcode
 ivl_stmt_parm
@@ -1,7 +1,7 @@
-#ifndef __ivl_alloc_H
-#define __ivl_alloc_H
+#ifndef IVL_ivl_alloc_H
+#define IVL_ivl_alloc_H
 /*
- *  Copyright (C) 2010  Cary R. (cygcary@yahoo.com)
+ *  Copyright (C) 2010-2014  Cary R. (cygcary@yahoo.com)
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
@@ -26,6 +26,7 @@
 #  include <stdio.h>
 #endif

+#if defined(__GNUC__)
 /*
 * Define a safer version of malloc().
 */
@@ -82,5 +83,6 @@
      } \
      __ivl_rtn; \
 })
-
 #endif
+
+#endif /* IVL_ivl_alloc_H */
@@ -1,5 +1,7 @@
+#ifndef IVL_ivl_assert_H
+#define IVL_ivl_assert_H
 /*
- * Copyright (c) 2007-2010 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2007-2014 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,9 +19,6 @@
 *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 */

-#ifndef __ivl_assert_h
-#define __ivl_assert_h
-
 # include  <cstdlib>

 #define ivl_assert(tok, expression)  \
@@ -32,4 +31,4 @@
 	    } \
      } while (0)

-#endif
+#endif /* IVL_ivl_assert_H */
@@ -1,7 +1,7 @@
-#ifndef __ivl_target_H
-#define __ivl_target_H
+#ifndef IVL_ivl_target_H
+#define IVL_ivl_target_H
 /*
- * Copyright (c) 2000-2013 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2020 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -24,7 +24,7 @@

 /* Re the _CLASS define: clang++ wants this to be class to match the
 * definition, but clang (the C) compiler needs it to be a struct
- * since class is not defined in C. They are effecively both pointers
+ * since class is not defined in C. They are effectively both pointers
 * to an object so everything works out. */

 #ifdef __cplusplus
@@ -41,6 +41,12 @@
 # define __attribute__(x)
 #endif

+#if defined(__cplusplus) && defined(_MSC_VER)
+# define ENUM_UNSIGNED_INT : unsigned int
+#else
+# define ENUM_UNSIGNED_INT
+#endif
+
 _BEGIN_DECL

 /*
@@ -201,7 +207,7 @@ typedef enum ivl_dis_domain_e {
      IVL_DIS_CONTINUOUS = 2
 } ivl_dis_domain_t;

-typedef enum ivl_drive_e {
+typedef enum ivl_drive_e ENUM_UNSIGNED_INT {
      IVL_DR_HiZ    = 0,
      IVL_DR_SMALL  = 1,
      IVL_DR_MEDIUM = 2,
@@ -228,6 +234,7 @@ typedef enum ivl_expr_type_e {
      IVL_EX_NEW    = 23,
      IVL_EX_NULL   = 22,
      IVL_EX_NUMBER = 5,
+      IVL_EX_ARRAY_PATTERN  = 26,
      IVL_EX_PROPERTY = 24,
      IVL_EX_REALNUM  = 16,
      IVL_EX_SCOPE  = 6,
@@ -242,7 +249,7 @@ typedef enum ivl_expr_type_e {
      IVL_EX_UNARY = 14
 } ivl_expr_type_t;

-typedef enum ivl_select_type_e {
+typedef enum ivl_select_type_e ENUM_UNSIGNED_INT {
      IVL_SEL_OTHER = 0,
      IVL_SEL_IDX_UP = 1,
      IVL_SEL_IDX_DOWN = 2
@@ -258,6 +265,8 @@ typedef enum ivl_logic_e {
      IVL_LO_BUFT   = 24, /* transparent bufz. (NOT "tri-state") */
      IVL_LO_BUFZ   =  5,
      IVL_LO_CMOS   = 22,
+      IVL_LO_EQUIV  = 25,
+      IVL_LO_IMPL   = 26,
      IVL_LO_NAND   =  6,
      IVL_LO_NMOS   =  7,
      IVL_LO_NOR    =  8,
@@ -273,7 +282,6 @@ typedef enum ivl_logic_e {
      IVL_LO_RPMOS  = 16,
      IVL_LO_XNOR   = 18,
      IVL_LO_XOR    = 19,
-
      IVL_LO_UDP    = 21
 } ivl_logic_t;

@@ -299,6 +307,10 @@ typedef enum ivl_lpm_type_e {
      IVL_LPM_CONCAT = 16,
      IVL_LPM_CONCATZ = 36, /* Transparent concat */
      IVL_LPM_CMP_EEQ= 18, /* Case EQ (===) */
+      IVL_LPM_CMP_EQX= 37, /* Wildcard EQ (casex) */
+      IVL_LPM_CMP_EQZ= 38, /* casez EQ */
+      IVL_LPM_CMP_WEQ= 41,
+      IVL_LPM_CMP_WNE= 42,
      IVL_LPM_CMP_EQ = 10,
      IVL_LPM_CMP_GE =  1,
      IVL_LPM_CMP_GT =  2,
@@ -306,6 +318,7 @@ typedef enum ivl_lpm_type_e {
      IVL_LPM_CMP_NEE= 19, /* Case NE (!==) */
      IVL_LPM_DIVIDE = 12,
      IVL_LPM_FF     =  3,
+      IVL_LPM_LATCH  = 40,
      IVL_LPM_MOD    = 13,
      IVL_LPM_MULT   =  4,
      IVL_LPM_MUX    =  5,
@@ -325,6 +338,7 @@ typedef enum ivl_lpm_type_e {
      IVL_LPM_SHIFTR =  7,
      IVL_LPM_SIGN_EXT=27,
      IVL_LPM_SUB    =  8,
+      IVL_LPM_SUBSTITUTE=39,
      /* IVL_LPM_RAM =  9, / obsolete */
      IVL_LPM_UFUNC  = 14
 } ivl_lpm_type_t;
@@ -341,10 +355,13 @@ typedef enum ivl_path_edge_e {

 /* Processes are initial, always, or final blocks with a statement. This is
   the type of the ivl_process_t object. */
-typedef enum ivl_process_type_e {
-      IVL_PR_INITIAL = 0,
-      IVL_PR_ALWAYS  = 1,
-      IVL_PR_FINAL   = 2
+typedef enum ivl_process_type_e ENUM_UNSIGNED_INT {
+      IVL_PR_INITIAL      = 0,
+      IVL_PR_ALWAYS       = 1,
+      IVL_PR_ALWAYS_COMB  = 3,
+      IVL_PR_ALWAYS_FF    = 4,
+      IVL_PR_ALWAYS_LATCH = 5,
+      IVL_PR_FINAL        = 2
 } ivl_process_type_t;

 /* These are the sorts of reasons a scope may come to be. These types
@@ -402,6 +419,7 @@ typedef enum ivl_statement_type_e {
      IVL_ST_DELAY   = 11,
      IVL_ST_DELAYX  = 12,
      IVL_ST_DISABLE = 13,
+      IVL_ST_DO_WHILE = 30,
      IVL_ST_FORCE   = 14,
      IVL_ST_FOREVER = 15,
      IVL_ST_FORK    = 16,
@@ -417,6 +435,14 @@ typedef enum ivl_statement_type_e {
      IVL_ST_WHILE   = 23
 } ivl_statement_type_t;

+/* Case statements can be tagged as unique/unique0/priority. */
+typedef enum ivl_case_quality_t {
+      IVL_CASE_QUALITY_BASIC    = 0,  /* no quality flags */
+      IVL_CASE_QUALITY_UNIQUE   = 1,
+      IVL_CASE_QUALITY_UNIQUE0  = 2,
+      IVL_CASE_QUALITY_PRIORITY = 3
+} ivl_case_quality_t;
+
 /* SystemVerilog allows a system function to be called as a task. */
 typedef enum ivl_sfunc_as_task_e {
      IVL_SFUNC_AS_TASK_ERROR   = 0,
@@ -426,7 +452,7 @@ typedef enum ivl_sfunc_as_task_e {

 /* This is the type of a variable, and also used as the type for an
   expression. */
-typedef enum ivl_variable_type_e {
+typedef enum ivl_variable_type_e ENUM_UNSIGNED_INT {
      IVL_VT_VOID    = 0,  /* Not used */
      IVL_VT_NO_TYPE = 1,  /* Place holder for missing/unknown type. */
      IVL_VT_REAL    = 2,
@@ -435,6 +461,7 @@ typedef enum ivl_variable_type_e {
      IVL_VT_STRING  = 5,
      IVL_VT_DARRAY  = 6,  /* Array (esp. dynamic array) */
      IVL_VT_CLASS   = 7,  /* SystemVerilog class instances */
+      IVL_VT_QUEUE   = 8,  /* SystemVerilog queue instances */
      IVL_VT_VECTOR = IVL_VT_LOGIC /* For compatibility */
 } ivl_variable_type_t;

@@ -498,6 +525,10 @@ extern ivl_island_t ivl_branch_island(ivl_branch_t obj);
 * ivl_path_is_condit
 *    Is this a conditional structure? Needed for ifnone.
 *
+ * ivl_path_is_parallel
+ *    This returns true if the path is a parallel connection and
+ *    false if the path is a full connection.
+ *
 * ivl_path_source_posedge
 * ivl_path_source_negedge
 *    These functions return true if the source is edge sensitive.
@@ -508,6 +539,8 @@ extern uint64_t ivl_path_delay(ivl_delaypath_t obj, ivl_path_edge_t pt);
 extern ivl_nexus_t ivl_path_condit(ivl_delaypath_t obj);
 extern int ivl_path_is_condit(ivl_delaypath_t obj);

+extern int ivl_path_is_parallel(ivl_delaypath_t obj);
+
 extern int ivl_path_source_posedge(ivl_delaypath_t obj);
 extern int ivl_path_source_negedge(ivl_delaypath_t obj);

@@ -775,7 +808,7 @@ extern unsigned ivl_event_lineno(ivl_event_t net);
 *
 * ivl_expr_net_type
 *    This is used in some cases to carry more advanced type
- *    descriptions. Over the long run, all type informatino will be
+ *    descriptions. Over the long run, all type information will be
 *    moved into the ivl_type_t type description method.
 *
 * ivl_expr_width
@@ -826,6 +859,20 @@ extern unsigned ivl_event_lineno(ivl_event_t net);
 * table. That number can be passed to ivl_type_prop_*() functions to
 * get details about the property.
 *
+ * If the property is an array, then the ivl_expr_oper1() function
+ * returns the canonical expression for accessing the element of the
+ * property.
+ *
+ * - IVL_EX_NEW
+ * This expression takes one or two operands. The first operand,
+ * returned by ivl_expr_oper1() is the number of elements to create
+ * for the dynamic array. The second operand, if present, is returned
+ * by the ivl_expr_oper2() function. If this returns a non-nil
+ * expression, it is the initial value to be written to the elements
+ * of the array. If the expression is an IVL_EX_ARRAY_PATTERN, then
+ * this is the very special case of a list of values to be written to
+ * array elements.
+ *
 * - IVL_EX_SELECT
 * This expression takes two operands, oper1 is the expression to
 * select from, and oper2 is the selection base. The ivl_expr_width
@@ -834,9 +881,9 @@ extern unsigned ivl_event_lineno(ivl_event_t net);
 * conversion from signal units to vector units, so the result of
 * ivl_expr_oper1 should range from 0 to ivl_expr_width().
 *
- * This exprsesion is also used to implement string substrings. If the
+ * This expression is also used to implement string substrings. If the
 * sub-expression (oper1) is IVL_VT_STRING, then the base expression
- * (oper2) is a charaster address, with 0 the first address of the
+ * (oper2) is a character address, with 0 the first address of the
 * string, 1 the second, and so on. This is OPPOSITE how a part select
 * of a string cast to a vector works, to be aware. The size of the
 * expression is an even multiple of 8, and is 8 times the number of
@@ -894,17 +941,17 @@ extern const char* ivl_expr_name(ivl_expr_t net);
 extern ivl_nature_t ivl_expr_nature(ivl_expr_t net);
  /* IVL_EX_BINARY IVL_EX_UNARY */
 extern char        ivl_expr_opcode(ivl_expr_t net);
-  /* IVL_EX_BINARY  IVL_EX_UNARY, IVL_EX_MEMORY IVL_EX_TERNARY */
+  /* IVL_EX_BINARY  IVL_EX_UNARY, IVL_EX_MEMORY IVL_EX_NEW IVL_EX_TERNARY */
 extern ivl_expr_t  ivl_expr_oper1(ivl_expr_t net);
-  /* IVL_EX_BINARY IVL_EX_TERNARY */
+  /* IVL_EX_BINARY IVL_EX_NEW IVL_EX_TERNARY */
 extern ivl_expr_t  ivl_expr_oper2(ivl_expr_t net);
  /* IVL_EX_TERNARY */
 extern ivl_expr_t  ivl_expr_oper3(ivl_expr_t net);
  /* and expression */
 extern ivl_parameter_t ivl_expr_parameter(ivl_expr_t net);
-  /* IVL_EX_CONCAT IVL_EX_UFUNC */
+  /* IVL_EX_ARRAY_PATTERN IVL_EX_CONCAT IVL_EX_UFUNC */
 extern ivl_expr_t  ivl_expr_parm(ivl_expr_t net, unsigned idx);
-  /* IVL_EX_CONCAT IVL_EX_SFUNC IVL_EX_UFUNC */
+  /* IVL_EX_ARRAY_PATTERN IVL_EX_CONCAT IVL_EX_SFUNC IVL_EX_UFUNC */
 extern unsigned    ivl_expr_parms(ivl_expr_t net);
  /* IVL_EX_CONCAT */
 extern unsigned    ivl_expr_repeat(ivl_expr_t net);
@@ -1219,8 +1266,10 @@ extern unsigned    ivl_lpm_lineno(ivl_lpm_t net);
 * width of a general power is the XXXX of the widths of the
 * inputs.
 *
- * Power may be signed. If so, the output should be sign extended
- * to fill in its result.
+ * Power may be signed. This indicates the type of the exponent. The
+ * base will always be treated as unsigned. The compiler must ensure
+ * the width of the base is equal to the width of the output to
+ * obtain the correct result when the base is really a signed value.
 *
 * - Part Select (IVL_LPM_PART_VP and IVL_LPM_PART_PV)
 * There are two part select devices, one that extracts a part from a
@@ -1253,7 +1302,7 @@ extern unsigned    ivl_lpm_lineno(ivl_lpm_t net);
 * width of the part. The ivl_lpm_q is the part end, and the
 * ivl_lpm_data(0) is the non-part end.
 *
- * - Comparisons (IVL_LPM_CMP_GT/GE/EQ/NE/EEQ/NEE)
+ * - Comparisons (IVL_LPM_CMP_GT/GE/EQ/NE/EEQ/NEE/EQX/EQZ)
 * These devices have two inputs, available by the ivl_lpm_data()
 * function, and one output available by the ivl_lpm_q function. The
 * output width is always 1, but the ivl_lpm_width() returns the width
@@ -1265,6 +1314,11 @@ extern unsigned    ivl_lpm_lineno(ivl_lpm_t net);
 * magnitude compare, the signedness does matter. In any case, the
 * result of the compare is always unsigned.
 *
+ * The EQX and EQZ nodes are wildcard compares, where xz bits (EQX) or
+ * z bits (EQZ) in the data(1) operand are treated as wildcards. no
+ * bits in the data(0) operand are wild. This matches the
+ * SystemVerilog convention for the ==? operator.
+ *
 * - Mux Device (IVL_LPM_MUX)
 * The MUX device has a q output, a select input, and a number of data
 * inputs. The ivl_lpm_q output and the ivl_lpm_data inputs all have
@@ -1278,8 +1332,13 @@ extern unsigned    ivl_lpm_lineno(ivl_lpm_t net);
 * inputs and the Q. All the types must be exactly the same.
 *
 * - D-FlipFlop (IVL_LPM_FF)
- * This data is an edge sensitive register. The ivl_lpm_q output and
- * single ivl_lpm_data input are the same with, ivl_lpm_width. This
+ * This device is an edge sensitive register. The ivl_lpm_q output and
+ * single ivl_lpm_data input are the same width, ivl_lpm_width. This
+ * device carries a vector like other LPM devices.
+ *
+ * - Latch (IVL_LPM_LATCH)
+ * This device is an asynchronous latch. The ivl_lpm_q output and
+ * single ivl_lpm_data input are the same width, ivl_lpm_width. This
 * device carries a vector like other LPM devices.
 *
 * - Memory port (IVL_LPM_RAM) (deprecated in favor of IVL_LPM_ARRAY)
@@ -1314,7 +1373,7 @@ extern unsigned    ivl_lpm_lineno(ivl_lpm_t net);
 * repeated to get the desired width. The ivl core assures that the
 * input vector is exactly ivl_lpm_width() / ivl_lpm_size() bits.
 *
- * - Sign Exend (IVL_LPM_SIGN_EXT)
+ * - Sign Extend (IVL_LPM_SIGN_EXT)
 * This node takes a single input and generates a single output. The
 * input must be signed, and the output will be a vector sign extended
 * to the desired width. The ivl_lpm_width() value is the output
@@ -1390,22 +1449,25 @@ extern ivl_nexus_t ivl_lpm_sync_set(ivl_lpm_t net);
 extern ivl_expr_t  ivl_lpm_sset_value(ivl_lpm_t net);
  /* IVL_LPM_ARRAY */
 extern ivl_signal_t ivl_lpm_array(ivl_lpm_t net);
-  /* IVL_LPM_PART */
+  /* IVL_LPM_PART IVL_LPM_SUBSTITUTE */
 extern unsigned ivl_lpm_base(ivl_lpm_t net);
  /* IVL_LPM_FF */
+extern unsigned    ivl_lpm_negedge(ivl_lpm_t net);
 extern ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net);
  /* IVL_LPM_UFUNC */
 extern ivl_scope_t  ivl_lpm_define(ivl_lpm_t net);
-  /* IVL_LPM_FF */
+  /* IVL_LPM_FF IVL_LPM_LATCH*/
 extern ivl_nexus_t ivl_lpm_enable(ivl_lpm_t net);
  /* IVL_LPM_ADD IVL_LPM_CONCAT IVL_LPM_FF IVL_LPM_PART IVL_LPM_MULT
     IVL_LPM_MUX IVL_LPM_POW IVL_LPM_SHIFTL IVL_LPM_SHIFTR IVL_LPM_SUB
-     IVL_LPM_UFUNC */
+     IVL_LPM_UFUNC IVL_LPM_SUBSTITUTE IVL_LPM_LATCH */
 extern ivl_nexus_t ivl_lpm_data(ivl_lpm_t net, unsigned idx);
-  /* IVL_LPM_ADD IVL_LPM_MULT IVL_LPM_POW IVL_LPM_SUB */
+  /* IVL_LPM_ADD IVL_LPM_MULT IVL_LPM_POW IVL_LPM_SUB IVL_LPM_CMP_EQ
+     IVL_LPM_CMP_EEQ IVL_LPM_CMP_EQX IVL_LPM_CMP_EQZ IVL_LPM_CMP_NEE */
 extern ivl_nexus_t ivl_lpm_datab(ivl_lpm_t net, unsigned idx);
  /* IVL_LPM_ADD IVL_LPM_FF IVL_LPM_MULT IVL_LPM_PART IVL_LPM_POW
-     IVL_LPM_SUB IVL_LPM_UFUNC */
+     IVL_LPM_SUB IVL_LPM_UFUNC IVL_LPM_CMP_EEQ IVL_LPM_CMP_EQX
+     IVL_LPM_CMP_EQZ IVL_LPM_CMP_NEE IVL_LPM_SUBSTITUTE IVL_LPM_LATCH */
 extern ivl_nexus_t ivl_lpm_q(ivl_lpm_t net);
 extern ivl_drive_t ivl_lpm_drive0(ivl_lpm_t net);
 extern ivl_drive_t ivl_lpm_drive1(ivl_lpm_t net);
@@ -1432,12 +1494,11 @@ extern const char*ivl_lpm_string(ivl_lpm_t net);
 *    for the local part selecting I might to in the lval object, as
 *    well as the target object width.
 *
- * ivl_lval_mux
- *    If the l-value includes a bit select expression, this method
- *    returns an ivl_expr_t that represents that
- *    expression.  Otherwise, it returns 0.
+ * ivl_lval_mux (* obsolete *)
 *
- *    (Should this be combined with ivl_lval_idx? -Ed)
+ * ivl_lval_nest
+ *    If the l-value is an object more complex than a variable, then
+ *    this returns the nested l-value (and ivl_lval_sig==0).
 *
 * ivl_lval_sig
 *    If the l-value is a variable, this method returns the signal
@@ -1477,15 +1538,21 @@ extern const char*ivl_lpm_string(ivl_lpm_t net);
 * then the ivl_lval_idx expression must *not* be present.
 *
 * For array words, the ivl_lval_width is the width of the word.
+ *
+ * - Arrayed properties
+ * If the l-value is a class property, then the ivl_lval_idx function
+ * will return an expression if the property is in fact arrayed. The
+ * expression is the canonical index for elements in the property.
 */

 extern unsigned    ivl_lval_width(ivl_lval_t net);
-extern ivl_expr_t  ivl_lval_mux(ivl_lval_t net); /* XXXX Obsolete? */
+extern ivl_expr_t  ivl_lval_mux(ivl_lval_t net) __attribute__((deprecated)); /* XXXX Obsolete? */
 extern ivl_expr_t  ivl_lval_idx(ivl_lval_t net);
 extern ivl_expr_t  ivl_lval_part_off(ivl_lval_t net);
 extern ivl_select_type_t ivl_lval_sel_type(ivl_lval_t net);
 extern int ivl_lval_property_idx(ivl_lval_t net);
 extern ivl_signal_t ivl_lval_sig(ivl_lval_t net);
+extern ivl_lval_t  ivl_lval_nest(ivl_lval_t net);


 /* NEXUS
@@ -1706,6 +1773,13 @@ extern unsigned    ivl_parameter_lineno(ivl_parameter_t net);
 * ivl_scope_lineno
 *    Returns the instantiation file and line for this scope.
 *
+ * ivl_scope_func_type
+ * ivl_scope_func_signed
+ * ivl_scope_func_width
+ *
+ *    If the scope is a function, these function can be used to get
+ *    the type of the return value.
+ *
 * ivl_scope_is_auto
 *    Is the task or function declared to be automatic?
 *
@@ -1824,6 +1898,9 @@ extern const char*  ivl_scope_tname(ivl_scope_t net);
 extern int          ivl_scope_time_precision(ivl_scope_t net);
 extern int          ivl_scope_time_units(ivl_scope_t net);

+extern ivl_variable_type_t ivl_scope_func_type(ivl_scope_t net);
+extern int ivl_scope_func_signed(ivl_scope_t net);
+extern unsigned ivl_scope_func_width(ivl_scope_t net);

 /* SIGNALS
 * Signals are named things in the Verilog source, like wires and
@@ -2045,6 +2122,7 @@ extern unsigned ivl_stmt_lineno(ivl_statement_t net);
 *    handle disable statements.
 *
 * ivl_stmt_events
+ * ivl_stmt_needs_t0_trigger
 * ivl_stmt_nevent
 *    Statements that have event arguments (TRIGGER and WAIT) make
 *    those event objects available through these methods.
@@ -2159,6 +2237,8 @@ extern ivl_scope_t ivl_stmt_call(ivl_statement_t net);
 extern unsigned ivl_stmt_case_count(ivl_statement_t net);
  /* IVL_ST_CASE,IVL_ST_CASER,IVL_ST_CASEX,IVL_ST_CASEZ */
 extern ivl_expr_t ivl_stmt_case_expr(ivl_statement_t net, unsigned i);
+  /* IVL+ST_CASE,IVL_ST_CASER,IVL_ST_CASEX,IVL_ST_CASEZ */
+extern ivl_case_quality_t ivl_stmt_case_quality(ivl_statement_t net);
  /* IVL_ST_CASE,IVL_ST_CASER,IVL_ST_CASEX,IVL_ST_CASEZ */
 extern ivl_statement_t ivl_stmt_case_stmt(ivl_statement_t net, unsigned i);
  /* IVL_ST_CONDIT IVL_ST_CASE IVL_ST_REPEAT IVL_ST_WHILE */
@@ -2172,6 +2252,7 @@ extern ivl_expr_t ivl_stmt_delay_expr(ivl_statement_t net);
  /* IVL_ST_DELAY */
 extern uint64_t ivl_stmt_delay_val(ivl_statement_t net);
  /* IVL_ST_WAIT IVL_ST_TRIGGER */
+extern unsigned    ivl_stmt_needs_t0_trigger(ivl_statement_t net);
 extern unsigned    ivl_stmt_nevent(ivl_statement_t net);
 extern ivl_event_t ivl_stmt_events(ivl_statement_t net, unsigned idx);
  /* IVL_ST_CONTRIB */
@@ -2280,7 +2361,7 @@ extern const char* ivl_type_prop_name(ivl_type_t net, int idx);
 extern ivl_type_t  ivl_type_prop_type(ivl_type_t net, int idx);


-#if defined(__MINGW32__) || defined (__CYGWIN32__)
+#if defined(__MINGW32__) || defined (__CYGWIN__)
 #  define DLLEXPORT __declspec(dllexport)
 #else
 #  define DLLEXPORT
@@ -2310,4 +2391,6 @@ typedef const char* (*target_query_f) (const char*key);

 _END_DECL

-#endif
+#undef ENUM_UNSIGNED_INT
+
+#endif /* IVL_ivl_target_H */
@@ -1,7 +1,7 @@
-#ifndef __ivl_target_priv_H
-#define __ivl_target_priv_H
+#ifndef IVL_ivl_target_priv_H
+#define IVL_ivl_target_priv_H
 /*
- * Copyright (c) 2008 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2008-2019 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -51,7 +51,6 @@ struct ivl_design_s {
      ivl_process_t threads_;

 	// Keep arrays of root scopes.
-      std::map<const NetScope*,ivl_scope_t> classes;
      std::vector<ivl_scope_t> packages;
      std::vector<ivl_scope_t> roots;

@@ -90,4 +89,4 @@ struct ivl_island_s {

 extern std::ostream& operator << (std::ostream&o, ivl_drive_t str);

-#endif
+#endif /* IVL_ivl_target_priv_H */
@@ -44,7 +44,7 @@ INCLUDE_PATH = -I. -I.. -I$(srcdir) -I$(srcdir)/..
 endif

 CPPFLAGS = $(INCLUDE_PATH) @CPPFLAGS@ @DEFS@
-CFLAGS = @WARNING_FLAGS@ @CFLAGS@
+CFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CC@ @CFLAGS@
 LDFLAGS = @LDFLAGS@

 O = main.o lexor.o
@@ -60,7 +60,7 @@ distclean: clean
 	rm -f Makefile config.log

 cppcheck: $(O:.o=.c)
-	cppcheck --enable=all -f $(INCLUDE_PATH) $^
+	cppcheck --enable=all --std=posix --std=c99 --std=c++03 -f $(INCLUDE_PATH) $^

 Makefile: $(srcdir)/Makefile.in ../config.status
 	cd ..; ./config.status --file=ivlpp/$@
@@ -71,9 +71,11 @@ ivlpp@EXEEXT@: $O
 lexor.c: $(srcdir)/lexor.lex
 	$(LEX) -t $< > $@

-install: all installdirs $(libdir)/ivl$(suffix)/ivlpp@EXEEXT@
+install: all installdirs installfiles

-$(libdir)/ivl$(suffix)/ivlpp@EXEEXT@: ivlpp@EXEEXT@
+F = ivlpp@EXEEXT@
+
+installfiles: $(F) | installdirs
 	$(INSTALL_PROGRAM) ./ivlpp@EXEEXT@ "$(DESTDIR)$(libdir)/ivl$(suffix)/ivlpp@EXEEXT@"

 installdirs: $(srcdir)/../mkinstalldirs
@@ -1,7 +1,7 @@
-#ifndef __globals_H
-#define __globals_H
+#ifndef IVL_globals_H
+#define IVL_globals_H
 /*
- * Copyright (c) 1999-2009 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2017 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -22,11 +22,11 @@
 # include  <stdio.h>

 extern void reset_lexor(FILE*out, char*paths[]);
-extern void destroy_lexor();
+extern void destroy_lexor(void);
 extern void load_precompiled_defines(FILE*src);
 extern void define_macro(const char*name, const char*value, int keyword,
                         int argc);
-extern void free_macros();
+extern void free_macros(void);
 extern void dump_precompiled_defines(FILE*out);

 /* These variables contain the include directories to be searched when
@@ -53,7 +53,10 @@ extern char dep_mode;

 extern int verbose_flag;

-/* This is the entry to the lexer. */
-extern int yylex();
+extern int warn_redef;
+extern int warn_redef_all;

-#endif
+/* This is the entry to the lexer. */
+extern int yylex(void);
+
+#endif /* IVL_globals_H */
@@ -95,7 +95,7 @@ keys, with their corresponding values, are:
      This is exactly the same as the "-Dname=<value>" described above.

   I:<dir>
-      This is exctly the same as "-I<dir>".
+      This is exactly the same as "-I<dir>".

   relative include:<flag>
      The <flag> can be "true" or "false". This enables "relative
@@ -1,5 +1,5 @@
 const char COPYRIGHT[] =
-          "Copyright (c) 1999-2011 Stephen Williams ([email protected])";
+          "Copyright (c) 1999-2020 Stephen Williams ([email protected])";
 /*
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -98,6 +98,10 @@ int line_direct_flag = 0;
 unsigned error_count = 0;
 FILE *depend_file = NULL;

+/* Should we warn about macro redefinitions? */
+int warn_redef = 0;
+int warn_redef_all = 0;
+
 static int flist_read_flags(const char*path)
 {
      char line_buf[2048];
@@ -282,7 +286,7 @@ int main(int argc, char*argv[])
      include_dir[0] = 0;  /* 0 is reserved for the current files path. */
      include_dir[1] = strdup(".");

-      while ((opt=getopt(argc, argv, "F:f:K:Lo:p:P:vV")) != EOF) switch (opt) {
+      while ((opt=getopt(argc, argv, "F:f:K:Lo:p:P:vVW:")) != EOF) switch (opt) {

 	  case 'F':
 	    flist_read_flags(optarg);
@@ -336,6 +340,15 @@ int main(int argc, char*argv[])
 		break;
 	  }

+	  case 'W':
+	    if (strcmp(optarg, "redef-all") == 0) {
+		  warn_redef_all = 1;
+		  warn_redef = 1;
+	    } else if (strcmp(optarg, "redef-chg") == 0) {
+		  warn_redef = 1;
+	    }
+	    break;
+
 	  case 'v':
 	    fprintf(stderr, "Icarus Verilog Preprocessor version "
 		    VERSION " (" VERSION_TAG ")\n\n");
@@ -366,7 +379,10 @@ int main(int argc, char*argv[])
 		    "    -p<fil> - Write precompiled defines to <fil>\n"
 		    "    -P<fil> - Read precompiled defines from <fil>\n"
 		    "    -v      - Verbose\n"
-		    "    -V      - Print version information and quit\n",
+		    "    -V      - Print version information and quit\n"
+		    "    -W<cat> - Enable extra ivlpp warning category:\n"
+		    "               o redef-all - all macro redefinitions\n"
+		    "               o redef-chg - macro definition changes\n",
 		    argv[0]);
 	    return flag_errors;
      }
@@ -4,7 +4,7 @@

 %{
 /*
- * Copyright (c) 1998-2013 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2020 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -51,6 +51,22 @@
 */
 extern YYLTYPE yylloc;

+char* yytext_string_filter(const char*str, size_t str_len)
+{
+      if (str == 0) return 0;
+      char*buf = new char[str_len+1];
+      for (size_t idx = 0 ; idx < str_len ; idx += 1) {
+	    if (str[idx] == 0) {
+		  VLerror(yylloc, "error: Found nil (\\000) in string literal, replacing with space (\\015) character.");
+		  buf[idx] = ' ';
+	    } else {
+		  buf[idx] = str[idx];
+	    }
+      }
+      buf[str_len] = 0;
+      return buf;
+}
+
 char* strdupnew(char const *str)
 {
       return str ? strcpy(new char [strlen(str)+1], str) : 0;
@@ -72,6 +88,7 @@ static const char* set_file_name(char*text)
 void reset_lexor();
 static void line_directive();
 static void line_directive2();
+static void reset_all();

 verinum*make_unsized_binary(const char*txt);
 verinum*make_undef_highz_dec(const char*txt);
@@ -134,9 +151,17 @@ TU [munpf]
 \n { yylloc.first_line += 1; }

  /* C++ style comments start with / / and run to the end of the
-     current line. These are very easy to handle. */
+     current line. These are very easy to handle. The meta-comments
+     format is a little more tricky to handle, but do what we can. */

-"//".* { comment_enter = YY_START; BEGIN(LCOMMENT); }
+  /* The lexor detects "// synthesis translate_on/off" meta-comments,
+     we handle them here by turning on/off a flag. The pform uses
+     that flag to attach implicit attributes to "initial" and
+     "always" statements. */
+
+"//"{W}*"synthesis"{W}+"translate_on"{W}*\n { pform_mc_translate_on(true); }
+"//"{W}*"synthesis"{W}+"translate_off"{W}*\n { pform_mc_translate_on(false); }
+"//" { comment_enter = YY_START; BEGIN(LCOMMENT); }
 <LCOMMENT>.    { yymore(); }
 <LCOMMENT>\n   { yylloc.first_line += 1; BEGIN(comment_enter); }

@@ -179,8 +204,11 @@ TU [munpf]
 "!=" { return K_NE; }
 "===" { return K_CEQ; }
 "!==" { return K_CNE; }
+"==?" { return K_WEQ; }
+"!=?" { return K_WNE; }
 "||" { return K_LOR; }
 "&&" { return K_LAND; }
+"<->" { return K_LEQUIV; }
 "&&&" { return K_TAND; }
 "~|" { return K_NOR; }
 "~^" { return K_NXOR; }
@@ -219,16 +247,18 @@ TU [munpf]
 <CSTRING>\\\\ { yymore(); /* Catch \\, which is a \ escaping itself */ }
 <CSTRING>\\\" { yymore(); /* Catch \", which is an escaped quote */ }
 <CSTRING>\n   { BEGIN(0);
-                yylval.text = strdupnew(yytext);
+                yylval.text = yytext_string_filter(yytext, yyleng);
 		VLerror(yylloc, "Missing close quote of string.");
 		yylloc.first_line += 1;
 		return STRING; }
 <CSTRING>\"   { BEGIN(0);
-                yylval.text = strdupnew(yytext);
+      yylval.text = yytext_string_filter(yytext, yyleng);
 		yylval.text[strlen(yytext)-1] = 0;
 		return STRING; }
 <CSTRING>.    { yymore(); }

+  /* The UDP Table is a unique lexical environment. These are most
+     tokens that we can expect in a table. */
 <UDPTABLE>\(\?0\)    { return '_'; }
 <UDPTABLE>\(\?1\)    { return '+'; }
 <UDPTABLE>\(\?[xX]\) { return '%'; }
@@ -253,7 +283,7 @@ TU [munpf]
 <UDPTABLE>[xX]     { return 'x'; }
 <UDPTABLE>[nN]     { return 'n'; }
 <UDPTABLE>[pP]     { return 'p'; }
-<UDPTABLE>[01\?\*\-] { return yytext[0]; }
+<UDPTABLE>[01\?\*\-:;] { return yytext[0]; }

 <EDGES>"01" { return K_edge_descriptor; }
 <EDGES>"0x" { return K_edge_descriptor; }
@@ -296,13 +326,8 @@ TU [munpf]
 	    in_UDP = false;
 	    break;

-	    /* Translate these to checks if we already have or are
-	     * outside the declaration region. */
-	  case K_timeunit:
-	    if (have_timeunit_decl) rc = K_timeunit_check;
-	    break;
-	  case K_timeprecision:
-	    if (have_timeprec_decl) rc = K_timeprecision_check;
+	  case K_table:
+	    BEGIN(UDPTABLE);
 	    break;

 	  default:
@@ -319,8 +344,8 @@ TU [munpf]
      if (in_package_scope) {
 	    if (rc == IDENTIFIER) {
 		  if (data_type_t*type = pform_test_type_identifier(in_package_scope, yylval.text)) {
-			delete[]yylval.text;
-			yylval.data_type = type;
+			yylval.type_identifier.text = yylval.text;
+			yylval.type_identifier.type = type;
 			rc = TYPE_IDENTIFIER;
 		  }
 	    }
@@ -341,7 +366,7 @@ TU [munpf]
 	    }
      }

-	/* If this identifer names a previously declared package, then
+	/* If this identifier names a previously declared package, then
 	   return this as a PACKAGE_IDENTIFIER instead. */
      if (rc == IDENTIFIER && gn_system_verilog()) {
 	    if (PPackage*pkg = pform_test_package_identifier(yylval.text)) {
@@ -354,9 +379,9 @@ TU [munpf]
 	/* If this identifier names a previously declared type, then
 	   return this as a TYPE_IDENTIFIER instead. */
      if (rc == IDENTIFIER && gn_system_verilog()) {
-	    if (data_type_t*type = pform_test_type_identifier(yylval.text)) {
-		  delete[]yylval.text;
-		  yylval.data_type = type;
+	    if (data_type_t*type = pform_test_type_identifier(yylloc, yylval.text)) {
+		  yylval.type_identifier.text = yylval.text;
+		  yylval.type_identifier.type = type;
 		  rc = TYPE_IDENTIFIER;
 	    }
      }
@@ -375,9 +400,9 @@ TU [munpf]
 	    }
      }
      if (gn_system_verilog()) {
-	    if (data_type_t*type = pform_test_type_identifier(yylval.text)) {
-		  delete[]yylval.text;
-		  yylval.data_type = type;
+	    if (data_type_t*type = pform_test_type_identifier(yylloc, yylval.text)) {
+		  yylval.type_identifier.text = yylval.text;
+		  yylval.type_identifier.type = type;
 		  return TYPE_IDENTIFIER;
 	    }
      }
@@ -414,22 +439,38 @@ TU [munpf]

      if (strcmp(yytext,"$attribute") == 0)
 	    return KK_attribute;
+
+      if (gn_system_verilog() && strcmp(yytext,"$unit") == 0) {
+	    yylval.package = pform_units.back();
+	    return PACKAGE_IDENTIFIER;
+      }
+
      yylval.text = strdupnew(yytext);
      return SYSTEM_IDENTIFIER; }


-\'[sS]?[dD][ \t]*[0-9][0-9_]*  { yylval.number = make_unsized_dec(yytext);
-                            return BASED_NUMBER; }
-\'[sS]?[dD][ \t]*[xzXZ?]_* { yylval.number = make_undef_highz_dec(yytext);
-                             return BASED_NUMBER; }
-\'[sS]?[bB][ \t]*[0-1xzXZ_\?]+ { yylval.number = make_unsized_binary(yytext);
-                        return BASED_NUMBER; }
-\'[sS]?[oO][ \t]*[0-7xzXZ_\?]+ { yylval.number = make_unsized_octal(yytext);
-                        return BASED_NUMBER; }
-\'[sS]?[hH][ \t]*[0-9a-fA-FxzXZ_\?]+ { yylval.number = make_unsized_hex(yytext);
-                              return BASED_NUMBER; }
+\'[sS]?[dD][ \t]*[0-9][0-9_]* {
+      yylval.number = make_unsized_dec(yytext);
+      return BASED_NUMBER;
+}
+\'[sS]?[dD][ \t]*[xzXZ?]_* {
+      yylval.number = make_undef_highz_dec(yytext);
+      return BASED_NUMBER;
+}
+\'[sS]?[bB][ \t]*[0-1xzXZ?][0-1xzXZ?_]* {
+      yylval.number = make_unsized_binary(yytext);
+      return BASED_NUMBER;
+}
+\'[sS]?[oO][ \t]*[0-7xzXZ?][0-7xzXZ?_]* {
+      yylval.number = make_unsized_octal(yytext);
+      return BASED_NUMBER;
+}
+\'[sS]?[hH][ \t]*[0-9a-fA-FxzXZ?][0-9a-fA-FxzXZ?_]* {
+      yylval.number = make_unsized_hex(yytext);
+      return BASED_NUMBER;
+}
 \'[01xzXZ] {
-      if (generation_flag < GN_VER2005_SV) {
+      if (!gn_system_verilog()) {
 	    cerr << yylloc.text << ":" << yylloc.first_line << ": warning: "
 		 << "Using SystemVerilog 'N bit vector.  Use at least "
 		 << "-g2005-sv to remove this warning." << endl;
@@ -440,14 +481,22 @@ TU [munpf]
      generation_flag = generation_save;
      return UNBASED_NUMBER; }

+  /* Decimal numbers are the usual. But watch out for the UDPTABLE
+     mode, where there are no decimal numbers. Reject the match if we
+     are in the UDPTABLE state. */
 [0-9][0-9_]* {
-      yylval.number = make_unsized_dec(yytext);
-      based_size = yylval.number->as_ulong();
-      return DEC_NUMBER; }
+      if (YY_START==UDPTABLE) {
+	    REJECT;
+      } else {
+	    yylval.number = make_unsized_dec(yytext);
+	    based_size = yylval.number->as_ulong();
+	    return DEC_NUMBER;
+      }
+}

  /* This rule handles scaled time values for SystemVerilog. */
 [0-9][0-9_]*(\.[0-9][0-9_]*)?{TU}?s {
-      if(generation_flag & (GN_VER2005_SV | GN_VER2009 | GN_VER2012)) {
+      if (gn_system_verilog()) {
 	    yylval.text = strdupnew(yytext);
 	    return TIME_LITERAL;
      } else REJECT; }
@@ -534,11 +583,7 @@ TU [munpf]
 		    "definition." << endl;
 	    error_count += 1;
      } else {
-	    pform_set_default_nettype(NetNet::WIRE, yylloc.text,
-	                              yylloc.first_line);
-	    in_celldefine = false;
-	    uc_drive = UCD_NONE;
-	    pform_set_timescale(def_ts_units, def_ts_prec, 0, 0);
+	    reset_all();
      } }

  /* Notice and handle the `unconnected_drive directive. */
@@ -791,16 +836,27 @@ TU [munpf]
 * lexor. The level characters are normally accepted as other things,
 * so the parser needs to switch my mode when it believes in needs to.
 */
-void lex_start_table()
-{
-      BEGIN(UDPTABLE);
-}
-
 void lex_end_table()
 {
      BEGIN(INITIAL);
 }

+static unsigned truncate_to_integer_width(verinum::V*bits, unsigned size)
+{
+      if (size <= integer_width) return size;
+
+      verinum::V pad = bits[size-1];
+      if (pad == verinum::V1) pad = verinum::V0;
+
+      for (unsigned idx = integer_width; idx < size; idx += 1) {
+	    if (bits[idx] != pad) {
+		  yywarn(yylloc, "Unsized numeric constant truncated to integer width.");
+		  break;
+	    }
+      }
+      return integer_width;
+}
+
 verinum*make_unsized_binary(const char*txt)
 {
      bool sign_flag = false;
@@ -814,7 +870,7 @@ verinum*make_unsized_binary(const char*txt)
 	    ptr += 1;
      }

-      assert((tolower(*ptr) == 'b') || (generation_flag >= GN_VER2005_SV));
+      assert((tolower(*ptr) == 'b') || gn_system_verilog());
      if (tolower(*ptr) == 'b') {
 	    ptr += 1;
      } else {
@@ -829,6 +885,14 @@ verinum*make_unsized_binary(const char*txt)
      for (const char*idx = ptr ;  *idx ;  idx += 1)
 	    if (*idx != '_') size += 1;

+      if (size == 0) {
+	    VLerror(yylloc, "Numeric literal has no digits in it.");
+	    verinum*out = new verinum();
+	    out->has_sign(sign_flag);
+	    out->is_single(single_flag);
+	    return out;
+      }
+
      if ((based_size > 0) && (size > based_size)) yywarn(yylloc,
          "extra digits given for sized binary constant.");

@@ -858,6 +922,9 @@ verinum*make_unsized_binary(const char*txt)
 	    ptr += 1;
      }

+      if (gn_strict_expr_width_flag && (based_size == 0))
+	    size = truncate_to_integer_width(bits, size);
+
      verinum*out = new verinum(bits, size, false);
      out->has_sign(sign_flag);
      out->is_single(single_flag);
@@ -926,6 +993,9 @@ verinum*make_unsized_octal(const char*txt)
 	    ptr += 1;
      }

+      if (gn_strict_expr_width_flag && (based_size == 0))
+	    size = truncate_to_integer_width(bits, size);
+
      verinum*out = new verinum(bits, size, false);
      out->has_sign(sign_flag);
      delete[]bits;
@@ -1003,6 +1073,9 @@ verinum*make_unsized_hex(const char*txt)
 	    ptr += 1;
      }

+      if (gn_strict_expr_width_flag && (based_size == 0))
+	    size = truncate_to_integer_width(bits, size);
+
      verinum*out = new verinum(bits, size, false);
      out->has_sign(sign_flag);
      delete[]bits;
@@ -1192,6 +1265,9 @@ verinum*make_unsized_dec(const char*ptr)
           number represents we do not check for extra bits. */
 //      if (based_size > 0) { }

+      if (gn_strict_expr_width_flag && (based_size == 0))
+	    size = truncate_to_integer_width(bits, size);
+
      verinum*res = new verinum(bits, size, false);
      res->has_sign(signed_flag);

@@ -1534,6 +1610,18 @@ static void line_directive2()
      yylloc.first_line = lineno;
 }

+/*
+ * Reset all compiler directives. This will be called when a `resetall
+ * directive is encountered or when a new compilation unit is started.
+ */
+static void reset_all()
+{
+      pform_set_default_nettype(NetNet::WIRE, yylloc.text, yylloc.first_line);
+      in_celldefine = false;
+      uc_drive = UCD_NONE;
+      pform_set_timescale(def_ts_units, def_ts_prec, 0, 0);
+}
+
 extern FILE*vl_input;
 void reset_lexor()
 {
@@ -1542,6 +1630,14 @@ void reset_lexor()

 	/* Announce the first file name. */
      yylloc.text = set_file_name(strdupnew(vl_file.c_str()));
+
+      if (separate_compilation) {
+	    reset_all();
+	    if (!keyword_mask_stack.empty()) {
+		  lexor_keyword_mask = keyword_mask_stack.back();
+		  keyword_mask_stack.clear();
+	    }
+      }
 }

 /*
@@ -1551,7 +1647,7 @@ void destroy_lexor()
 {
 # ifdef FLEX_SCANNER
 #   if YY_FLEX_MAJOR_VERSION >= 2 && YY_FLEX_MINOR_VERSION >= 5
-#     if defined(YY_FLEX_SUBMINOR_VERSION) && YY_FLEX_SUBMINOR_VERSION >= 9
+#     if YY_FLEX_MINOR_VERSION > 5 || defined(YY_FLEX_SUBMINOR_VERSION) && YY_FLEX_SUBMINOR_VERSION >= 9
    yylex_destroy();
 #     endif
 #   endif
@@ -3,9 +3,11 @@
 * tokenType values are not initialized for the empty table entries.
 */
 %define initializer-suffix ,0,0
+%language=C++
+%define class-name Lkwd

 %{
-/* Command-line: gperf -o -i 1 -C -k 1-3,$ -L C -H keyword_hash -N check_identifier -tT lexor_keyword.gperf */
+/* Command-line: gperf -o -i 7 -C -k '1-4,6,9,$' -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf  */

 #include "config.h"
 #include "parse_misc.h"
@@ -362,7 +364,7 @@ int lexor_keyword_mask = 0;

 int lexor_keyword_code(const char*str, unsigned nstr)
 {
-      const struct lexor_keyword*rc = check_identifier(str, nstr);
+      const struct lexor_keyword*rc = Lkwd::check_identifier(str, nstr);
      if (rc == 0)
 	  return IDENTIFIER;
      else if ((rc->mask & lexor_keyword_mask) == 0)
@@ -1,7 +1,7 @@
-#ifndef __lexor_keyword_H
-#define __lexor_keyword_H
+#ifndef IVL_lexor_keyword_H
+#define IVL_lexor_keyword_H
 /*
- * Copyright (c) 2000 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -21,4 +21,4 @@

 extern int lexor_keyword_code (const char*str, unsigned len);

-#endif
+#endif /* IVL_lexor_keyword_H */
@@ -27,6 +27,11 @@ LineInfo::LineInfo()
 {
 }

+LineInfo::LineInfo(const LineInfo&that) :
+    file_(that.file_), lineno_(that.lineno_)
+{
+}
+
 LineInfo::~LineInfo()
 {
 }
@@ -1,7 +1,7 @@
-#ifndef __LineInfo_H
-#define __LineInfo_H
+#ifndef IVL_LineInfo_H
+#define IVL_LineInfo_H
 /*
- * Copyright (c) 1999-2011 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2014 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -36,6 +36,7 @@ using namespace std;
 class LineInfo {
    public:
      LineInfo();
+      LineInfo(const LineInfo&that);
      virtual ~LineInfo();

 	// Get a fully formatted file/lineno
@@ -54,4 +55,4 @@ class LineInfo {
      unsigned lineno_;
 };

-#endif
+#endif /* IVL_LineInfo_H */
--- a/Show More
+++ b/Show More