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Author SHA1 Message Date
Matt Guthaus d88ff01792 Change default operating conditions to OC 2018-02-23 13:38:55 -08:00
Matt Guthaus 29aa6002e6 Make period into p instead of remove it. Changes file names... 2018-02-23 12:50:02 -08:00
Matt Guthaus 9d1f31467e Move internal power to clock pin. Differentiate leakge power when CSb is high. 2018-02-23 12:21:32 -08:00
Matt Guthaus 107752b1fb Fix num words in example. 2018-02-23 12:17:43 -08:00
Matt Guthaus e3e7a31c6b Fix syntax error in functional test. 2018-02-23 07:47:01 -08:00
Hunter Nichols 62ad30e741 Added initial version of analytical power esitmation. Loops through instances but power estimate is not accurate. 2018-02-22 19:35:54 -08:00
Matt Guthaus 23f06bfa9a Reduce number of parameters in function calls for delay.py. 2018-02-22 11:14:58 -08:00
Hunter Nichols beb7dad9bc Added corner paramters to power functions. This commit does not compile (sorry) 2018-02-22 00:15:55 -08:00
Hunter Nichols d4a0f48d4f Added power calculations for inverter. Still testing. 2018-02-21 19:51:21 -08:00
mguthaus fbc2d772be Fix index order of golden tests. 2018-02-21 19:37:10 -08:00
Matt Guthaus b31f3c18af Change BSIM3 models to version 3.3.0. Add comment about multithreading selection. 2018-02-21 17:50:12 -08:00
mguthaus a22badeeb5 Fix pruned results 2018-02-21 17:48:46 -08:00
Matt Guthaus cf5f1e94b9 Update hspice results 2018-02-21 16:12:20 -08:00
Matt Guthaus 4e414b6c15 Fix unintended unmerge of changes. Bad bad. 2018-02-21 16:03:49 -08:00
Matt Guthaus a44346110b Fix merge of results. 2018-02-21 15:47:07 -08:00
Matt Guthaus fcacd46866 UPdate tests with new delay and slew names and leakage power. 2018-02-21 15:45:49 -08:00
mguthaus b8b2375346 Updated golden tests with new leakage aware power numbers. 2018-02-21 15:44:52 -08:00
Matt Guthaus 4b9ea66a42 Change names of variables to indicate transistions for clarity. 2018-02-21 15:13:46 -08:00
Matt Guthaus 71831e7737 Get delays only for successful run. 2018-02-21 14:05:39 -08:00
Matt Guthaus 9600dae7df Remove print statements. 2018-02-21 13:45:14 -08:00
Matt Guthaus 7d2f4386e2 Include leakage of non-trimmed array. Back out leakage of trimmed, add back leakage of nontrimmed. Reorgs simulation of delay and power a bit. 2018-02-21 13:38:43 -08:00
Hunter Nichols 179a27b0e3 Added some power functions. 2018-02-20 18:22:23 -08:00
Michael Timothy Grimes 4ea2a70a1b removing unnecessary unit test for pbitcell 2018-02-19 10:58:08 -08:00
mguthaus 5e8dff1e90 Fix unit tests with newest RBL delays. Fix tech problem with new spice models. 2018-02-16 13:54:05 -08:00
mguthaus c1c1ba38a3 Fix unit test to have fanout. 2018-02-16 11:53:38 -08:00
mguthaus 28fe49d069 Change RBL to allow stages and FO for configuration 2018-02-16 11:51:01 -08:00
mguthaus 1297cb4e40 Convert dff to VTG transistors in 45nm. Correct pin order in dff library cell. 2018-02-16 10:40:05 -08:00
mguthaus cb449a1cd2 Ignore non-rectangular pins. 2018-02-16 10:24:57 -08:00
Matt Guthaus 2e3e95efda Change ratio of delay line and RBL size. Need to tune it better automatically. 2018-02-14 16:50:08 -08:00
Matt Guthaus 9559421ca8 Connect dff array clk in rows and columns. 2018-02-14 16:46:26 -08:00
Matt Guthaus 2d87dcda46 dff array done except for clock net 2018-02-14 16:03:29 -08:00
Hunter Nichols 8ea384a761 Fixed merging issues with power branch 2018-02-14 15:21:42 -08:00
Matt Guthaus 0804a1eceb Add new DFF. Create DFF module. Start dff_array, not tested. 2018-02-14 15:16:28 -08:00
mguthaus 767990ca3b Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name. 2018-02-13 15:54:50 -08:00
Matt Guthaus f457091bba Fix typo in precharge. 2018-02-12 15:34:01 -08:00
Matt Guthaus e32b0b8f7a Change precharge input from clk to en 2018-02-12 15:32:47 -08:00
mguthaus e210d3d49a Make some common lib memory sizes. Update Makefile to auto build and char them all. 2018-02-12 12:00:59 -08:00
mguthaus 636099c5e1 Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library. 2018-02-12 11:22:47 -08:00
Matt Guthaus a12ebeed9f Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 09:33:23 -08:00
mguthaus 1795dc5677 Fix three unit tests to work with new lib corner files. 2018-02-11 20:43:41 -08:00
Michael Timothy Grimes 72fc92ad95 Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-02-11 16:47:53 -08:00
mguthaus f690532563 Add new corner-based lib files to unit tests. 2018-02-11 16:35:10 -08:00
Matt Guthaus 4dd075c7b7 Add V and C to names of lib files. 2018-02-11 16:34:32 -08:00
Matt Guthaus ce164fb7a8 Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-02-10 10:03:26 -08:00
Matt Guthaus b75eef3684 Fix syntax error. 2018-02-10 08:02:59 -08:00
Matt Guthaus 4d35972553 Get default corner options from tech file 2018-02-09 15:49:55 -08:00
Matt Guthaus f86985821a Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-09 15:33:03 -08:00
Matt Guthaus d19867e64c Move utils to base. 2018-02-09 10:42:23 -08:00
Matt Guthaus 84c798d9e4 Move last few modules to base dir 2018-02-09 10:29:37 -08:00
Matt Guthaus 7c83ef3f04 Fix missing subdir name. Comment about organization. 2018-02-09 10:27:43 -08:00
Matt Guthaus 15747b4759 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-02-09 10:25:28 -08:00
Matt Guthaus 7100d6f904 Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
Matt Guthaus 489faaba99 Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-02-09 10:20:56 -08:00
Matt Guthaus 13fd87d99e Accidentally committed to master. Merge branch 'master' into dev 2018-02-09 10:19:22 -08:00
Matt Guthaus d62da44329 Fix bug where path does not obey specified width. 2018-02-09 10:03:09 -08:00
mguthaus 5aa92a6549 Reorganize top-level functions a bit more. Add help info to banner. 2018-02-09 09:53:28 -08:00
mguthaus 8719a19377 Move parameter setting to config reading rather than status function. 2018-02-09 09:26:13 -08:00
Matt Guthaus 3c86f94549 Change argument name for lib in tests as well. 2018-02-08 15:28:49 -08:00
Matt Guthaus d684189241 Don't output text in SRAM during unit test. 2018-02-08 14:58:55 -08:00
Michael Timothy Grimes ce83b67350 Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-02-08 14:27:53 -08:00
Michael Timothy Grimes b90f5c9a59 pbitcell is now a multiport cell with a read transistor that connects to RBL and RROW and a read access transistor that connects to Q and gnd 
current commit works without drc errors on freepdk45 but has drc rules not included in scn3me_subm. Does have lvs errors
adding several unit tests: the basic one that tests the full functionality of the pbitcell, one with no write ports, and one with no read ports
 2018-02-08 14:21:15 -08:00
Matt Guthaus 17716191c1 Clean up time statements in openram output 2018-02-08 13:11:18 -08:00
Matt Guthaus 6c89f7965d Refactor openram.py. 2018-02-08 12:47:19 -08:00
Matt Guthaus 54c21f6282 Added method=gear back to ngspice simulation to fix convergence bug. 2018-02-07 21:07:11 -08:00
mguthaus e8f658d356 Add updated non-pruned unit test results. 2018-02-07 19:35:21 -08:00
mguthaus 63ce754c72 Update unit test results 2018-02-07 18:48:22 -08:00
Matt Guthaus 1b4be741df Fix broken print statements 2018-02-07 17:39:42 -08:00
Matt Guthaus 9cc46453a2 Fix PWL bug to output last value. Fix bug in setup/hold use of improved PWL function. 2018-02-07 15:43:09 -08:00
Matt Guthaus 2413304f4e Update replica bitline test for new parameters. Add small test and a larger test. 2018-02-07 15:15:19 -08:00
Matt Guthaus 1a491f3cd0 Make temp directory unique for test 30. Update LEF files after delay chain size change. 2018-02-07 15:05:21 -08:00
Matt Guthaus e93517529c Make delay chain length and bitcell load parameters to enable tuning. Rename the parameters to be more descriptive. 2018-02-07 14:54:59 -08:00
Matt Guthaus 8e91552701 Remvoe newline. 2018-02-07 14:33:29 -08:00
Matt Guthaus 5dacafc698 Disable gear integration in ngspice. Not sure it is necessary anymore and it is quite slow. 2018-02-07 14:20:15 -08:00
Matt Guthaus a2bf66b063 Add metal1 gnd line to prevent DRC errors when sizing delay chain. 2018-02-07 14:15:13 -08:00
Matt Guthaus 3e4ef36efe Clean up Python comments and improve comments in stimulus file. 2018-02-07 14:04:18 -08:00
Matt Guthaus 3820861ce8 Increase control delay line from 4 inverters to 3 FO4 delays. Need to dynamically adjust this. 2018-02-07 13:10:45 -08:00
Matt Guthaus 5c4999d4cc Move delay-specific stimulus commands to delay.py. Keep stimuli.py generic. 2018-02-07 12:58:47 -08:00
Matt Guthaus 8e91faaccb Remove version from OpenRAM. We will go bit git hashes. 2018-02-06 10:56:26 -08:00
mguthaus 3af1bbba26 Updated delay tests with new delays including ps, pd, as, ad. 2018-02-06 07:58:25 -08:00
mguthaus c3592b3d46 Added new timing tests with ps,pd,as,ad caps included. 2018-02-06 05:26:27 -08:00
Matt Guthaus 33b04bbca5 Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements. 2018-02-05 16:02:57 -08:00
Matt Guthaus 941094ce31 Return slews to 10-90 and 90-10 so I don't have to re-hardcode the results in unit tests. 2018-02-05 15:21:53 -08:00
Matt Guthaus 4505c0f74e Improve error to setup model dir path. Use it to override FreePDK45 too. 2018-02-05 15:12:12 -08:00
Matt Guthaus 85f4438280 Exit with error if model files are not found. 2018-02-05 15:09:21 -08:00
mguthaus e01d5b7c61 Disable virtual connects at top level LVS with Calibre. 2018-02-05 14:52:51 -08:00
Matt Guthaus e2e5f45cec Correct vague comments about char cycles. End simulation after last period even though a transition would mean a failed simulation. 2018-02-05 14:07:12 -08:00
Matt Guthaus a8e1abdce8 Use method=gear for ngspice to improve convergence. Split TD for trig and targ in measure statements. Start waiting for clk neg edge trigger at clk pos edge. 2018-02-05 11:36:46 -08:00
Matt Guthaus 92095e52f7 Update new LEF files for unit tests. 2018-02-05 10:27:56 -08:00
Matt Guthaus f21ff38cae Simplify via offsets in replica bitline. Route clk_bar in control over supply rail until we get channel router working. 2018-02-05 10:22:38 -08:00
Matt Guthaus 84b42b0170 Fix bug in trim netlist. Add info comments to spice netlist and trimmed netlist. Increase verbosity for simulations. 2018-02-02 19:33:07 -08:00
Matt Guthaus 7127895270 Update LEF files for unit tests 2018-02-02 15:51:29 -08:00
Matt Guthaus d6d96907ef Route to the right in the bank decode for DRC. 2018-02-02 15:50:45 -08:00
Matt Guthaus 1415d139a3 Specify file format for sp spice extension. 2018-02-02 15:33:35 -08:00
Matt Guthaus 3873f72a58 Ensure wells are spaced in the bank select and column decoder 2018-02-02 15:26:15 -08:00
Matt Guthaus ffcf58100e Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module. 2018-02-02 15:17:21 -08:00
Matt Guthaus 9d043b904e Remove unnecessary design reset 2018-02-02 14:26:53 -08:00
Matt Guthaus 27dbb95c19 Fix name of column mux. 2018-02-02 14:26:39 -08:00
Matt Guthaus 9d7dc4c552 Reset even if not purging temp files. 2018-02-02 14:26:09 -08:00
Matt Guthaus 2a8199c3ca Force re-extract of cells in DRC/LVS. 2018-02-02 14:21:31 -08:00
Matt Guthaus fb90b8f5fe Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder. 2018-02-02 14:08:56 -08:00
Matt Guthaus 3be59fb762 Change DRC output for magic to drc.summary just like calibre output. 2018-02-02 14:07:15 -08:00
Matt Guthaus 63392c8d71 Fix gnd connection in control logic. 2018-02-02 13:04:38 -08:00
Matt Guthaus 072c8e3174 Change LVS report file to same name as Calibre 2018-02-02 12:47:42 -08:00
Hunter Nichols db4913dd9c Added skeleton code for analytical power in functions with analytical delay. 2018-02-02 12:31:34 -08:00
Matt Guthaus 74064fc854 Replace LEF files with new changes. 2018-02-02 12:31:34 -08:00
Matt Guthaus e8d001a3f9 Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-02 12:31:33 -08:00
Matt Guthaus e4295ea61b Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-02-02 12:31:33 -08:00
Matt Guthaus 3e2d4d631d Do not require hspice during tests. Check if a valid simulator is found, however. 2018-02-02 12:31:33 -08:00
Matt Guthaus 7c9c16e29c Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message. 2018-02-02 12:31:33 -08:00
Matt Guthaus cc987daeb9 Add well around column muxes. 2018-02-02 12:31:33 -08:00
mguthaus 2ad52205c5 Clean up messages. 2018-02-02 12:31:33 -08:00
mguthaus d0c9382d97 Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-02-02 12:31:33 -08:00
Hunter Nichols 56f7caf59f Added first test power model to sram 2018-02-02 12:31:33 -08:00
Matt Guthaus 5527e73db0 Add descriptive exceptions along with cleanup in unit test checking. 2018-02-02 12:31:33 -08:00
Matt Guthaus be1c59f10c Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. 2018-02-02 12:31:33 -08:00
Matt Guthaus ea5eda91fc Connect all gnd rails of RBL. 2018-02-02 12:27:24 -08:00
Matt Guthaus d552d88f45 Add -d option to not delete temp directory on successful runs. 2018-02-01 11:53:02 -08:00
Matt Guthaus 8ef1e0af2c Replace LEF files with new changes. 2018-02-01 05:43:37 -08:00
Matt Guthaus 64546ad3dd Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-01 05:38:48 -08:00
Matt Guthaus 512448f9e8 Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-01-31 17:37:16 -08:00
Matt Guthaus 9fea4a1a2d Do not require hspice during tests. Check if a valid simulator is found, however. 2018-01-31 16:21:43 -08:00
Matt Guthaus 590f6e01d1 Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message. 2018-01-31 15:38:02 -08:00
Matt Guthaus acf3fe8376 Add well around column muxes. 2018-01-31 14:31:50 -08:00
mguthaus 4273a3717d Clean up messages. 2018-01-31 11:54:20 -08:00
mguthaus 4aee700331 Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-01-31 11:48:41 -08:00
Matt Guthaus 1175f515c8 Add descriptive exceptions along with cleanup in unit test checking. 2018-01-31 10:35:51 -08:00
Matt Guthaus 58da8af619 Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. 2018-01-31 10:04:28 -08:00
Matt Guthaus 012c3923be Create empty setup.tcl file as workaround for resetting netgen LVS options until Tim fix's bug. 2018-01-31 08:28:53 -08:00
Matt Guthaus 264d55b16c Remove temp files 2018-01-30 08:05:50 -08:00
Matt Guthaus 8fcb551953 Only perform DRC not LVS on transistors 2018-01-30 08:03:54 -08:00
Matt Guthaus 1d9274621a Only remove files when cleaning temp dir 2018-01-30 07:58:31 -08:00
Matt Guthaus 0b6eddef43 Force write the specific cell during DRC. 2018-01-29 17:00:20 -08:00
Matt Guthaus 56770f558f Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
Matt Guthaus 313e06d2af Fix pwell contact in column mux to have layers for Magic. 2018-01-29 15:53:22 -08:00
Matt Guthaus 6080b59058 Fix nand input ordering to correct netgen LVS error of wordline driver. 2018-01-29 15:36:37 -08:00
Matt Guthaus a56fa0e787 Fix wrong pin order on pnand2 LVS problem. 2018-01-29 15:31:14 -08:00
Matt Guthaus 79715ae1a2 Fix input discrepencies in pre3x8 2018-01-29 15:25:41 -08:00
Matt Guthaus 3c5ecb963d Remove level of indirection to ptx devices to allow LVS symmetries. 2018-01-29 15:25:15 -08:00
Matt Guthaus 586d80623e Remove level of indirection to ptx devices to allow LVS symmetries. 2018-01-29 15:25:00 -08:00
Michael Timothy Grimes fb2572bd71 Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-01-28 21:44:22 -08:00
Matt Guthaus 31c192c2e9 Fix precharge nwell contact spacing DRC violatin. 2018-01-26 13:53:45 -08:00
Matt Guthaus e46a4fb115 Use any spice for the functional tests. 2018-01-26 13:53:11 -08:00
Matt Guthaus 028146f3c2 Add output explaining error for not finding simulator in unit tests. 2018-01-26 13:23:11 -08:00
Matt Guthaus 369aa85cd2 Fail simulation tests if correct spice is not found. Correctly load spice characterizer. 2018-01-26 13:00:25 -08:00
Matt Guthaus 50107636a0 Fail test early if spice simulator is not found. 2018-01-26 12:47:32 -08:00
Matt Guthaus 1dc7752429 Fix 6T and replica cell contact spacing issues with Magic DRC. 
DRC/LVS passing for all parameterized gates.
Magic and GDS match for SCMOS rules again.
 2018-01-26 12:39:00 -08:00
Matt Guthaus ac8eada0d8 Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments. 2018-01-24 13:02:55 -08:00
Matt Guthaus 1b2df3a5a1 Properly ignore ad as, pd, ps property errors 2018-01-22 17:50:53 -08:00
Matt Guthaus 2468f224d9 SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh. 2018-01-22 17:14:39 -08:00
Matt Guthaus fb2ed1d46c Add wells to fix DRC errors in SCMOS library cells. 2018-01-22 16:28:20 -08:00
Matt Guthaus f572b83671 Add Makefile for parallel test execution. 2018-01-22 13:39:07 -08:00
Matt Guthaus 10ced33127 Fixed command line arguments to take priority over config file. Any option can be specified in config file now. 2018-01-21 11:21:09 -08:00
Matt Guthaus 84ec7a5be0 Convert unit tests to use new options as well. 2018-01-19 17:23:38 -08:00
Matt Guthaus 95fab1ca71 Remove personalized temp dir. 2018-01-19 16:39:14 -08:00
Matt Guthaus 490a70dee9 Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-19 16:38:19 -08:00
Matt Guthaus 72b0617e81 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-01-19 16:19:12 -08:00
Matt Guthaus efa465757c Remove dead code ptx_port. 2018-01-19 16:19:05 -08:00
Matt Guthaus fcc533ec11 Initial LVS using netgen. pinv nad pnand2 pass. No property checks in LVS yet. 2018-01-17 16:48:35 -08:00
Matt Guthaus ba489f0291 Only check if using magic with freepdk when LVSDRC is enabled. 2018-01-17 07:38:29 -08:00
Matt Guthaus 7c50708158 Check that we are not using Magic for FreePDK45. 2018-01-12 14:50:35 -08:00
Matt Guthaus 243097cb33 Remove print statement in magic.py 2018-01-12 14:45:11 -08:00
Matt Guthaus 1b30eb4b64 Initial DRC with Magic is done. 2018-01-12 14:39:42 -08:00
Matt Guthaus 7a172873a3 Update unit tests to load verify after config file. Start magic DRC. 2018-01-12 10:24:49 -08:00
Matt Guthaus e0a6b59773 Fix LEF test mismatch in regression. 2018-01-12 08:54:31 -08:00
Matt Guthaus 1701eac1a9 Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells. 2018-01-11 10:24:44 -08:00
Michael Timothy Grimes 64e7ed5b5e Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports 
Adding 04_pbitcell_test.py: The benchtest for pbitcell

Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read
transistors and their corresponding vias. Then several drc corrections need to be made.
 2018-01-09 13:39:42 -08:00
Matt Guthaus f028436156 Add implant/select enclosure rule to ptx. 2018-01-08 12:27:50 -08:00
Matt Guthaus e95988c639 Document tech files. Remove unused/redundant rules. Made rule names consistent/simple. 2018-01-08 11:57:51 -08:00
Matt Guthaus 547746f839 Merge branch 'dev' 2018-01-05 08:34:47 -08:00
Matt Guthaus fd748b4fe4 Move info messages about modes to better locations. 2018-01-05 08:32:23 -08:00
Matt Guthaus 4885616bec Remove metal3 in LEF library cells. 2017-12-19 13:12:39 -08:00
Matt Guthaus 97a2d620fe Fix dev tests. Split pruned test to separate golden result. 2017-12-19 11:42:11 -08:00
Matt Guthaus ee7bf7c5f2 Remove metal3 blanket blockage on library cells. 2017-12-19 09:55:59 -08:00
Matt Guthaus 40465d6518 Merge tolerance change from master. 2017-12-19 09:17:43 -08:00
Matt Guthaus 9059a15ceb Remove tab in lef file. 2017-12-19 09:14:59 -08:00
Matt Guthaus 9a4b2b4341 Revised LEF and Verilog generation. Does not read GDS for speed improvements. 2017-12-19 09:01:24 -08:00
mguthaus 13902538ff Increase lib file tolerance to 25 percent. 2017-12-19 07:41:08 -08:00
mguthaus f98155fc0b Increase lib file tolerance to 25 percent. 2017-12-19 07:39:43 -08:00
Matt Guthaus 317f2d1293 Merge update master and dev. 2017-12-18 08:13:59 -08:00
Matt Guthaus a4a9205a56 Change thresholds to 50 percent. 2017-12-15 08:02:48 -08:00
Matt Guthaus ed4ca62dbf Update thresholds to 15 percent. Fix ngspice data. 2017-12-15 08:01:19 -08:00
Matt Guthaus 7e091fc622 Increase threshold to 30% for SCMOS 2017-12-14 16:52:49 -08:00
Matt Guthaus e9005add14 Fix tests that were failing. 2017-12-14 15:43:05 -08:00
Matt Guthaus 819e249526 Remove nor_2 reference 2017-12-12 19:25:35 -08:00
Matt Guthaus e3a6c1ac6b Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947. 2017-12-12 15:50:45 -08:00
Matt Guthaus abee235963 Rewrite the parameterized transistor and gate classes. 
Changes propagate through all designs.
All modules use instance and layout pins.
 2017-12-12 15:04:01 -08:00
Matt Guthaus 1085497476 Fail when using Magic/netgen for DRC/LVS. Remove arguments in running precharge test. 2017-12-12 13:06:01 -08:00
Matt Guthaus 8df46abb30 Move nmos gate to the top of the ptx. 2017-12-01 08:31:16 -08:00
Matt Guthaus 45ae8c7315 Reduce beta test. Remove other betas. Beta doesn't work well due to simplified rules. 2017-11-30 16:02:32 -08:00
Matt Guthaus 74a22fb515 Reduce beta test. Remove other betas. Beta doesn't work well due to simplified rules. 2017-11-30 16:02:17 -08:00
Matt Guthaus 44faa8d58d Fixed SCMOS bugs. 2017-11-30 15:58:16 -08:00
Matt Guthaus c4ce646b81 Fix min height check for scmos 2017-11-30 13:42:55 -08:00
Matt Guthaus c7ff58cef3 Round finger widths to grid. 2017-11-30 12:15:20 -08:00
Matt Guthaus 107cad15a1 Change layout function names to be consistent. 2017-11-30 12:01:04 -08:00
Matt Guthaus 0214cfb48e Fix single finger ptx bugs. 2017-11-30 11:56:40 -08:00
Matt Guthaus 6207f2157c Fix gnd vdd rail overlap bugs. 2017-11-30 09:18:28 -08:00
Matt Guthaus de5c736cb4 Remove temp directory change. 2017-11-29 16:15:22 -08:00
Matt Guthaus 9abe82b203 Pinv implemented, but not DRCed. More new unit tests added for pinv. 2017-11-29 16:11:15 -08:00
Matt Guthaus 13008e1de4 Split pinv unit tests. 2017-11-29 13:43:50 -08:00
Matt Guthaus 1bcef7e3ee Prune ptx code. Change sizes to be relative to min size. 2017-11-29 12:31:00 -08:00
Matt Guthaus d4f8d63442 Fix bug for even number of fingers. Add even finger tests. 2017-11-29 09:44:40 -08:00
Matt Guthaus 7ff82a2aed Improved ptx code but removed internal active/poly positions. 2017-11-28 18:13:32 -08:00
mguthaus 09ca8ba17d Improve output format. Rename option to be more sensible. 2017-11-22 15:57:29 -08:00
Matt Guthaus cf66c83fe4 Fixed address bug to simulate correct wordline 2017-11-21 13:57:59 -08:00
Matt Guthaus aa4768bf87 Add time info for spice simulation calls. 2017-11-21 13:04:18 -08:00
Matt Guthaus 6873342748 Prepend the config file path so it imports your local copy rather than example_config_freepdk, for example. 2017-11-20 11:57:41 -08:00
Matt Guthaus 76ea89e06f Merge branch 'magic_netgen_support' into dev 2017-11-16 13:57:18 -08:00
Matt Guthaus 88740c107f Improve global and code structure using modules. 
Comment and reorganize globals.py
Tests consistently use globals module for OPTions.
Add characterizer as module support.
Modify unit tests to reload new characterizer for ngspice/hspice.
Enable relative and absolute config file arguments so you can run
openram from anywhere on any config file.
 2017-11-16 13:52:58 -08:00
Matt Guthaus 347f1f97fd Merge branch 'master' into magic_netgen_support 2017-11-15 17:05:38 -08:00
mguthaus 2eb9f5c6bc Move verify into a module. Make characterizer a module. Move exe searching to modules. 2017-11-15 17:02:53 -08:00
Matt Guthaus 658f794b12 Add draft of assura DRC/LVS 2017-11-15 12:07:10 -08:00
Matt Guthaus f6410e0371 Merge branch 'master' into dev 2017-11-15 11:46:11 -08:00
Matt Guthaus 75a3884568 Remove tab 2017-11-15 11:45:55 -08:00
Matt Guthaus f123a3ca40 Merge branch 'master' into dev 2017-11-15 07:43:56 -08:00
Matt Guthaus 102db4fecf Fixed prune unit test by relaxing tolerance. 2017-11-15 07:43:43 -08:00
Matt Guthaus 37edd7cac6 Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py. 2017-11-14 16:24:26 -08:00
Matt Guthaus 4285e576f8 Change error to warning for magic/netgen. 2017-11-14 15:49:47 -08:00
Matt Guthaus 40410cc9f5 Clean up code to work when no drc/lvs/pex is found. 2017-11-14 15:31:58 -08:00
Matt Guthaus 257cd62d25 Remove tools from tech file and have search order preference like spice. 2017-11-14 15:27:03 -08:00
Matt Guthaus 3e0f39cd8e Skeleton code for indirect DRC/LVS/PEX tools. 2017-11-14 14:59:14 -08:00
Matt Guthaus 70ab672c5c Pad strings in GDS to even number of bytes per bug report. 2017-11-14 14:30:00 -08:00
Matt Guthaus 29c5ab48f0 Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
Matt Guthaus 8071dcc0f3 Add customsim (xa) as optional simulator. Fix regex to support scientific notation. Go through list of preferred simulators in order. Always abort if command-line simulator not found. 2017-11-12 10:42:41 -08:00
Jun Chen 054e4d3c28 my change 2017-11-11 16:54:04 +09:00
Matt Guthaus 95f1a24f72 Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
Matt Guthaus 0744cbcc60 Merge branch 'master' into dev 2017-11-09 09:11:26 -08:00
Matt Guthaus 05158f104b Removed unnecessary sram_tb.v file. 2017-10-17 15:51:31 -07:00
mguthaus 5c10aebc0f Fix bug in multifinger ptx. Replace LEF file with new snapped layout. 2017-10-06 16:23:23 -07:00
Matt Guthaus 10a8531813 Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function. 2017-10-06 15:30:15 -07:00
Matt Guthaus a9797d12ab Added pins to the ptx class. Modified pin class to do lazy write of GDS shapes to allow removal of pins. 2017-10-05 17:35:05 -07:00
Matt Guthaus b2043bef11 Fix small delay difference in unit test 21_hspice_delay_test. 2017-10-05 08:13:53 -07:00
Matt Guthaus 69e44c78d8 Upgrade version to 1.01 2017-10-04 20:18:30 -07:00
Matt Guthaus 59a0394c2b Update LEF files with modified blockages. 2017-10-04 20:17:30 -07:00
Matt Guthaus 788f3d9122 4-bank SRAMs are now working. 2017-10-04 18:05:45 -07:00
Matt Guthaus 21c77645d3 Remove LVS correspondence points for multibank in single bank. 2017-09-29 16:44:24 -07:00
Matt Guthaus e06e1691c8 Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
Matt Guthaus d29dd03373 SRAM single bank passing DRC/LVS. 2017-09-13 15:46:41 -07:00
Matt Guthaus 3ea003c367 Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error. 2017-09-11 14:30:52 -07:00
Matt Guthaus d17711c394 Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way. 2017-08-24 16:22:14 -07:00
Matt Guthaus cf940fb15d Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
Matt Guthaus 857b997367 Modify LEF output to have all capital LAYER. Remove extra space before new lines. 2017-08-15 08:21:54 -07:00
Matt Guthaus d77216d6dd Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays. 2017-08-07 10:24:45 -07:00
Matt Guthaus 7ec20a72c8 Fix old unit test golden result 2017-07-06 14:16:02 -07:00
Matt Guthaus 20d8c0bc45 Improved characterizer. 2017-07-06 08:42:25 -07:00
mguthaus e92cb9ecef Removed array_type from ms_flop_array since it is extraneous code. 2017-07-03 12:08:50 -07:00
Matt Guthaus 8a821e13ac Convert print to functional type call like Python 3. Perform error checking that requires Python >2.7 <3.0 for better error checking. 2017-06-12 15:02:48 -07:00
mguthaus 6e90bf0d6d Enable output filename and path to be in config file. Command line will over-ride config file. 2017-06-12 14:37:15 -07:00
mguthaus a840209c08 Fix unit tests to be DRC clean. 2017-06-07 10:29:53 -07:00
Matt Guthaus 93389ac723 Add test to reroute after route fails. Disable GDS route debug info unless verbosity is more than 0. 2017-06-07 10:10:18 -07:00
mguthaus 5960324ca6 Simplify sparse add for grid map. 2017-06-07 09:38:57 -07:00
mguthaus c061b985ba Fix missing map key check in blocked get/set. 2017-06-06 17:12:19 -07:00
Matt Guthaus 8b5e92e582 Merge branch 'master' of github.com:mguthaus/OpenRAM 2017-06-06 11:06:35 -07:00
Matt Guthaus 4e97e385e1 New lib file. Tolerances were off. 2017-06-06 11:06:16 -07:00
Matt Guthaus d67a7149ab Small fixes to last commit. Remove grid pin debug output. Remove extraneous function calls to add grids. 2017-06-05 15:46:50 -07:00
mguthaus 11bb105545 Mark inaccessible off-grid pins as blocked. Improve on-grid pin analysis, but not quite good enough yet. 2017-06-05 14:42:56 -07:00
mguthaus 16063cc9a0 Merge branch 'master' into router 2017-06-05 13:12:51 -07:00
Matt Guthaus 3e2b6e42d4 Merge branch 'router' 2017-06-05 09:08:17 -07:00
Matt Guthaus d20ea65923 Fix lib test to enable spice simulation. Fixed bug with change in default argument. 2017-06-05 09:07:52 -07:00
Matt Guthaus 0acbf43908 Fix lib test to enable spice simulation. Fixed bug with change in default argument. 2017-06-05 09:03:51 -07:00
mguthaus f32912f07c Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity. 2017-06-02 11:11:57 -07:00
Matt Guthaus b18f0e9905 Moved TODO items to GitHub issues. 2017-05-31 15:47:01 -07:00
Matt Guthaus 384e169b5b Modified unit tests: one for analytical model, one for characterization. 2017-05-31 14:59:22 -07:00
Matt Guthaus 367d4168ad Merge branch 'master' into router 2017-05-31 14:04:31 -07:00
Matt Guthaus d31b1862a3 Improved router debugging and return error if unable to route. 2017-05-31 13:59:49 -07:00
Matt Guthaus 8cc63560f8 Merge branch 'master' into router 2017-05-31 12:09:04 -07:00
Matt Guthaus 424c7b7e64 Made back-annotation and analytical modelling boolean options. Default is false. 2017-05-31 08:12:17 -07:00
Matt Guthaus 46c56863ee Bin Wu fixed unit test to pass with analytical delay option 2017-05-31 08:01:42 -07:00
Matt Guthaus 34e180b901 Analytical delay model from Bin Wu. Unit test not passing. 2017-05-30 12:50:07 -07:00
Matt Guthaus 0fe104af66 Output labels in GDS for debug 2017-05-25 14:18:12 -07:00
Matt Guthaus 7e44d8762e New algorithm for finding pins. Includes off-grid pin computation. 2017-05-25 10:37:24 -07:00
Matt Guthaus dd9b9d73b8 Round pins smaller. 2017-05-24 16:09:43 -07:00
Matt Guthaus 4c0fb2d7d1 Add space around route end rectangles. Separate pin and blockage conversions. 2017-05-24 15:36:30 -07:00
Matt Guthaus 24cfed9fa8 Merge branch 'master' into router 2017-05-24 15:18:06 -07:00
Matt Guthaus 2936038c90 Adding new pin shape conversion using design rules 2017-05-24 15:17:49 -07:00
mguthaus 14b040720b Add some router tests for SCMOS. Not all are there. Found bug in off-grid pin access for one test that is still there. 2017-05-24 13:57:27 -07:00
Matt Guthaus c3769bd375 Added new scmos test with a bigger design. Added error checks for not found label and not found pin shapes. 2017-05-24 10:50:45 -07:00
mguthaus 7ca5c0b34f Added zoom to technology file so labels in each tech are readable size. Made default size. 2017-05-23 16:18:11 -07:00
Matt Guthaus 2e86da4cd1 Add router to the python path 2017-05-23 08:31:23 -07:00
mguthaus 68ce3843fe Debugged and tested route by pin location,layer 2017-05-17 15:58:29 -07:00
Matt Guthaus a1496e70a8 Updated gdsMill with new getter routines for router to get by location. Cleaned up vlsiLayout. 2017-05-17 14:27:14 -07:00
Matt Guthaus b16dd80088 Add checks for valid OPENRAM_HOME and OPENRAM_TECH directories and subdirs 2017-05-12 14:56:31 -07:00
Matt Guthaus cffcd46f6d Removed the name from ptx class. Ptx name is uniquely constructed based on the ptx parameters of type, width, and mult. This allows reuse of ptx among multiple modules. 2017-04-26 14:33:03 -07:00
Matt Guthaus 1e8743f5a5 Removed unique id for contacts. Contact/via name, however, must distinguish types of contacts based on layers used. 2017-04-26 10:24:51 -07:00
mguthaus d85f78a54c Fixed format errors 2017-04-24 13:50:19 -07:00
mguthaus 9b86083524 Fixed rotated via bug. May still have a via-to-via spacing problem. 2017-04-24 13:47:56 -07:00
mguthaus 8a185ffc1a Merge branch 'master' into router 2017-04-24 12:17:21 -07:00
Matt Guthaus 21f5444f81 Forgot one more view to comment out 2017-04-24 12:14:19 -07:00
Matt Guthaus e960cbe9d6 Clean up output so that it does not print routing grid debug. 2017-04-24 12:13:01 -07:00
mguthaus bd7958be28 Fixed format test. It was not performing checks due to moving of OPENRAM_HOME. Fixed some tabs and print statements. 2017-04-24 11:55:11 -07:00
Matt Guthaus 9478d6f94d Change width of default text routing grid to display. 2017-04-24 11:33:14 -07:00
Matt Guthaus 388794b1e0 Fix multiple net routing cost reset bug. 2017-04-24 11:28:36 -07:00
Matt Guthaus 96f1eb413e Fixed costs and view grid function so that we have better routes and less expansion. 2017-04-24 10:27:04 -07:00
mguthaus c005960072 Changed DRC and LVS results output database to end in .db instead of .results. Calibre uses file extensions to determine file type. 2017-04-21 14:07:16 -07:00
Matt Guthaus 55ed6212a1 Created route and add_route for layer assigned wires. It will replace add_wire/wire eventually. 2017-04-19 12:41:13 -07:00
mguthaus f51e82e75a Commented unit tests. Added negative coordinate test on test 03. 2017-04-16 08:04:06 -07:00
mguthaus 7cac1a0357 Rename test classes. 2017-04-15 07:49:05 -07:00
mguthaus 2350be8e39 Fixed router test 03. Cleaned up code. 2017-04-14 13:56:09 -07:00
mguthaus b61df7614d Added gds for test 01 2017-04-14 13:19:44 -07:00
mguthaus 76f338e982 Fixed offgrid pins. Added vias to src/dst pins. Added preferred direction routing costs. 2017-04-14 13:18:35 -07:00
Matthew Guthaus 0766db9e11 Rename unit test files according to test. Modify off-grid pins and blockages. Reorganize router code a bit. 2017-04-12 10:59:04 -07:00
Matt Guthaus 1f5841b933 Merge branch 'temp_merge' into router 2017-01-11 12:24:44 -08:00
Matt Guthaus e5c58bf3d5 Merge remote-tracking branch 'origin/master' into HEAD 2017-01-11 12:22:25 -08:00
Matt Guthaus 747af592bd Merge remote-tracking branch 'origin/router' into router 2017-01-11 12:18:42 -08:00
Matt Guthaus e46ff50269 Modified default tech back to freepdk. Config file overrides command line. 2017-01-11 11:47:58 -08:00
Matt Guthaus d46e416c29 Change snap to grid function name 2017-01-11 09:23:17 -08:00
Matt Guthaus a31f87bc72 Merge master branch into router 2017-01-09 14:04:37 -08:00
Matt Guthaus 2d0533a7d5 Merge remote-tracking branch 'bin/merge_hierarchical_decoder' 2016-11-23 17:20:45 -08:00
Matt Guthaus 9356d1771f Merge remote-tracking branch 'bin/move_snap_to_vector_fix1' 2016-11-23 17:19:55 -08:00
Matt Guthaus 841532a52f Change characterizer to be one data structure. Add approximate diff for lib file. 2016-11-23 17:18:48 -08:00
Bin wu a9b7baa206 merge hierarchical_decoder 2x4 and 3x8 routing functions together 2016-11-22 12:23:55 -08:00
Bin wu 8c4b97753a not applying snap_to_grid to all vectors 2016-11-20 11:06:53 -08:00
Bin wu 905f5cf28e Merge branch 'master' of https://github.com/mguthaus/OpenRAM into move_snap_to_vector 2016-11-20 10:48:45 -08:00
Samira Ataei 233acc3fcc Added seprate return for power values of lib. 2016-11-20 11:16:19 -06:00
Matt Guthaus 7969ac2846 Non functioning commit 2016-11-20 08:41:49 -08:00
Samira Ataei d195df682d Added Power results to lib. 
Fixed min_period and min_pulse_width values.
  Updated lib golden files.
 2016-11-19 20:19:16 -06:00
Matt Guthaus 5149ec34f0 Update unit tests with block 2016-11-18 16:17:49 -08:00
Matt Guthaus 2a17856c69 Add src/dest pin block 2016-11-18 16:16:19 -08:00
Matt Guthaus 62237830cd Fix rounding, offsets, and increase halo 2016-11-18 15:49:07 -08:00
Matt Guthaus 7e03eaf41e Shrink blockages to avoid wide metal rules 2016-11-18 15:30:35 -08:00
Matt Guthaus da1df1f580 Fix max track width computation 2016-11-18 15:18:36 -08:00
Matt Guthaus 51d7a673bd Improve debug messages. Remove add_inst for via in wire. 2016-11-18 14:10:30 -08:00
Matt Guthaus 70365a8116 Add double grid snap for centerline wires 2016-11-18 12:57:07 -08:00
Matt Guthaus c802d53a60 Remove view from tests 2016-11-18 11:35:41 -08:00
Matt Guthaus c4d2cb78ef Relative gds file names in tests. 2016-11-18 11:33:03 -08:00
Matt Guthaus 4e505b80dc Convert gds to on grid. Remove view from tests. 2016-11-18 11:30:14 -08:00
Matt Guthaus 396a41733c Added regress script for router 2016-11-18 11:21:39 -08:00
Matt Guthaus 3466162152 Merge branch 'master' into router 2016-11-18 09:20:05 -08:00
Matt Guthaus 710b6d64d7 Fix bug to only see if this path visited a point. 2016-11-18 09:17:59 -08:00
Matt Guthaus ed5700d698 Fix spelling errors. Allow multiple rectangle pin shapes in router. 2016-11-18 08:55:34 -08:00
Matt Guthaus 1c9b5c7372 Document vlsiLayout functions in comments 2016-11-18 08:01:19 -08:00
Matt Guthaus eceb27cad7 Add regress.sh script for convenience 2016-11-18 08:00:34 -08:00
Bin wu a22ba2087b fix the conflicts for merge 2016-11-17 17:19:48 -08:00
Bin wu 0658cc20e6 move snapt_to_grid to a function in vector class 2016-11-17 17:12:48 -08:00
Matt Guthaus c143f62b25 Forgot to add testutils.py 2016-11-17 16:59:22 -08:00
Matt Guthaus e215885b2f Update unit tests. 2016-11-17 16:46:41 -08:00
Matt Guthaus b5b1f1753e Rename tests. Make 4 pin test. 2016-11-17 16:33:38 -08:00
Matt Guthaus 5cef8606b4 Merge branch 'master' into router 2016-11-17 16:11:21 -08:00
Matt Guthaus 19e7100f80 Fix error in metal stack 2016-11-17 16:04:01 -08:00
Matt Guthaus 81ab1f1f82 Change layer order for add_wire 2016-11-17 14:05:50 -08:00
Matt Guthaus 3c7fd924f7 Revert change to horizontal/vertical 2016-11-17 13:51:09 -08:00
Matt Guthaus 717718ed5a Adding checking of rounding and contract path to simplify route wire. 2016-11-17 13:48:27 -08:00
Matt Guthaus 0a9b326f6a Contract path to simplified route 2016-11-17 13:26:03 -08:00
Matt Guthaus aa950c3b21 Fix unit during gds read. Fix blockage and pin rounding bugs. 2016-11-17 11:24:17 -08:00
Matt Guthaus 614ff23e3a Routing multilayer, around blockages. 2016-11-16 16:52:33 -08:00
Matt Guthaus 784bad2e99 Routing multilayer, around blockages. 2016-11-16 16:47:31 -08:00
Matt Guthaus b947989970 Add router data structure, blockage parser, pin parser, initial unit tests 2016-11-16 15:02:07 -08:00
Matt Guthaus d0782df9fe Merge branch 'master' into router 2016-11-15 11:22:30 -08:00
Matt Guthaus 836c7ece73 Merge remote-tracking branch 'origin/master' into router 2016-11-15 10:21:02 -08:00
Matt Guthaus a846132ef8 Merge remote-tracking branch 'bin/clean_unchanged_offset_to_vector' 2016-11-15 10:19:07 -08:00
Matt Guthaus 51e4104624 Modify banner to output temp path 2016-11-15 10:14:04 -08:00
Matt Guthaus a2b7636e58 Modify banner to output temp path 2016-11-15 10:13:57 -08:00
Matt Guthaus 3074349c38 Fix ngspice scnmos results 2016-11-15 10:13:45 -08:00
Matt Guthaus 00b3772b4e Add temp path to test header 2016-11-15 09:55:18 -08:00
Matt Guthaus c33e283283 Fix ngspice results 2016-11-15 09:41:30 -08:00
Matt Guthaus eb57c6e7fd Fix arg parsing order in openram.py 2016-11-15 09:36:15 -08:00
Matt Guthaus d1f6f205c0 No output during level 0 debug. 2016-11-15 09:04:32 -08:00
Matt Guthaus cbc0f7c5d2 run_pex argument is now use_pex. Each unit test must RESET its options before assertions for consistent start state. 2016-11-15 09:03:16 -08:00
Matt Guthaus e95e9e8229 Change some debug levels. Fix ngspice test values. ix cwd warning in some tests. 2016-11-15 08:57:06 -08:00
Matt Guthaus 0e2409d836 Fix file compare scope error 2016-11-12 11:16:08 -08:00
Matt Guthaus 392dbc7c56 Moved output of tests 30 to openram_temp 2016-11-12 11:15:55 -08:00
Matt Guthaus 475a5223a7 Moved output of tests 23-25 to openram_temp 2016-11-12 11:15:34 -08:00
Matt Guthaus 7fcce2633f Fix delays in ngspice as they are diff than hspice 2016-11-12 09:28:22 -08:00
Matt Guthaus 2a6b709a41 Merge branch 'master' into router 2016-11-12 08:58:24 -08:00
Matt Guthaus cdb101b377 Sketch new router procedures 2016-11-12 08:57:26 -08:00
Matt Guthaus b82aaa4201 Merge use-temp-dir-pid 2016-11-12 08:55:42 -08:00
Matt Guthaus 096505af14 Merge branch 'use-temp-dir-pid' 2016-11-12 08:49:51 -08:00
Matt Guthaus d85efb772f Temp files were deleted. 2016-11-12 08:49:39 -08:00
Matt Guthaus 7e16bf37df Add code for isdiff to output diff in tests when files mismatch. 2016-11-12 07:56:50 -08:00
Bin wu 072a65a511 add rotate_scale function in vector and use it everywhere 2016-11-11 14:33:19 -08:00
Matt Guthaus 7d0d590879 Don't converge only after a successful measurement. 2016-11-11 14:25:46 -08:00
Matt Guthaus 9ea1a06244 Remove openram_temp at end of openram and unit tests. 2016-11-11 14:05:14 -08:00
Matt Guthaus 5e33781268 Remove control structure from ngspice. Add probe for ngspice too since it doesn't hurt. Unskip delay test. 2016-11-11 13:22:01 -08:00
Matt Guthaus 5211be5ffc No control statements in ngspice 26 2016-11-11 13:10:54 -08:00
Matt Guthaus 33b46b450d No control statements in ngspice 26 2016-11-11 13:09:46 -08:00
Matt Guthaus b9ad65c1de TODO for make characterizer a module 2016-11-11 13:09:26 -08:00
Matt Guthaus 16ea09293c Skip ngspice delay test, too slow 2016-11-11 12:14:13 -08:00
Matt Guthaus 3f879c69c8 Add TODO to convert lib to negative edge for data 2016-11-11 10:04:27 -08:00
Matt Guthaus 07efb52ca9 Lower debug level of relative compare since it's only in unit tests 2016-11-11 10:04:09 -08:00
Matt Guthaus 1356e5142d Add print of values if tests fail. Modify some ngspice tests to pass withcorrect results. 2016-11-11 09:41:43 -08:00
Bin wu 7bae37c026 apply vector to hierchay_layout and geometry and contact 2016-11-10 17:28:06 -08:00
Matt Guthaus c318a7d1bb Check if spice preferred version was found before fallback 2016-11-10 11:44:48 -08:00
Matt Guthaus f3f2171f89 Add both ngspice and hspice timing tests. Add hidden option to force to a version. Otherwise, default to either version if found. 2016-11-10 11:33:10 -08:00
Matt Guthaus 992d091a8b Change step resolution in setup_hold to 5p to avoid convergence problems with ngspice. 2016-11-10 11:07:52 -08:00
Matt Guthaus 868f97caaa Add optimize inverter TODO 2016-11-10 11:07:14 -08:00
Matt Guthaus 46fceba692 More debug messages 2016-11-10 08:55:11 -08:00
Matt Guthaus e017f3f4ca Add better info messages. Convert subprocess to a shell command. 2016-11-10 08:36:28 -08:00
Matt Guthaus 7b90b9a0e6 Try alternative spice if not found. 2016-11-10 08:18:52 -08:00
Matt Guthaus d7afb27322 Break subprocess call into arg list. 2016-11-10 07:27:38 -08:00
Matt Guthaus 342de4e384 Merge branch 'master' of github.com:mguthaus/OpenRAM 2016-11-09 12:21:07 -08:00
Matt Guthaus e1c3d77a5d Removed import cell since cell is removed from simplified txt file 2016-11-09 12:20:52 -08:00
Matt Guthaus 7a23550ae0 Improve error messages on misconfiguration of environment variables. 2016-11-09 12:00:16 -08:00
Matt Guthaus 1fdb0ba5fc Update TODO list 2016-11-09 11:38:36 -08:00
Matt Guthaus f48272bde6 RELEASE 1.0 2016-11-08 09:57:35 -08:00