Version bump

First half of #6301

.bake.toml

@@ -0,0 +1,30 @@
+# mbake configuration file
+
+[formatter]
+# Indentation settings
+use_tabs = true
+tab_width = 2
+
+# Spacing settings
+space_around_assignment = true
+space_before_colon = false
+space_after_colon = true
+
+# Line continuation settings
+normalize_line_continuations = true
+max_line_length = 100
+
+# PHONY settings
+group_phony_declarations = false
+phony_at_top = false
+auto_insert_phony_declarations = false
+
+# General settings
+remove_trailing_whitespace = true
+ensure_final_newline = true
+normalize_empty_lines = true
+max_consecutive_empty_lines = 2
+
+# Global settings
+debug = false
+verbose = false

.clang-format

@@ -63,6 +63,8 @@ ForEachMacros:
 SortIncludes:    true
 IncludeBlocks:   Regroup
 IncludeCategories:
+  - Regex:           '"V3Pch.*\.h"'
+    Priority:        -2 # Precompiled headers
   - Regex:           '"(config_build|verilated_config|verilatedos)\.h"'
     Priority:        -1 # Sepecials before main header
   - Regex:           '(<|")verilated.*'
@@ -112,6 +114,9 @@ SpacesBeforeTrailingComments: 2
 SpacesInAngles:  false
 SpacesInContainerLiterals: true
 SpacesInCStyleCastParentheses: false
+SpacesInLineCommentPrefix:
+  Minimum: 0
+  Maximum: -1
 SpacesInParentheses: false
 SpacesInSquareBrackets: false
 Standard:        Cpp11

.clang-tidy

@@ -1,4 +1,4 @@
-Checks:          '*,-hicpp*,-android-cloexec-fopen,-cert-dcl50-cpp,-cert-env33-c,-cert-err34-c,-cert-err58-cpp,-clang-analyzer-core.UndefinedBinaryOperatorResult,-clang-analyzer-security*,-cppcoreguidelines-avoid-magic-numbers,-cppcoreguidelines-no-malloc,-cppcoreguidelines-owning-memory,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-constant-array-index,-cppcoreguidelines-pro-bounds-pointer-arithmetic,-cppcoreguidelines-pro-type-const-cast,-cppcoreguidelines-pro-type-reinterpret-cast,-cppcoreguidelines-pro-type-static-cast-downcast,-cppcoreguidelines-pro-type-union-access,-cppcoreguidelines-pro-type-vararg,-cppcoreguidelines-special-member-functions,-fuchsia-*,-google-default-arguments,-google-readability-todo,-google-runtime-references,-llvm-header-guard,-llvm-include-order,-misc-string-integer-assignment,-misc-string-literal-with-embedded-nul,-modernize-use-auto,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-container-size-empty,-readability-delete-null-pointer,-readability-else-after-return,-readability-implicit-bool-conversion,-readability-named-parameter,-readability-static-accessed-through-instance'
+Checks:          '*,-hicpp*,-android-cloexec-fopen,-cert-dcl50-cpp,-cert-env33-c,-cert-err34-c,-cert-err58-cpp,-clang-analyzer-core.UndefinedBinaryOperatorResult,-clang-analyzer-security*,-cppcoreguidelines-avoid-magic-numbers,-cppcoreguidelines-no-malloc,-cppcoreguidelines-owning-memory,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-constant-array-index,-cppcoreguidelines-pro-bounds-pointer-arithmetic,-cppcoreguidelines-pro-type-const-cast,-cppcoreguidelines-pro-type-reinterpret-cast,-cppcoreguidelines-pro-type-static-cast-downcast,-cppcoreguidelines-pro-type-union-access,-cppcoreguidelines-pro-type-vararg,-cppcoreguidelines-special-member-functions,-fuchsia-*,-google-default-arguments,-google-readability-todo,-google-runtime-references,-llvm-header-guard,-llvm-include-order,-misc-string-integer-assignment,-misc-string-literal-with-embedded-nul,-modernize-use-auto,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-container-size-empty,-readability-delete-null-pointer,-readability-else-after-return,-readability-implicit-bool-conversion,-readability-named-parameter,-readability-static-accessed-through-instance,-llvmlibc-*,-altera-*'
 WarningsAsErrors: ''
 HeaderFilterRegex: ''
 FormatStyle:     none

.codacy.yml

@@ -1,6 +1,6 @@
 ---
 exclude_paths:
-  - '.github/**'
+  - ".github/**"
-  - 'ci/build_verilator.sh'
+  - "ci/build_verilator.sh"
-  - 'include/vltstd/**'
+  - "include/vltstd/**"
-  - 'nodist/fastcov.py'
+  - "nodist/fastcov.py"

.devcontainer/devcontainer.json

@@ -0,0 +1,8 @@
+{
+        "name": "Verilator Build Environment",
+
+        "build": {
+        "dockerfile": "../ci/docker/buildenv/Dockerfile"
+    }
+
+}

.github/ISSUE_TEMPLATE/bug_report.md

@@ -9,10 +9,14 @@ assignees: ''
 
 Thanks for taking the time to report this.
 
-Can you attach an example that shows the issue?  (Must be openly licensed, ideally in test_regress format.)
+Can you attach an example that shows the issue?  (Must be openly licensed, completely self-contained and self-checking so can directly run what you provide. Ideally use test_regress format, see https://veripool.org/guide/latest/contributing.html?highlight=test_regress#reporting-bugs
+
+What 'verilator' command line do we use to run your example?
 
 What 'verilator --version' are you using?  Did you try it with the git master version?
 
 What OS and distribution are you using?
 
 May we assist you in trying to fix this in Verilator yourself?
+
+(Please avoid attaching screenshots that show text - you can convert images to text using e.g. https://ocr.space)

.github/ISSUE_TEMPLATE/feature.md

@@ -11,6 +11,8 @@ Thanks for taking the time to report this.
 
 What would you like added/supported?
 
-Can you attach an example that runs on other simulators?  (Must be openly licensed, ideally in test_regress format.)
+What 'verilator --version' are you using?  Did you try it with the git master version?
+
+Can you attach an example that runs on other simulators?  (Must be openly licensed, completely self-contained and self-checking so can directly run what you provide. Ideally use test_regress format, see https://veripool.org/guide/latest/contributing.html?highlight=test_regress#reporting-bugs
 
 May we assist you in trying to fix this in Verilator yourself?

.github/ISSUE_TEMPLATE/questions.md

@@ -8,3 +8,5 @@ assignees: ''
 ---
 
 How may we help - what is your question?
+
+(If reporting a bug or requesting a feature please use one of the other issue templates.)

.github/workflows/build.yml

@@ -1,3 +1,4 @@
+---
 # DESCRIPTION: Github actions config
 # This name is key to badges in README.rst, so we use the name build
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
@@ -9,156 +10,187 @@ on:
   pull_request:
   workflow_dispatch:
   schedule:
-  - cron: '0 0 * * 0' # weekly
+    - cron: '0 0 * * 0'  # weekly
 
-env:
+permissions:
-  CI_OS_NAME: linux
+  contents: read
-  CI_COMMIT: ${{ github.sha }}
-  CCACHE_COMPRESS: 1
-  CCACHE_DIR: ${{ github.workspace }}/.ccache
-  CCACHE_LIMIT_MULTIPLE: 0.95
 
 defaults:
   run:
     shell: bash
     working-directory: repo
 
+concurrency:
+  group: ${{ github.workflow }}-${{ github.actor }}-${{ github.event_name == 'pull_request' && github.ref || github.run_id }}
+  cancel-in-progress: true
+
 jobs:
 
-  build:
+  build-2404-gcc:
+    name: Build
+    uses: ./.github/workflows/reusable-build.yml
+    with:
+      os: ${{ matrix.os }}
+      cc: ${{ matrix.cc }}
     strategy:
       fail-fast: false
       matrix:
-        os: [ubuntu-22.04, ubuntu-20.04]
-        compiler:
-          - { cc: clang, cxx: clang++ }
-          - { cc: gcc,   cxx: g++     }
-        m32: [0, 1]
-        exclude:
-          # Build pull requests only with ubuntu-22.04 and without m32
-          # - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-18.04' || 'do-not-exclude' }}
-          # - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-20.04' || 'do-not-exclude' }}
-          # - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
-          # Build -m32 only on ubuntu-22.04 clang++
-          - {os: ubuntu-18.04, m32: 1}
-          - {os: ubuntu-20.04, m32: 1}
-          - compiler: { cc: gcc, cxx: g++ }
-            m32: 1
         include:
-          # Build GCC 10 on ubuntu-20.04
+          - {os: ubuntu-24.04, cc: gcc}
-          - os: ubuntu-20.04
+
-            compiler: { cc: gcc-10, cxx: g++-10 }
+  build-2404-clang:
-            m32: 0
+    name: Build
-    runs-on: ${{ matrix.os }}
+    uses: ./.github/workflows/reusable-build.yml
-    name: Build | ${{ matrix.os }} | ${{ matrix.compiler.cc }} ${{ matrix.m32 && '| -m32' || '' }}
+    with:
+      os: ${{ matrix.os }}
+      cc: ${{ matrix.cc }}
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          - {os: ubuntu-24.04, cc: clang}
+
+  build-2204-gcc:
+    name: Build
+    uses: ./.github/workflows/reusable-build.yml
+    with:
+      os: ${{ matrix.os }}
+      cc: ${{ matrix.cc }}
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          - {os: ubuntu-22.04, cc: gcc}
+
+  build-2204-clang:
+    name: Build
+    uses: ./.github/workflows/reusable-build.yml
+    with:
+      os: ${{ matrix.os }}
+      cc: ${{ matrix.cc }}
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          - {os: ubuntu-22.04, cc: clang}
+
+  test-2404-gcc:
+    name: Test | ${{ matrix.os }} | ${{ matrix.cc }}
+    needs: build-2404-gcc
+    uses: ./.github/workflows/reusable-test.yml
+    with:
+      os: ${{ matrix.os }}
+      cc: ${{ matrix.cc }}
+      reloc: ${{ matrix.reloc }}
+      suite: ${{ matrix.suite }}
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          # Ubuntu 24.04 gcc
+          - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt-0}
+          - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt-1}
+          - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt-2}
+          - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt-3}
+          - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt-0}
+          - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt-1}
+          - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt-2}
+
+  test-2404-clang:
+    name: Test | ${{ matrix.os }} | ${{ matrix.cc }}
+    needs: build-2404-clang
+    uses: ./.github/workflows/reusable-test.yml
+    with:
+      os: ${{ matrix.os }}
+      cc: ${{ matrix.cc }}
+      reloc: ${{ matrix.reloc }}
+      suite: ${{ matrix.suite }}
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          # Ubuntu 24.04 clang
+          - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt-0}
+          - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt-1}
+          - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt-2}
+          - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt-3}
+          - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt-0}
+          - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt-1}
+          - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt-2}
+
+  test-2204-gcc:
+    name: Test | ${{ matrix.os }} | ${{ matrix.cc }}
+    needs: build-2204-gcc
+    uses: ./.github/workflows/reusable-test.yml
+    with:
+      os: ${{ matrix.os }}
+      cc: ${{ matrix.cc }}
+      reloc: ${{ matrix.reloc }}
+      suite: ${{ matrix.suite }}
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          # Ubuntu 22.04 gcc
+          - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt-0}
+          - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt-1}
+          - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt-2}
+          - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt-3}
+          - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt-0}
+          - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt-1}
+          - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt-2}
+
+  test-2204-clang:
+    name: Test | ${{ matrix.os }} | ${{ matrix.cc }}
+    needs: build-2204-clang
+    uses: ./.github/workflows/reusable-test.yml
+    with:
+      os: ${{ matrix.os }}
+      cc: ${{ matrix.cc }}
+      reloc: ${{ matrix.reloc }}
+      suite: ${{ matrix.suite }}
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          # Ubuntu 22.04 clang, also test relocation
+          - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: dist-vlt-0}
+          - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: dist-vlt-1}
+          - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: dist-vlt-2}
+          - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: dist-vlt-3}
+          - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: vltmt-0}
+          - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: vltmt-1}
+          - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: vltmt-2}
+
+  lint-py:
+    runs-on: ubuntu-22.04
+    name: Lint Python
     env:
+      CI_OS_NAME: linux
+      CI_COMMIT: ${{ github.sha }}
       CI_BUILD_STAGE_NAME: build
-      CI_RUNS_ON: ${{ matrix.os }}
+      CI_RUNS_ON: ubuntu-22.04
-      CI_M32: ${{ matrix.m32 }}
+      CCACHE_COMPRESS: 1
-      CC: ${{ matrix.compiler.cc }}
+      CCACHE_DIR: ${{ github.workspace }}/.ccache
-      CXX: ${{ matrix.compiler.cxx }}
+      CCACHE_LIMIT_MULTIPLE: 0.95
-      CACHE_BASE_KEY: build-${{ matrix.os }}-${{ matrix.compiler.cc }}-m32=${{ matrix.m32 }}
-      CCACHE_MAXSIZE: 250M # Per build matrix entry (2000M in total)
-      VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ matrix.os }}-${{ matrix.compiler.cc }}${{ matrix.m32 && '-m32' || '' }}.tar.gz
-    steps:
-
-    - name: Checkout
-      uses: actions/checkout@v3
-      with:
-        path: repo
-
-    - name: Cache $CCACHE_DIR
-      uses: actions/cache@v3
-      env:
-        CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
-      with:
-        path: ${{ env.CCACHE_DIR }}
-        key: ${{ env.CACHE_KEY }}-${{ github.sha }}
-        restore-keys: |
-          ${{ env.CACHE_KEY }}-
-
-    - name: Install packages for build
-      run: ./ci/ci-install.bash
-
-    - name: Build
-      run: ./ci/ci-script.bash
-
-    - name: Tar up repository
-      working-directory: ${{ github.workspace }}
-      run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo
-
-    - name: Upload tar archive
-      uses: actions/upload-artifact@v3
-      with:
-        path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }}
-        name: ${{ env.VERILATOR_ARCHIVE }}
-
-
-  test:
-    needs: build
     strategy:
       fail-fast: false
-      matrix:
-        os: [ubuntu-22.04, ubuntu-20.04]
-        compiler:
-          - { cc: clang, cxx: clang++ }
-          - { cc: gcc,   cxx: g++     }
-        m32: [0, 1]
-        suite: [dist-vlt-0, dist-vlt-1, dist-vlt-2, vltmt-0, vltmt-1]
-        exclude:
-          # Build pull requests only with ubuntu-22.04 and without m32
-          # - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-18.04' || 'do-not-exclude' }}
-          # - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-20.04' || 'do-not-exclude' }}
-          # - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
-          # Build -m32 only on ubuntu-22.04
-          - {os: ubuntu-18.04, m32: 1}
-          - {os: ubuntu-20.04, m32: 1}
-          - compiler: { cc: gcc, cxx: g++ }
-            m32: 1
-        include:
-          # Test with GCC 10 on ubuntu-20.04 without m32
-          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-0}
-          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-1}
-          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-2}
-          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: vltmt-0}
-          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: vltmt-1}
-    runs-on: ${{ matrix.os }}
-    name: Test | ${{ matrix.os }} | ${{ matrix.compiler.cc }} | ${{ matrix.suite }} ${{ matrix.m32 && '| -m32' || '' }}
-    env:
-      CI_BUILD_STAGE_NAME: test
-      CI_RUNS_ON: ${{ matrix.os }}
-      CI_M32: ${{ matrix.m32 }}
-      CC: ${{ matrix.compiler.cc }}
-      CXX: ${{ matrix.compiler.cxx }}
-      CACHE_BASE_KEY: test-${{ matrix.os }}-${{ matrix.compiler.cc }}-m32=${{ matrix.m32 }}-${{ matrix.suite }}
-      CCACHE_MAXSIZE: 64M # Per build matrix entry (2160M in total)
-      VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ matrix.os }}-${{ matrix.compiler.cc }}${{ matrix.m32 && '-m32' || '' }}.tar.gz
     steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+        with:
+          path: repo
 
-    - name: Download tar archive
+      - name: Install packages for build
-      uses: actions/download-artifact@v3
+        run: ./ci/ci-install.bash
-      with:
-        name: ${{ env.VERILATOR_ARCHIVE }}
-        path: ${{ github.workspace }}
 
-    - name: Unpack tar archive
+    # We use specific version numbers, otherwise a Python package
-      working-directory: ${{ github.workspace }}
+    # update may add a warning and break our build
-      run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }}
+      - name: Install packages for lint
+        run: sudo pip3 install pylint==3.0.2 ruff==0.1.3 clang sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe ruff
 
-    - name: Cache $CCACHE_DIR
+      - name: Configure
-      uses: actions/cache@v3
+        run: autoconf && ./configure --enable-longtests --enable-ccwarn
-      env:
-        CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
-      with:
-        path: ${{ env.CCACHE_DIR }}
-        key: ${{ env.CACHE_KEY }}-${{ github.sha }}
-        restore-keys: |
-          ${{ env.CACHE_KEY }}-
 
-    - name: Install test dependencies
+      - name: Lint
-      run: ./ci/ci-install.bash
+        run: make -k lint-py
-
-    - name: Test
-      env:
-        TESTS: ${{ matrix.suite }}
-      run: ./ci/ci-script.bash

.github/workflows/contributor.yml

@@ -1,17 +1,18 @@
+---
 # DESCRIPTION: Github actions config
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
+#
 name: Contributor Agreement
-
 on:
   push:
   pull_request:
   workflow_dispatch:
-
+permissions:
+  contents: read
 jobs:
   Test:
     name: "'docs/CONTRIBUTORS' was signed"
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     steps:
-    - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
-    - run: test_regress/t/t_dist_contributors.pl
+      - run: test_regress/t/t_dist_contributors.py

.github/workflows/coverage.yml

@@ -1,3 +1,4 @@
+---
 # DESCRIPTION: Github actions config
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
@@ -6,12 +7,14 @@ name: coverage
 on:
   workflow_dispatch:
   schedule:
-  - cron: '0 0 * * 0' # weekly
+    - cron: '0 0 * * 0'  # weekly
+
+permissions:
+  contents: read
 
 env:
   CI_OS_NAME: linux
   CI_COMMIT: ${{ github.sha }}
-  CI_M32: 0
   COVERAGE: 1
   VERILATOR_ARCHIVE: verilator-coverage-${{ github.sha }}.tar.gz
 
@@ -22,78 +25,73 @@ defaults:
 
 jobs:
 
-
   Build:
-    runs-on: ubuntu-22.04
+    # Only run scheduled jobs if explicitly enabled for that repo (e.g.: not on forks)
+    if: ${{ github.event_name != 'schedule' || vars.ENABLE_SCHEDULED_JOBS == 'true' }}
+    runs-on: ubuntu-24.04
     env:
       CI_BUILD_STAGE_NAME: build
-      CI_RUNS_ON: ubuntu-22.04
+      CI_RUNS_ON: ubuntu-24.04
     steps:
 
-    - name: Checkout
+      - name: Checkout
-      uses: actions/checkout@v3
+        uses: actions/checkout@v4
-      with:
+        with:
-        path: repo
+          path: repo
 
-    - name: Install packages for build
+      - name: Install packages for build
-      run: ./ci/ci-install.bash
+        run: ./ci/ci-install.bash
 
-    - name: Build
+      - name: Build
-      run: ./ci/ci-script.bash
+        run: ./ci/ci-script.bash
 
-    - name: Tar up repository
+      - name: Tar up repository
-      working-directory: ${{ github.workspace }}
+        working-directory: ${{ github.workspace }}
-      run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo
+        run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo
-
-    - name: Upload tar archive
-      uses: actions/upload-artifact@v3
-      with:
-        path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }}
-        name: ${{ env.VERILATOR_ARCHIVE }}
 
+      - name: Upload tar archive
+        uses: actions/upload-artifact@v4
+        with:
+          path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }}
+          name: ${{ env.VERILATOR_ARCHIVE }}
 
   Test:
     needs: Build
     strategy:
       fail-fast: false
       matrix:
-        test:
+        test: [vlt-, vltmt-]
-        - vlt-
+        num: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]
-        - vltmt-
-        num:
-        - 0
-        - 1
-        - 2
-        - 3
-        - 4
-        - 5
-        - 6
-        - 7
-        - 8
-        - 9
         include:
-        - { test: dist, num: '' }
+          - {test: dist, num: ''}
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     name: test-${{ matrix.test }}${{ matrix.num }}
     env:
       CI_BUILD_STAGE_NAME: test
-      CI_RUNS_ON: ubuntu-22.04
+      CI_RUNS_ON: ubuntu-24.04
     steps:
 
-    - name: Download tar archive
+      - name: Download tar archive
-      uses: actions/download-artifact@v3
+        uses: actions/download-artifact@v4
-      with:
+        with:
-        name: ${{ env.VERILATOR_ARCHIVE }}
+          name: ${{ env.VERILATOR_ARCHIVE }}
-        path: ${{ github.workspace }}
+          path: ${{ github.workspace }}
 
-    - name: Unpack tar archive
+      - name: Unpack tar archive
-      working-directory: ${{ github.workspace }}
+        working-directory: ${{ github.workspace }}
-      run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }}
+        run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }}
 
-    - name: Install test dependencies
+      - name: Install test dependencies
-      run: ./ci/ci-install.bash
+        run: ./ci/ci-install.bash
 
-    - name: Test
+      - name: Test
-      env:
+        env:
-        TESTS: coverage-${{ matrix.test }}${{ matrix.num }}
+          TESTS: coverage-${{ matrix.test }}${{ matrix.num }}
-      run: ./ci/ci-script.bash
+        run: ./ci/ci-script.bash
+
+      - name: Upload coverage data to Codecov
+        env:
+          CODECOV_TOKEN: ${{ secrets.CODECOV_TOKEN }}
+        run: |
+          find . -name '*.gcno' -exec rm {} \;
+          ./ci/codecov -v upload-process -Z --sha ${{ github.sha }} -f nodist/obj_dir/coverage/app_total.info

.github/workflows/docker.yml

@@ -1,13 +1,15 @@
+---
 # Build and push verilator docker image when tags are pushed to the repository.
-# The following secrets must be configured in the github repository:
+# The following variable(s) must be configured in the github repository:
 # DOCKER_HUB_NAMESPACE: docker hub namespace.
+# The following secrets must be configured in the github repository:
 # DOCKER_HUB_USER: user name for logging into docker hub
 # DOCKER_HUB_ACCESS_TOKEN: docker hub access token.
 name: Build Verilator Container
 
 on:
   push:
-    tags: [ 'v*' ]
+    tags: ['v*']
   workflow_dispatch:
     inputs:
       manual_tag:
@@ -20,11 +22,14 @@ on:
         type: boolean
         default: false
 
+permissions:
+  contents: write
+
 jobs:
 
   build:
 
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
 
     strategy:
       matrix:
@@ -33,52 +38,52 @@ jobs:
           # - "ci/docker/buildenv:verilator-buildenv"
 
     steps:
-    - name: Checkout
+      - name: Checkout
-      uses: actions/checkout@v3
+        uses: actions/checkout@v4
 
-    - name: Extract context variables
+      - name: Extract context variables
-      run: |
+        run: |
-        echo "${{ matrix.contexts }}" | sed -r 's/(.*):.*/build_context=\1/' >> "$GITHUB_ENV"
+          echo "${{ matrix.contexts }}" | sed -r 's/(.*):.*/build_context=\1/' >> "$GITHUB_ENV"
-        echo "${{ matrix.contexts }}" | sed -r 's/.*:(.*)/image_name=\1/' >> "$GITHUB_ENV"
+          echo "${{ matrix.contexts }}" | sed -r 's/.*:(.*)/image_name=\1/' >> "$GITHUB_ENV"
-        echo "git_tag=${GITHUB_REF#refs/*/}" >> "$GITHUB_ENV"
+          echo "git_tag=${GITHUB_REF#refs/*/}" >> "$GITHUB_ENV"
 
-    - name: Use manual tag
+      - name: Use manual tag
-      if: ${{ inputs.manual_tag }}
+        if: ${{ inputs.manual_tag }}
-      run: |
+        run: |
-        echo "git_tag=${{ inputs.manual_tag }}" >> "$GITHUB_ENV"
+          echo "git_tag=${{ inputs.manual_tag }}" >> "$GITHUB_ENV"
 
-    - name: Docker meta
+      - name: Docker meta
-      id: docker_meta
+        id: docker_meta
-      uses: docker/metadata-action@v4
+        uses: docker/metadata-action@v4
-      with:
+        with:
-        images: |
+          images: |
-          ${{ secrets.DOCKER_HUB_NAMESPACE }}/${{ env.image_name }}
+            ${{ vars.DOCKER_HUB_NAMESPACE }}/${{ env.image_name }}
-        tags: |
+          tags: |
-          type=match,pattern=(v.*),group=1,enable=${{ startsWith(github.ref, 'refs/tags/v') }}
+            type=match,pattern=(v.*),group=1,enable=${{ startsWith(github.ref, 'refs/tags/v') }}
-          type=raw,value=${{ inputs.manual_tag }},enable=${{ inputs.manual_tag != '' }}
+            type=raw,value=${{ inputs.manual_tag }},enable=${{ inputs.manual_tag != '' }}
-          type=raw,value=latest,enable=${{ inputs.add_latest_tag == true }}
+            type=raw,value=latest,enable=${{ inputs.add_latest_tag == true }}
 
-    - name: Set up QEMU
+      - name: Set up QEMU
-      uses: docker/setup-qemu-action@v2
+        uses: docker/setup-qemu-action@v2
 
-    - name: Set up Docker Buildx
+      - name: Set up Docker Buildx
-      uses: docker/setup-buildx-action@v2
+        uses: docker/setup-buildx-action@v2
-      with:
+        with:
           buildkitd-flags: --debug
 
-    - name: Login to Docker Hub
+      - name: Login to Docker Hub
-      uses: docker/login-action@v2
+        uses: docker/login-action@v2
-      with:
+        with:
-        username: ${{ secrets.DOCKER_HUB_USER }}
+          username: ${{ secrets.DOCKER_HUB_USER }}
-        password: ${{ secrets.DOCKER_HUB_ACCESS_TOKEN }}
+          password: ${{ secrets.DOCKER_HUB_ACCESS_TOKEN }}
 
-    - name: Build and Push to Docker
+      - name: Build and Push to Docker
-      uses: docker/build-push-action@v4
+        uses: docker/build-push-action@v4
-      if: startsWith(github.ref, 'refs/tags/v')
+        if: startsWith(github.ref, 'refs/tags/v') || github.event_name == 'workflow_dispatch'
-      with:
+        with:
-        context: ${{ env.build_context }}
+          context: ${{ env.build_context }}
-        build-args: SOURCE_COMMIT=${{ env.git_tag }}
+          build-args: SOURCE_COMMIT=${{ env.git_tag }}
-        platforms: linux/arm64,linux/amd64
+          platforms: linux/arm64,linux/amd64
-        push: ${{ !env.ACT && startsWith(github.ref, 'refs/tags/v') }}
+          push: ${{ !env.ACT && (startsWith(github.ref, 'refs/tags/v') || github.event_name == 'workflow_dispatch') }}
-        tags: ${{ steps.docker_meta.outputs.tags }}
+          tags: ${{ steps.docker_meta.outputs.tags }}
-        labels: ${{ steps.docker_meta.outputs.labels }}
+          labels: ${{ steps.docker_meta.outputs.labels }}

.github/workflows/format.yml

@@ -1,25 +1,25 @@
+---
 # DESCRIPTION: Github actions config
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
+#
 name: format
-
 on:
   push:
   pull_request_target:
   workflow_dispatch:
-
+permissions:
+  contents: write
 jobs:
   format:
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
-    name: Ubuntu 22.04 | format
+    name: Ubuntu 24.04 | format
     env:
       CI_OS_NAME: linux
-      CI_RUNS_ON: ubuntu-22.04
+      CI_RUNS_ON: ubuntu-24.04
       CI_COMMIT: ${{ github.sha }}
-      CI_M32: 0
     steps:
       - name: Checkout
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
         with:
           token: ${{ secrets.GITHUB_TOKEN }}
       - name: Install packages for build
@@ -27,14 +27,15 @@ jobs:
           CI_BUILD_STAGE_NAME: build
         run: |
           bash ci/ci-install.bash &&
-          sudo apt-get install clang-format-14 yapf3 &&
+          sudo apt-get install clang-format-18 yapf3 &&
+          sudo pip3 install gersemi mbake &&
           git config --global user.email "[email protected]" &&
           git config --global user.name "github action"
       - name: Format code
         run: |
           autoconf &&
           ./configure &&
-          make -j 2 format CLANGFORMAT=clang-format-14 &&
+          make -j 2 format CLANGFORMAT=clang-format-18 &&
           git status
       - name: Push
         run: |

.github/workflows/msbuild.yml

@@ -1,51 +1,52 @@
+---
 # DESCRIPTION: Github actions config
 # This name is key to badges in README.rst, so we use the name build
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
+#
 name: msbuild
-
 on:
   push:
   pull_request:
   workflow_dispatch:
   schedule:
-  - cron: '0 0 * * 0' # weekly
+    - cron: 0 0 * * 0  # weekly
-
+permissions:
+  contents: read
 env:
   CI_OS_NAME: win
   CI_COMMIT: ${{ github.sha }}
   CCACHE_COMPRESS: 1
   CCACHE_DIR: ${{ github.workspace }}/.ccache
   CCACHE_LIMIT_MULTIPLE: 0.95
-
 defaults:
   run:
     working-directory: repo
-
+concurrency:
+  group: ${{ github.workflow }}-${{ github.actor }}-${{ github.event_name == 'pull_request' && github.ref || github.run_id }}
+  cancel-in-progress: true
 jobs:
-
+  windows:
-   windows:
     name: run on windows
-    runs-on: windows-latest
+    runs-on: windows-2025
     steps:
-    - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
-      with:
+        with:
-        path: repo
+          path: repo
-    - name: Cache $CCACHE_DIR
+      - name: Cache $CCACHE_DIR
-      uses: actions/cache@v3
+        uses: actions/cache@v4
-      with:
+        with:
-        path: ${{ env.CCACHE_DIR }}
+          path: ${{ env.CCACHE_DIR }}
-        key: msbuild-msvc-cmake
+          key: msbuild-msvc-cmake
-    - name: compile
+      - name: compile
-      env:
+        env:
-        WIN_FLEX_BISON: ${{ github.workspace }}/.ccache
+          WIN_FLEX_BISON: ${{ github.workspace }}/.ccache
-      run: ./ci/ci-win-compile.ps1
+        run: ./ci/ci-win-compile.ps1
-    - name: test build
+      - name: test build
-      run: ./ci/ci-win-test.ps1
+        run: ./ci/ci-win-test.ps1
-    - name: Zip up repository
+      - name: Zip up repository
-      run: Compress-Archive -LiteralPath install -DestinationPath verilator.zip
+        run: Compress-Archive -LiteralPath install -DestinationPath verilator.zip
-    - name: Upload zip archive
+      - name: Upload zip archive
-      uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
-      with:
+        with:
-        path: ${{ github.workspace }}/repo/verilator.zip
+          path: ${{ github.workspace }}/repo/verilator.zip
-        name: verilator-win.zip
+          name: verilator-win.zip

.github/workflows/reusable-build.yml

@@ -0,0 +1,75 @@
+---
+# DESCRIPTION: Github actions config
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+name: reusable-build
+
+on:
+  workflow_call:
+    inputs:
+      os:  # e.g. ubuntu-24.04
+        required: true
+        type: string
+      cc:  # gcc or clang
+        required: true
+        type: string
+
+env:
+  CI_OS_NAME: linux
+  CI_COMMIT: ${{ github.sha }}
+  CCACHE_COMPRESS: 1
+  CCACHE_DIR: ${{ github.workspace }}/.ccache
+  CCACHE_LIMIT_MULTIPLE: 0.95
+  INSTALL_DIR: ${{ github.workspace }}/install
+  RELOC_DIR: ${{ github.workspace }}/relloc
+
+defaults:
+  run:
+    shell: bash
+    working-directory: repo
+
+jobs:
+
+  build:
+    runs-on: ${{ inputs.os }}
+    name: Sub-build | ${{ inputs.os }} | ${{ inputs.cc }}
+    env:
+      CI_BUILD_STAGE_NAME: build
+      CI_RUNS_ON: ${{ inputs.os }}
+      CC: ${{ inputs.cc }}
+      CXX: ${{ inputs.cc == 'clang' && 'clang++' || 'g++' }}
+      CACHE_BASE_KEY: build-${{ inputs.os }}-${{ inputs.cc }}
+      CCACHE_MAXSIZE: 1000M  # Per build matrix entry (* 5 = 5000M in total)
+      VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ inputs.os }}-${{ inputs.cc }}.tar.gz
+    steps:
+
+      - name: Checkout
+        uses: actions/checkout@v4
+        with:
+          path: repo
+
+      - name: Cache $CCACHE_DIR
+        uses: actions/cache@v4
+        env:
+          CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
+        with:
+          path: ${{ env.CCACHE_DIR }}
+          key: ${{ env.CACHE_KEY }}-${{ github.sha }}
+          restore-keys: |
+            ${{ env.CACHE_KEY }}-
+
+      - name: Install packages for build
+        run: ./ci/ci-install.bash
+
+      - name: Build
+        run: ./ci/ci-script.bash
+
+      - name: Tar up repository
+        working-directory: ${{ github.workspace }}
+        run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo
+
+      - name: Upload tar archive
+        uses: actions/upload-artifact@v4
+        with:
+          path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }}
+          name: ${{ env.VERILATOR_ARCHIVE }}

.github/workflows/reusable-rtlmeter-build.yml

@@ -0,0 +1,72 @@
+---
+# DESCRIPTION: Github actions config
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+name: reusable-rtlmeter-build
+
+on:
+  workflow_call:
+    inputs:
+      runs-on:
+        description: "Runner to use, e.g.: ubuntu-24.04"
+        type: string
+        required: true
+      cc:
+        description: "Compiler to use: 'gcc' or 'clang'"
+        type: string
+        required: true
+
+defaults:
+  run:
+    shell: bash
+
+env:
+  CCACHE_DIR: ${{ github.workspace }}/ccache
+  CCACHE_MAXSIZE: 512M
+
+jobs:
+  build:
+    runs-on: ${{ inputs.runs-on }}
+    name: Build
+    steps:
+      - name: Install dependencies
+        run: |
+          sudo apt update
+          sudo apt install ccache mold help2man libfl-dev libgoogle-perftools-dev libsystemc-dev
+
+      - name: Use saved ccache
+        uses: actions/cache@v4
+        with:
+          path: ccache
+          key: rtlmeter-build-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ github.run_id }}-${{ github.run_attempt }}
+          restore-keys: rtlmeter-build-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}
+
+      - name: Checkout
+        uses: actions/checkout@v4
+        with:
+          path: repo
+          fetch-depth: 0 # Required for 'git describe' used for 'verilator --version'
+
+      - name: Configure
+        working-directory: repo
+        run: |
+          autoconf
+          ./configure --prefix=${{ github.workspace }}/install CXX=${{ inputs.cc == 'clang' && 'clang++' || 'g++' }}
+
+      - name: Make
+        working-directory: repo
+        run: make -j $(nproc)
+
+      - name: Install
+        working-directory: repo
+        run: make install
+
+      - name: Tar up installation
+        run: tar --posix -c -z -f verilator-rtlmeter.tar.gz install
+
+      - name: Upload Verilator installation archive
+        uses: actions/upload-artifact@v4
+        with:
+          path: verilator-rtlmeter.tar.gz
+          name: verilator-rtlmeter-${{ inputs.runs-on }}-${{ inputs.cc }}
+          overwrite: true

.github/workflows/reusable-rtlmeter-run.yml

@@ -0,0 +1,128 @@
+---
+# DESCRIPTION: Github actions config
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+name: reusable-rtlmeter-run
+
+on:
+  workflow_call:
+    inputs:
+      tag:
+        description: "Unique identifier for storing results"
+        type: string
+        required: true
+      runs-on:
+        description: "Runner to use, e.g.: ubuntu-24.04"
+        type: string
+        required: true
+      cc:
+        description: "Compiler to use: 'gcc' or 'clang'"
+        type: string
+        required: true
+      # Note: The combination of 'cases' and 'run-name' must be unique for all
+      # invocations of this workflow within a run of the parent workflow.
+      # These two are used together to generate a unique results file name.
+      cases:
+        description: "RTLMeter cases to run"
+        type: string
+        required: true
+      run-name:
+        description: "Run name (identifier) to add to collated results"
+        type: string
+        required: true
+      compileArgs:
+        description: "Additional Verilator command line arguments"
+        type: string
+        default: ""
+      executeArgs:
+        description: "Additional simulator command line arguments"
+        type: string
+        default: ""
+
+defaults:
+  run:
+    shell: bash
+
+env:
+  CCACHE_DIR: ${{ github.workspace }}/ccache
+  CCACHE_MAXSIZE: 512M
+  CCACHE_DISABLE: 1
+
+jobs:
+  run:
+    runs-on: ${{ inputs.runs-on }}
+    name: Run
+    steps:
+      - name: Install dependencies
+        run: |
+          sudo apt update
+          sudo apt install ccache mold libfl-dev libgoogle-perftools-dev libsystemc-dev
+
+      - name: Download Verilator installation archive
+        uses: actions/download-artifact@v4
+        with:
+          name: verilator-rtlmeter-${{ inputs.runs-on }}-${{ inputs.cc }}
+
+      - name: Unpack Verilator installation archive
+        run: |
+          tar -x -z -f verilator-rtlmeter.tar.gz
+          echo "${{ github.workspace }}/install/bin" >> $GITHUB_PATH
+
+      - name: Use saved ccache
+        if: ${{ env.CCACHE_DISABLE == 0 }}
+        uses: actions/cache@v4
+        with:
+          path: ${{ env.CCACHE_DIR }}
+          key: rtlmeter-run-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ inputs.cases }}-${{ inputs.compileArgs }}-${{ github.run_id }}-${{ github.run_attempt }}
+          restore-keys: rtlmeter-run-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ inputs.cases }}-${{ inputs.compileArgs }}
+
+      - name: Checkout RTLMeter
+        uses: actions/checkout@v4
+        with:
+          repository: "verilator/rtlmeter"
+          path: rtlmeter
+
+      - name: Setup RTLMeter venv
+        working-directory: rtlmeter
+        run: make venv
+
+      - name: Compile cases
+        working-directory: rtlmeter
+        run: |
+          ./rtlmeter run --verbose --cases='${{ inputs.cases }}' --compileArgs='${{ inputs.compileArgs }}' --executeArgs='${{ inputs.executeArgs }}' --nExecute=0
+          # My YAML highlighter sucks, so I put this comment here wiht a phony closing quote mark to make it work: '
+
+      - name: Execute cases
+        working-directory: rtlmeter
+        continue-on-error: true  # Do not fail on error, so we can at leat save the successful results
+        run: |
+          ./rtlmeter run --verbose --cases='${{ inputs.cases }}' --compileArgs='${{ inputs.compileArgs }}' --executeArgs='${{ inputs.executeArgs }}'
+          # My YAML highlighter sucks, so I put this comment here wiht a phony closing quote mark to make it work: '
+
+      - name: Collate results
+        id: results
+        working-directory: rtlmeter
+        run: |
+          # Use 'inputs.cases' and 'inputs.run-name' to generate a unique file name
+          hash=$(md5sum <<< '${{ inputs.cases }} ${{ inputs.run-name }}' | awk '{print $1}')
+          echo "hash=${hash}" >> $GITHUB_OUTPUT
+          ./rtlmeter collate --runName "${{ inputs.run-name }}"  > ../results-${hash}.json
+
+      - name: Report results
+        working-directory: rtlmeter
+        run: |
+          ./rtlmeter report --steps '*' --metrics '*' ../results-${{ steps.results.outputs.hash }}.json
+
+      - name: Upload results
+        uses: actions/upload-artifact@v4
+        with:
+          path: results-${{ steps.results.outputs.hash }}.json
+          name: rtlmeter-results-${{ inputs.tag }}-${{ steps.results.outputs.hash }}
+          overwrite: true
+          retention-days: 2
+
+      - name: Report status
+        working-directory: rtlmeter
+        run: | # This will fail the job if any of the runs failed
+          ./rtlmeter run --verbose --cases='${{ inputs.cases }}' --compileArgs='${{ inputs.compileArgs }}' --executeArgs='${{ inputs.executeArgs }}'
+          # My YAML highlighter sucks, so I put this comment here wiht a phony closing quote mark to make it work: '

.github/workflows/reusable-test.yml

@@ -0,0 +1,79 @@
+---
+# DESCRIPTION: Github actions config
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+name: reusable-test
+
+on:
+  workflow_call:
+    inputs:
+      os:  # e.g. ubuntu-24.04
+        required: true
+        type: string
+      cc:  # gcc or clang
+        required: true
+        type: string
+      reloc:  # 0 or 1
+        required: true
+        type: number
+      suite:  # e.g. dist-vlt-0
+        required: true
+        type: string
+
+env:
+  CI_OS_NAME: linux
+  CI_COMMIT: ${{ github.sha }}
+  CCACHE_COMPRESS: 1
+  CCACHE_DIR: ${{ github.workspace }}/.ccache
+  CCACHE_LIMIT_MULTIPLE: 0.95
+  INSTALL_DIR: ${{ github.workspace }}/install
+  RELOC_DIR: ${{ github.workspace }}/relloc
+
+defaults:
+  run:
+    shell: bash
+    working-directory: repo
+
+jobs:
+
+  test:
+    runs-on: ${{ inputs.os }}
+    name: Sub-test | ${{ inputs.os }} | ${{ inputs.cc }} | ${{inputs.reloc && 'reloc | ' || '' }} ${{ inputs.suite }}
+    env:
+      CI_BUILD_STAGE_NAME: test
+      CI_RUNS_ON: ${{ inputs.os }}
+      CI_RELOC: ${{inputs.reloc }}
+      CC: ${{ inputs.cc }}
+      CXX: ${{ inputs.cc == 'clang' && 'clang++' || 'g++' }}
+      CACHE_BASE_KEY: test-${{ inputs.os }}-${{ inputs.cc }}-${{inputs.reloc }}-${{ inputs.suite }}
+      CCACHE_MAXSIZE: 100M  # Per build per suite (* 5 * 5 = 2500M in total)
+      VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ inputs.os }}-${{ inputs.cc }}.tar.gz
+    steps:
+
+      - name: Download tar archive
+        uses: actions/download-artifact@v4
+        with:
+          name: ${{ env.VERILATOR_ARCHIVE }}
+          path: ${{ github.workspace }}
+
+      - name: Unpack tar archive
+        working-directory: ${{ github.workspace }}
+        run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }}
+
+      - name: Cache $CCACHE_DIR
+        uses: actions/cache@v4
+        env:
+          CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache2
+        with:
+          path: ${{ env.CCACHE_DIR }}
+          key: ${{ env.CACHE_KEY }}-${{ github.sha }}
+          restore-keys: |
+            ${{ env.CACHE_KEY }}-
+
+      - name: Install test dependencies
+        run: ./ci/ci-install.bash
+
+      - name: Test
+        env:
+          TESTS: ${{ inputs.suite }}
+        run: ./ci/ci-script.bash

.github/workflows/rtlmeter.yml

@@ -0,0 +1,322 @@
+---
+# DESCRIPTION: Github actions config
+# This name is key to badges in README.rst, so we use the name build
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+name: RTLMeter
+
+on:
+  workflow_dispatch:
+  schedule:
+    - cron: '0 2 * * *'  # Daily, starting at 02:00 UTC
+  pull_request:
+    types:
+      - opened
+      - synchronize
+      - reopened
+      - labeled
+      - unlabeled
+
+permissions:
+  contents: read
+
+defaults:
+  run:
+    shell: bash
+
+concurrency:
+  group: ${{ github.ref }}
+  cancel-in-progress: ${{ github.event_name != 'schedule' }}
+
+jobs:
+  start:
+    name: Start
+    # Only run scheduled jobs if explicitly enabled for that repo (e.g.: not on forks)
+    # Only run pull request jobs if labelled as needing an RTLMeter run
+    # Always run workflow dispatch jobs
+    if: |
+      (github.event_name == 'schedule'
+        && vars.ENABLE_SCHEDULED_JOBS == 'true') ||
+      (github.event_name == 'pull_request'
+        && contains(github.event.pull_request.labels.*.name, 'pr: rtlmeter')) ||
+      (github.event_name == 'workflow_dispatch')
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Startup
+        run: echo
+
+  build-gcc:
+    name: Build GCC
+    needs: start
+    uses: ./.github/workflows/reusable-rtlmeter-build.yml
+    with:
+      runs-on: ubuntu-24.04
+      cc: gcc
+
+  build-clang:
+    name: Build Clang
+    needs: start
+    uses: ./.github/workflows/reusable-rtlmeter-build.yml
+    with:
+      runs-on: ubuntu-24.04
+      cc: clang
+
+  run-gcc:
+    name: Run GCC | ${{ matrix.cases }}
+    needs: build-gcc
+    uses: ./.github/workflows/reusable-rtlmeter-run.yml
+    with:
+      tag: gcc
+      runs-on: ubuntu-24.04
+      cc: gcc
+      cases: ${{ matrix.cases }}
+      run-name: "gcc"
+      compileArgs: ""
+      executeArgs: ""
+    strategy:
+      fail-fast: false
+      max-parallel: ${{ github.event == 'schedule' && 2 || 7 }}
+      matrix:
+        cases:
+          - "NVDLA:*"
+          - "OpenPiton:1x1:*"
+          - "OpenPiton:2x2:*"
+          - "OpenPiton:4x4:*"
+          - "OpenTitan:*"
+          - "VeeR-EH1:asic*"
+          - "VeeR-EH1:default*"
+          - "VeeR-EH1:hiperf*"
+          - "VeeR-EH2:asic*"
+          - "VeeR-EH2:default*"
+          - "VeeR-EH2:hiperf*"
+          - "VeeR-EL2:asic*"
+          - "VeeR-EL2:default*"
+          - "VeeR-EL2:hiperf*"
+          - "Vortex:mini:*"
+          - "Vortex:sane:*"
+          - "XiangShan:default-chisel3:* !*:linux"
+          - "XiangShan:default-chisel6:* !*:linux"
+          - "XiangShan:mini-chisel3:* !*:linux"
+          - "XiangShan:mini-chisel6:* !*:linux"
+          - "XuanTie-E902:*"
+          - "XuanTie-E906:*"
+          - "XuanTie-C906:*"
+          - "XuanTie-C910:*"
+
+  run-clang:
+    name: Run Clang | ${{ matrix.cases }}
+    needs: build-clang
+    uses: ./.github/workflows/reusable-rtlmeter-run.yml
+    with:
+      tag: clang
+      runs-on: ubuntu-24.04
+      cc: clang
+      cases: ${{ matrix.cases }}
+      run-name: "clang --threads 4"
+      compileArgs: "--threads 4"
+      executeArgs: ""
+    strategy:
+      fail-fast: false
+      max-parallel: ${{ github.event == 'schedule' && 2 || 7 }}
+      matrix:
+        cases:
+          - "NVDLA:*"
+          - "OpenPiton:1x1:*"
+          - "OpenPiton:2x2:*"
+          - "OpenPiton:4x4:*"
+          - "OpenTitan:*"
+          - "VeeR-EH1:asic*"
+          - "VeeR-EH1:default*"
+          - "VeeR-EH1:hiperf*"
+          - "VeeR-EH2:asic*"
+          - "VeeR-EH2:default*"
+          - "VeeR-EH2:hiperf*"
+          - "VeeR-EL2:asic*"
+          - "VeeR-EL2:default*"
+          - "VeeR-EL2:hiperf*"
+          - "Vortex:mini:*"
+          - "Vortex:sane:*"
+          - "XiangShan:default-chisel3:* !*:linux"
+          - "XiangShan:default-chisel6:* !*:linux"
+          - "XiangShan:mini-chisel3:* !*:linux"
+          - "XiangShan:mini-chisel6:* !*:linux"
+          - "XuanTie-E902:*"
+          - "XuanTie-E906:*"
+          - "XuanTie-C906:*"
+          - "XuanTie-C910:*"
+
+  combine-results:
+    name: Combine results
+    needs: [run-gcc, run-clang]
+    # Run if any of the dependencies have run, even if failed.
+    # That is: do not run if all skipped, or the workflow was cancelled.
+    if: ${{ (contains(needs.*.result, 'success') || contains(needs.*.result, 'failure')) && !cancelled() }}
+    runs-on: ubuntu-24.04
+    strategy:
+      fail-fast: false
+      matrix:
+        tag:
+          - gcc
+          - clang
+    steps:
+      - name: Checkout RTLMeter
+        uses: actions/checkout@v4
+        with:
+          repository: "verilator/rtlmeter"
+          path: rtlmeter
+      - name: Setup RTLMeter venv
+        working-directory: rtlmeter
+        run: make venv
+      - name: Download all results
+        uses: actions/download-artifact@v4
+        with:
+          pattern: rtlmeter-results-${{ matrix.tag }}-*
+          path: all-results-${{ matrix.tag }}
+          merge-multiple: true
+      - name: Combine results
+        working-directory: rtlmeter
+        run: |
+          ./rtlmeter collate ../all-results-${{ matrix.tag }}/*.json > ../all-results-${{ matrix.tag }}.json
+      - name: Upload combined results
+        uses: actions/upload-artifact@v4
+        with:
+          path: all-results-${{ matrix.tag }}.json
+          name: all-results-${{ matrix.tag }}
+          overwrite: true
+          retention-days: 30
+
+  publish-scheduled-results:
+    name: Publish results to verilator/verilator-rtlmeter-results
+    needs: combine-results
+    # Only run on scheduled builds on the main repository. We also restrict
+    # the publishing to run only on the first run_attempt. This is required
+    # to prevent multiple uploads the same day (if rerunning), as the
+    # dashboard UI currently assumes there is only one data point per
+    # calendar day. Results from reruns can be imported manually if needed.
+    if: ${{ github.event_name == 'schedule' && github.repository == 'verilator/verilator' && github.run_attempt == 1 && contains(needs.*.result, 'success') && !cancelled() }}
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Download combined results
+        uses: actions/download-artifact@v4
+        with:
+          pattern: all-results-*
+          path: results
+          merge-multiple: true
+      - name: Upload published results
+        uses: actions/upload-artifact@v4
+        with:
+          path: results/*.json
+          name: published-results
+      # Pushing to verilator/verilator-rtlmeter-results requires elevated permissions
+      - name: Generate access token
+        id: generate-token
+        uses: actions/[email protected]
+        with:
+          app-id: ${{ vars.VERILATOR_CI_ID }}
+          private-key: ${{ secrets.VERILATOR_CI_KEY }}
+          owner: verilator
+          repositories: verilator-rtlmeter-results
+          permission-contents: write
+      - name: Checkout verilator-rtlmeter-results
+        uses: actions/checkout@v4
+        with:
+          repository: "verilator/verilator-rtlmeter-results"
+          token: ${{ steps.generate-token.outputs.token }}
+          path: verilator-rtlmeter-results
+      - name: Import results
+        id: import-results
+        working-directory: verilator-rtlmeter-results
+        run: |
+          for f in $(find ../results -name "*.json"); do \
+            echo "Importing $f"; \
+            ./bin/add-rtlmeter-result $f; \
+          done
+          test -z "$(git status --porcelain)" || echo "valid=1" >> "$GITHUB_OUTPUT"
+      - name: Push to verilator-rtlmeter-results
+        if: ${{ steps.import-results.outputs.valid }}
+        working-directory: verilator-rtlmeter-results
+        run: |
+          git config --global user.email "[email protected]"
+          git config --global user.name "github action"
+          git add .
+          git commit -m "Verilator CI: Results of 'RTLMeter' workflow run #${{ github.run_number }}"
+          git push origin
+
+  #publish-pr-results:
+  #  name: Publish results to Pull Request
+  #  needs: combine-results
+  #  if: ${{ github.event_name == 'pull_request' && github.repository == 'verilator/verilator' && github.run_attempt == 1 && contains(needs.*.result, 'success') && !cancelled() }}
+  #  runs-on: ubuntu-24.04
+  #  steps:
+  #    - name: Checkout RTLMeter
+  #      uses: actions/checkout@v4
+  #      with:
+  #        repository: "verilator/rtlmeter"
+  #        path: rtlmeter
+  #    - name: Setup RTLMeter venv
+  #      working-directory: rtlmeter
+  #      run: make venv
+  #    - name: Download combined results
+  #      uses: actions/download-artifact@v4
+  #      with:
+  #        pattern: all-results-*
+  #        path: all-results
+  #        merge-multiple: true
+  #    - name: Get scheduled run info
+  #      id: scheduled-info
+  #      run:
+  #        IDLATEST=$(gh run list --workflow RTLMeter --event schedule --status success --limit 1 --json databaseId --jq ".[0].databaseId")
+  #        echo "id=$IDLATEST" >> $GITHUB_OUTPUT
+  #        URL=$(gh run view $IDLATEST --json url --jq ".url")
+  #        echo "url=$URL" >> $GITHUB_OUTPUT
+  #        NUM=$(gh run view $IDLATEST --json number --jq ".number")
+  #        echo "num=$NUM" >> $GITHUB_OUTPUT
+  #    # Fetching artifacts from different workflow requires elevated privilege
+  #    - name: Generate access token
+  #      id: generate-token
+  #      uses: actions/[email protected]
+  #      with:
+  #        app-id: ${{ vars.VERILATOR_CI_ID }}
+  #        private-key: ${{ secrets.VERILATOR_CI_KEY }}
+  #        owner: verilator
+  #        repositories: verilator
+  #        permission-actions: read
+  #    - name: Download scheduled run results
+  #      uses: actions/download-artifact@v4
+  #      with:
+  #        name: published-results
+  #        path: nightly-results
+  #        run-id: ${{ steps.schedueld-info.outputs.id }}
+  #        github-token: ${{ steps.generate-token.outputs.token }}
+  #    # TODO: diff and present
+
+  # Create GitHub issue for failed schedueld jobs
+  # This should always be the last job (we want an issue if anything breaks)
+  create-issue:
+    name: Create issue on failure
+    needs: publish-scheduled-results
+    if: ${{ github.event_name == 'schedule' && github.repository == 'verilator/verilator' && github.run_attempt == 1 && failure() && !cancelled() }}
+    runs-on: ubuntu-24.04
+    steps:
+      # Creating issues requires elevated privilege
+      - name: Generate access token
+        id: generate-token
+        uses: actions/[email protected]
+        with:
+          app-id: ${{ vars.VERILATOR_CI_ID }}
+          private-key: ${{ secrets.VERILATOR_CI_KEY }}
+          owner: verilator
+          repositories: verilator
+          permission-issues: write
+      - name: Create issue
+        env:
+          GH_TOKEN: ${{ steps.generate-token.outputs.token }}
+        run: |
+          echo "This issue was created automatically by the GitHub Actions CI due to the failure of a scheduled RTLMeter run." >> body.txt
+          echo "" >> body.txt
+          echo "Workflow status: ${{ github.server_url }}/${{ github.repository }}/actions/runs/${{ github.run_id }}" >> body.txt
+          gh issue --repo ${{ github.repository }} create \
+            --title "RTLMeter run #${{ github.run_number }} Failed" \
+            --body-file body.txt \
+            --label new \
+            --assignee gezalore,wsnyder

.gitignore

@@ -29,15 +29,24 @@ dddrun*
 doxygen-doc
 gdbrun*
 gmon.out
-ncverilog.history
 internals.txt
+ncverilog.history
+nohup.out
+verilator-config-version.cmake
+verilator-config.cmake
+verilator.pc
 verilator.txt
 verilator_bin*
 verilator_coverage_bin*
-verilator.pc
-verilator-config.cmake
-verilator-config-version.cmake
 **/__pycache__/*
 **/_build/*
 **/obj_dir/*
 /.vscode/
+/.idea/
+/cmake-build-*/
+/test_regress/snapshot/
+xmverilog.*
+xrun.history
+
+# Normal CMake build directory
+/build

.pre-commit-hooks.yaml

@@ -0,0 +1,8 @@
+---
+- id: verilator
+  name: verilator-lint
+  description: Runs verilator Docker image to lint (System) Verilog designs
+  args: [--lint-only]
+  language: docker_image
+  entry: verilator/verilator:latest
+  types_or: [verilog, system-verilog]

.style.yapf

@@ -0,0 +1,4 @@
+[style]
+based_on_style = pep8
+column_limit = 99
+#split_before_arithmetic_operator=True

CITATION.cff

@@ -0,0 +1,27 @@
+# See https://citation-file-format.github.io/
+cff-version: 1.2.0
+title: Verilator
+message: >-
+  If you use this software, please cite it using the
+  metadata from this file.
+type: software
+authors:
+  - given-names: Wilson
+    family-names: Snyder
+    email: [email protected]
+    affiliation: Veripool
+  - given-names: Paul
+    family-names: Wasson
+  - given-names: Duane
+    family-names: Galbi
+  - name: 'et al'
+repository-code: 'https://github.com/verilator/verilator'
+url: 'https://verilator.org'
+abstract: >-
+  The Verilator package converts Verilog and SystemVerilog hardware
+  description language (HDL) designs into a fast C++ or SystemC model
+  that, after compiling, can be executed.  Verilator is not a
+  traditional simulator but a compiler.
+license:
+  - LGPL-3.0-only
+  - Artistic-2.0

CMakeLists.txt

@@ -4,7 +4,7 @@
 #
 #*****************************************************************************
 #
-# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -14,48 +14,87 @@
 
 cmake_minimum_required(VERSION 3.15)
 cmake_policy(SET CMP0091 NEW) # Use MSVC_RUNTIME_LIBRARY to select the runtime
-project(Verilator
+project(
-    VERSION 5.014
+    Verilator
+    VERSION 5.040
     HOMEPAGE_URL https://verilator.org
     LANGUAGES CXX
 )
 
-option(DEBUG_AND_RELEASE_AND_COVERAGE
+# Set default build type to Release if not specified
-    "Builds both the debug and release binaries, overriding CMAKE_BUILD_TYPE. Not supported under MSBuild.")
+if(NOT CMAKE_BUILD_TYPE)
+    set(CMAKE_BUILD_TYPE "Release" CACHE STRING "Build type" FORCE)
+endif()
+
+option(
+    DEBUG_AND_RELEASE_AND_COVERAGE
+    "Builds both the debug and release binaries, overriding CMAKE_BUILD_TYPE. Not supported under MSBuild."
+)
 
 find_package(Python3 COMPONENTS Interpreter)
-set(PYTHON3 Python3::Interpreter)
+set(PYTHON3 ${Python3_EXECUTABLE})
-set(CMAKE_INSTALL_DATADIR ${CMAKE_INSTALL_PREFIX})
+# See also CMake built-in; CMAKE_INSTALL_PREFIX is applied by the install command.
+set(CMAKE_INSTALL_DATADIR .)
 include(GNUInstallDirs)
 include(CMakePackageConfigHelpers)
 include(CheckStructHasMember)
 include(ExternalProject)
+include(FindThreads)
 
-if (NOT WIN32)
+if(NOT WIN32)
     message(WARNING "CMake support on Linux/OSX is experimental.")
 endif()
 
-if (MSVC)
+if(WIN32)
-    if (DEFINED ENV{WIN_FLEX_BISON})
+    if(DEFINED ENV{WIN_FLEX_BISON})
         set(WIN_FLEX_BISON "$ENV{WIN_FLEX_BISON}")
     endif()
-    if (EXISTS ${WIN_FLEX_BISON})
+    if(EXISTS ${WIN_FLEX_BISON})
         list(APPEND CMAKE_PREFIX_PATH ${WIN_FLEX_BISON})
     endif()
-    if (NOT WIN_FLEX_BISON)
+    if(NOT WIN_FLEX_BISON)
-        message(FATAL_ERROR "Please install https://github.com/lexxmark/winflexbison and set WIN_FLEX_BISON environment variable. Please use install cmake target after a successful build.")
+        message(
+            FATAL_ERROR
+            "Please install https://github.com/lexxmark/winflexbison and set WIN_FLEX_BISON environment variable. Please use install cmake target after a successful build."
+        )
     endif()
     set(CMAKE_CXX_STANDARD 20)
 endif()
 
+set(OBJCACHE "" CACHE STRING "Path for ccache, auto-detected if empty")
+option(OBJCACHE_ENABLED "Compile Verilator with ccache" ON)
+
+if(OBJCACHE_ENABLED)
+    if(OBJCACHE STREQUAL "")
+        find_program(OBJCACHE_PATH ccache)
+        if(OBJCACHE_PATH STREQUAL "OBJCACHE_PATH-NOTFOUND")
+            set(OBJCACHE_PATH "")
+        endif()
+    else()
+        set(OBJCACHE_PATH "${OBJCACHE}")
+    endif()
+    if(NOT OBJCACHE_PATH STREQUAL "")
+        execute_process(
+            COMMAND "${OBJCACHE_PATH}" --version
+            OUTPUT_VARIABLE objcache_version
+        )
+        string(REGEX MATCH "[^\n\r]+" objcache_version "${objcache_version}")
+        message(
+            STATUS
+            "Found ccache: ${OBJCACHE_PATH} (\"${objcache_version}\")"
+        )
+        set(CMAKE_CXX_COMPILER_LAUNCHER "${OBJCACHE_PATH}")
+    endif()
+endif()
+
 find_package(BISON)
 find_package(FLEX)
 
 # Build
 #set_property(GLOBAL PROPERTY JOB_POOLS one_job=1)
 
-if (DEBUG_AND_RELEASE_AND_COVERAGE)
+if(DEBUG_AND_RELEASE_AND_COVERAGE)
-    if (CMAKE_GENERATOR MATCHES "^Visual Studio ")
+    if(CMAKE_GENERATOR MATCHES "^Visual Studio ")
         error("%Error: The DEBUG_AND_RELEASE_AND_COVERAGE option is not supported in MSBuild-based builds.")
     endif()
     set(saved_build_type ${CMAKE_BUILD_TYPE})
@@ -74,44 +113,69 @@ endif()
 
 set(PACKAGE_NAME ${PROJECT_NAME})
 set(PACKAGE_VERSION ${PROJECT_VERSION})
+set(CXX ${CMAKE_CXX_COMPILER})
+set(AR ${CMAKE_AR})
 
 configure_file(include/verilated_config.h.in include/verilated_config.h @ONLY)
+configure_file(include/verilated.mk.in include/verilated.mk @ONLY)
 
-install(FILES ${CMAKE_CURRENT_BINARY_DIR}/include/verilated_config.h DESTINATION ${CMAKE_INSTALL_PREFIX}/include)
+install(
-
+    FILES ${CMAKE_CURRENT_BINARY_DIR}/include/verilated_config.h
-configure_package_config_file(verilator-config.cmake.in verilator-config.cmake
+    DESTINATION include
-    INSTALL_DESTINATION ${CMAKE_INSTALL_PREFIX}
+)
+install(
+    FILES ${CMAKE_CURRENT_BINARY_DIR}/include/verilated.mk
+    DESTINATION include
 )
 
-install(FILES ${CMAKE_CURRENT_BINARY_DIR}/verilator-config.cmake DESTINATION ${CMAKE_INSTALL_PREFIX})
+configure_package_config_file(
-
+    verilator-config.cmake.in
-configure_package_config_file(verilator-config-version.cmake.in verilator-config-version.cmake
+    verilator-config.cmake
-    INSTALL_DESTINATION ${CMAKE_INSTALL_PREFIX}
+    INSTALL_DESTINATION .
 )
 
-install(FILES ${CMAKE_CURRENT_BINARY_DIR}/verilator-config-version.cmake DESTINATION ${CMAKE_INSTALL_PREFIX})
+install(FILES ${CMAKE_CURRENT_BINARY_DIR}/verilator-config.cmake DESTINATION .)
 
-foreach (program
+configure_package_config_file(
+    verilator-config-version.cmake.in
+    verilator-config-version.cmake
+    INSTALL_DESTINATION .
+)
+
+install(
+    FILES ${CMAKE_CURRENT_BINARY_DIR}/verilator-config-version.cmake
+    DESTINATION .
+)
+
+foreach(
+    program
     verilator
     verilator_gantt
     verilator_ccache_report
     verilator_difftree
     verilator_profcfunc
+    verilator_includer
 )
     install(PROGRAMS bin/${program} TYPE BIN)
 endforeach()
 
-install(DIRECTORY examples TYPE DATA FILES_MATCHING
+install(
+    DIRECTORY examples
+    TYPE DATA
+    FILES_MATCHING
     PATTERN "examples/*/*.[chv]*"
     PATTERN "examples/*/Makefile*"
     PATTERN "examples/*/CMakeLists.txt"
 )
 
-install(DIRECTORY include TYPE DATA FILES_MATCHING
+install(
+    DIRECTORY include
+    TYPE DATA
+    FILES_MATCHING
     PATTERN "include/verilated_config.h"
-    PATTERN "include/verilated.mk"
     PATTERN "include/*.[chv]"
     PATTERN "include/*.cpp"
+    PATTERN "include/*.vlt"
     PATTERN "include/*.sv"
     PATTERN "include/gtkwave/*.[chv]*"
     PATTERN "include/vltstd/*.[chv]*"

Makefile.in

@@ -7,7 +7,7 @@
 #
 #*****************************************************************************
 #
-# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -52,6 +52,7 @@ INSTALL_PROGRAM = @INSTALL_PROGRAM@
 INSTALL_DATA = @INSTALL_DATA@
 MAKEINFO = makeinfo
 POD2TEXT = pod2text
+PYTHON3 = @PYTHON3@
 MKINSTALLDIRS = $(SHELL) $(srcdir)/src/mkinstalldirs
 
 # Version (for docs/guide/conf.py)
@@ -76,7 +77,7 @@ datadir = @datadir@
 # Directory in which to install documentation info files.
 infodir = @infodir@
 
-# Directory in which to install package specific files
+# Directory in which to install package-specific files
 # Generally ${prefix}/share/verilator
 pkgdatadir = @pkgdatadir@
 
@@ -91,61 +92,66 @@ datarootdir = @datarootdir@
 CFG_WITH_CCWARN = @CFG_WITH_CCWARN@
 CFG_WITH_DEFENV = @CFG_WITH_DEFENV@
 CFG_WITH_LONGTESTS = @CFG_WITH_LONGTESTS@
+CFG_WITH_SOLVER = @CFG_WITH_SOLVER@
 PACKAGE_VERSION = @PACKAGE_VERSION@
 
 #### End of system configuration section. ####
 ######################################################################
+# Main build targets
 
 .SUFFIXES:
 
 SHELL = /bin/sh
 
 SUBDIRS = docs src test_regress \
-	examples/cmake_hello_c \
+  examples/cmake_hello_c \
-	examples/cmake_hello_sc \
+  examples/cmake_hello_sc \
-	examples/cmake_tracing_c \
+  examples/cmake_tracing_c \
-	examples/cmake_tracing_sc \
+  examples/cmake_tracing_sc \
-	examples/cmake_protect_lib \
+  examples/cmake_protect_lib \
-	examples/make_hello_binary \
+  examples/make_hello_binary \
-	examples/make_hello_c \
+  examples/make_hello_c \
-	examples/make_hello_sc \
+  examples/make_hello_sc \
-	examples/make_tracing_c \
+  examples/make_tracing_c \
-	examples/make_tracing_sc \
+  examples/make_tracing_sc \
-	examples/make_protect_lib \
+  examples/make_protect_lib \
-	examples/xml_py \
+  examples/json_py \
 
 INFOS = verilator.html verilator.pdf
 
 INFOS_OLD = README README.html README.pdf
 
 EXAMPLES_FIRST = \
-	examples/make_hello_c \
+  examples/make_hello_c \
-	examples/make_hello_sc \
+  examples/make_hello_sc \
 
 EXAMPLES = $(EXAMPLES_FIRST) $(filter-out $(EXAMPLES_FIRST), $(sort $(wildcard examples/*)))
 
 # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff
 # No verilator_ccache_report.1, verilator_difftree.1 as those are not bin/ installed
 VL_INST_MAN_FILES = \
-	verilator.1 \
+  verilator.1 \
-	verilator_coverage.1 \
+  verilator_coverage.1 \
-	verilator_gantt.1 \
+  verilator_gantt.1 \
-	verilator_profcfunc.1 \
+  verilator_profcfunc.1 \
 
 default: all
 all: all_nomsg msg_test
 all_nomsg: verilator_exe $(VL_INST_MAN_FILES)
 
-.PHONY:verilator_exe
+.PHONY: verilator_exe
-.PHONY:verilator_bin$(EXEEXT)
+.PHONY: verilator_bin$(EXEEXT)
-.PHONY:verilator_bin_dbg$(EXEEXT)
+.PHONY: verilator_bin_dbg$(EXEEXT)
-.PHONY:verilator_coverage_bin_dbg$(EXEEXT)
+.PHONY: verilator_coverage_bin_dbg$(EXEEXT)
 verilator_exe verilator_bin$(EXEEXT) verilator_bin_dbg$(EXEEXT) verilator_coverage_bin_dbg$(EXEEXT):
 	@echo ------------------------------------------------------------
 	@echo "making verilator in src"
 	$(MAKE) -C src $(OBJCACHE_JOBS)
 
-.PHONY:msg_test
+######################################################################
+# Tests
+
+.PHONY: msg_test
 msg_test: all_nomsg
 	@echo "Build complete!"
 	@echo
@@ -155,7 +161,7 @@ msg_test: all_nomsg
 .PHONY: test
 ifeq ($(CFG_WITH_LONGTESTS),yes)  # Local... Else don't burden users
 test: smoke-test test_regress
-# examples is part of test_regress's test_regress/t/t_a2_examples.pl
+# examples is part of test_regress's test_regress/t/t_a2_examples.py
 # (because that allows it to run in parallel with other test_regress's)
 else
 test: smoke-test examples
@@ -167,19 +173,26 @@ endif
 	@echo
 
 smoke-test: all_nomsg
-	test_regress/t/t_a1_first_cc.pl
+	test_regress/t/t_a1_first_cc.py
-	test_regress/t/t_a2_first_sc.pl
+	test_regress/t/t_a2_first_sc.py
 
 test_regress: all_nomsg
 	$(MAKE) -C test_regress
 
+.PHONY: test-snap test-diff
+test-snap test-diff:
+	$(MAKE) -C test_regress $@
+
 examples: all_nomsg
 	for p in $(EXAMPLES) ; do \
 	  $(MAKE) -C $$p VERILATOR_ROOT=`pwd` || exit 10; \
 	done
 
+######################################################################
+# Docs
+
 .PHONY: docs
-docs: info
+docs: info $(VL_INST_MAN_FILES)
 
 info: $(INFOS)
 
@@ -188,7 +201,8 @@ verilator.1: ${srcdir}/bin/verilator
 verilator_coverage.1: ${srcdir}/bin/verilator_coverage
 	pod2man $< $@
 %.1: ${srcdir}/bin/%
-	help2man --no-info --no-discard-stderr --version-string=- $< -o $@
+	help2man --no-info --no-discard-stderr --version-string=- \
+		-n "$(shell $< --help | head -n 3 | tail -n 1)" $< -o $@
 
 .PHONY: verilator.html
 verilator.html:
@@ -199,42 +213,93 @@ verilator.html:
 verilator.pdf: Makefile
 	$(MAKE) -C docs verilator.pdf
 
-# See uninstall also - don't put wildcards in this variable, it might uninstall other stuff
+TAGFILES = ${srcdir}/*/*.cpp ${srcdir}/*/*.h ${srcdir}/*/*.in \
-VL_INST_BIN_FILES = verilator verilator_bin$(EXEEXT) verilator_bin_dbg$(EXEEXT) verilator_coverage_bin_dbg$(EXEEXT) \
+  ${srcdir}/*.in ${srcdir}/*.pod
-	verilator_ccache_report verilator_coverage verilator_difftree verilator_gantt verilator_includer verilator_profcfunc
+
-# Some scripts go into both the search path and pkgdatadir,
+TAGS: $(TAGFILES)
-# so they can be found by the user, and under $VERILATOR_ROOT.
+	etags $(TAGFILES)
+
+.PHONY: doxygen
+
+doxygen:
+	$(MAKE) -C docs doxygen
+
+.PHONY: spelling
+spelling:
+	$(MAKE) -C docs spelling
+
+######################################################################
+# Install
+
+# Public executables intended to be invoked directly by the user
+# Don't put wildcards in these variables, it might cause an uninstall of other stuff
+VL_INST_PUBLIC_SCRIPT_FILES = \
+  verilator \
+  verilator_coverage \
+  verilator_gantt \
+  verilator_profcfunc \
+
+VL_INST_PUBLIC_BIN_FILES = \
+  verilator_bin$(EXEEXT) \
+  verilator_bin_dbg$(EXEEXT) \
+  verilator_coverage_bin_dbg$(EXEEXT) \
+
+# Private executabels intended to be invoked by internals
+# Don't put wildcards in these variables, it might cause an uninstall of other stuff
+VL_INST_PRIVATE_SCRIPT_FILES = \
+  verilator_ccache_report \
+  verilator_includer \
 
 VL_INST_INC_BLDDIR_FILES = \
-	include/verilated_config.h \
+  include/verilated_config.h \
-	include/verilated.mk \
+  include/verilated.mk \
 
 # Files under srcdir, instead of build time
 VL_INST_INC_SRCDIR_FILES = \
-	include/*.[chv]* \
+  include/*.[chv]* \
-	include/*.sv \
+  include/*.vlt \
-	include/gtkwave/*.[chv]* \
+  include/*.sv \
-	include/vltstd/*.[chv]* \
+  include/gtkwave/*.[chv]* \
+  include/vltstd/*.[chv]* \
 
 VL_INST_DATA_SRCDIR_FILES = \
-	examples/*/*.[chv]* \
+  examples/*/*.[chv]* \
-	examples/*/CMakeLists.txt \
+  examples/*/CMakeLists.txt \
-	examples/*/Makefile* \
+  examples/*/Makefile* \
-	examples/*/vl_* \
+  examples/*/vl_* \
 
-installbin:
+mkbindirs:
-	$(MKINSTALLDIRS) $(DESTDIR)$(bindir)
-	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator $(DESTDIR)$(bindir)/verilator )
-	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_coverage $(DESTDIR)$(bindir)/verilator_coverage )
-	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_gantt $(DESTDIR)$(bindir)/verilator_gantt )
-	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_profcfunc $(DESTDIR)$(bindir)/verilator_profcfunc )
-	( cd bin ; $(INSTALL_PROGRAM) verilator_bin$(EXEEXT) $(DESTDIR)$(bindir)/verilator_bin$(EXEEXT) )
-	( cd bin ; $(INSTALL_PROGRAM) verilator_bin_dbg$(EXEEXT) $(DESTDIR)$(bindir)/verilator_bin_dbg$(EXEEXT) )
-	( cd bin ; $(INSTALL_PROGRAM) verilator_coverage_bin_dbg$(EXEEXT) $(DESTDIR)$(bindir)/verilator_coverage_bin_dbg$(EXEEXT) )
 	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/bin
-	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_includer $(DESTDIR)$(pkgdatadir)/bin/verilator_includer )
+	$(MKINSTALLDIRS) $(DESTDIR)$(bindir)
-	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_ccache_report $(DESTDIR)$(pkgdatadir)/bin/verilator_ccache_report )
+
-	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_difftree $(DESTDIR)$(pkgdatadir)/bin/verilator_difftree )
+installbin: | mkbindirs
+	cd $(srcdir)/bin; \
+	for p in $(VL_INST_PUBLIC_SCRIPT_FILES) ; do \
+	  $(INSTALL_PROGRAM) $$p $(DESTDIR)$(bindir)/$$p; \
+	done
+	perl -p -i -e 'use File::Spec;' \
+	           -e' $$path = File::Spec->abs2rel("$(realpath $(DESTDIR)$(pkgdatadir))", "$(realpath $(DESTDIR)$(bindir))");' \
+	           -e 's/my \$$verilator_pkgdatadir_relpath = .*/my \$$verilator_pkgdatadir_relpath = "$$path";/g' \
+	           -- "$(DESTDIR)/$(bindir)/verilator"
+	cd bin; \
+	for p in $(VL_INST_PUBLIC_BIN_FILES) ; do \
+	  $(INSTALL_PROGRAM) $$p $(DESTDIR)$(bindir)/$$p; \
+	done
+	cd $(srcdir)/bin; \
+	for p in $(VL_INST_PRIVATE_SCRIPT_FILES) ; do \
+	  $(INSTALL_PROGRAM) $$p $(DESTDIR)$(pkgdatadir)/bin/$$p; \
+	done
+
+installredirect: installbin | mkbindirs
+	cp ${srcdir}/bin/redirect ${srcdir}/bin/redirect.tmp
+	perl -p -i -e 'use File::Spec;' \
+	           -e' $$path = File::Spec->abs2rel("$(realpath $(DESTDIR)$(bindir))", "$(realpath $(DESTDIR)$(pkgdatadir)/bin)");' \
+	           -e 's/RELPATH.*/"$$path";/g' -- "${srcdir}/bin/redirect.tmp"
+	cd $(srcdir)/bin; \
+	for p in $(VL_INST_PUBLIC_SCRIPT_FILES) $(VL_INST_PUBLIC_BIN_FILES) ; do \
+	  $(INSTALL_PROGRAM) redirect.tmp $(DESTDIR)$(pkgdatadir)/bin/$$p; \
+	done
+	rm ${srcdir}/bin/redirect.tmp
 
 # Man files can either be part of the original kit, or built in current directory
 # So important we use $^ so VPATH is searched
@@ -265,7 +330,7 @@ installdata:
 	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_tracing_c
 	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_tracing_sc
 	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_protect_lib
-	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/xml_py
+	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/json_py
 	cd $(srcdir) \
 	; for p in $(VL_INST_DATA_SRCDIR_FILES) ; do \
 	  $(INSTALL_DATA) $$p $(DESTDIR)$(pkgdatadir)/$$p; \
@@ -277,8 +342,11 @@ installdata:
 
 # We don't trust rm -rf, so rmdir instead as it will fail if user put in other files
 uninstall:
-	-cd $(DESTDIR)$(bindir) && rm -f $(VL_INST_BIN_FILES)
+	-cd $(DESTDIR)$(bindir) && rm -f $(VL_INST_PUBLIC_SCRIPT_FILES)
-	-cd $(DESTDIR)$(pkgdatadir)/bin && rm -f $(VL_INST_BIN_FILES)
+	-cd $(DESTDIR)$(bindir) && rm -f $(VL_INST_PUBLIC_BIN_FILES)
+	-cd $(DESTDIR)$(pkgdatadir)/bin && rm -f $(VL_INST_PUBLIC_SCRIPT_FILES)
+	-cd $(DESTDIR)$(pkgdatadir)/bin && rm -f $(VL_INST_PUBLIC_BIN_FILES)
+	-cd $(DESTDIR)$(pkgdatadir)/bin && rm -f $(VL_INST_PRIVATE_SCRIPT_FILES)
 	-cd $(DESTDIR)$(mandir)/man1 && rm -f $(VL_INST_MAN_FILES)
 	-cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_INC_BLDDIR_FILES)
 	-cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_INC_SRCDIR_FILES)
@@ -301,65 +369,78 @@ uninstall:
 	-rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_tracing_c
 	-rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_tracing_sc
 	-rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_protect_lib
-	-rmdir $(DESTDIR)$(pkgdatadir)/examples/xml_py
+	-rmdir $(DESTDIR)$(pkgdatadir)/examples/json_py
 	-rmdir $(DESTDIR)$(pkgdatadir)/examples
 	-rmdir $(DESTDIR)$(pkgdatadir)
 	-rmdir $(DESTDIR)$(pkgconfigdir)
 
 install: all_nomsg install-all
-install-all: installbin installman installdata install-msg
+install-all: installbin installredirect installman installdata install-msg
 
 install-here: installman info
 
-# Use --xml flag to see the cppcheck code to use for suppression
+install-msg:
-CPPCHECK1_CPP = $(wildcard $(srcdir)/include/*.cpp)
+	@echo
-CPPCHECK2_CPP = $(wildcard $(srcdir)/examples/*/*.cpp)
+	@echo "Installed binaries to $(DESTDIR)$(bindir)/verilator"
-CPPCHECK3_CPP = $(wildcard $(srcdir)/src/Vlc*.cpp)
+	@echo "Installed man to $(DESTDIR)$(mandir)/man1"
-CPPCHECK4_CPP = $(wildcard $(srcdir)/src/V3[A-D]*.cpp $(srcdir)/src/Verilator*.cpp)
+	@echo "Installed examples to $(DESTDIR)$(pkgdatadir)/examples"
-CPPCHECK5_CPP = $(wildcard $(srcdir)/src/V3[E-I]*.cpp)
+	@echo
-CPPCHECK6_CPP = $(wildcard $(srcdir)/src/V3[P-Z]*.cpp)
+	@echo "For documentation see 'man verilator' or 'verilator --help'"
-CPPCHECK7_CPP = $(wildcard $(srcdir)/src/V3[L-R]*.cpp)
+	@echo "For forums and to report bugs see https://verilator.org"
-CPPCHECK8_CPP = $(wildcard $(srcdir)/src/V3[S-Z]*.cpp)
+	@echo
-CHECK_CPP = $(CPPCHECK1_CPP) $(CPPCHECK2_CPP) $(CPPCHECK3_CPP) $(CPPCHECK4_CPP) \
-	$(CPPCHECK5_CPP) $(CPPCHECK6_CPP) $(CPPCHECK7_CPP) $(CPPCHECK8_CPP)
-CHECK_H = $(wildcard \
-	$(srcdir)/include/*.h \
-	$(srcdir)/src/*.h )
-CHECK_YL = $(wildcard \
-	$(srcdir)/src/*.y \
-	$(srcdir)/src/*.l )
-CPPCHECK = src/cppcheck_filtered cppcheck
-CPPCHECK_FLAGS = --enable=all --inline-suppr \
-	--suppress=cstyleCast --suppress=useInitializationList \
-	--suppress=nullPointer --suppress=nullPointerRedundantCheck --suppress=ctunullpointer \
-	--suppress=unusedFunction --suppress=unusedScopedObject \
-	--suppress=useStlAlgorithm
-CPPCHECK_FLAGS += --xml
-CPPCHECK_DEP = $(subst .cpp,.cppcheck,$(CHECK_CPP))
-CPPCHECK_INC = -I$(srcdir)/include -I$(srcdir)/src/obj_dbg -I$(srcdir)/src
 
-cppcheck: cppcheck-1 cppcheck-2 cppcheck-3 cppcheck-4 cppcheck-5 cppcheck-6 cppcheck-7 cppcheck-8
+######################################################################
-cppcheck-1:
+# Format/Lint
-	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK1_CPP)
+
-cppcheck-2:
+CPPCHECK_VERILATOR_CPP = $(wildcard $(srcdir)/src/V3*.cpp $(srcdir)/src/Verilator*.cpp)
-	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK2_CPP)
+CPPCHECK_RUNTIME_CPP = $(wildcard $(srcdir)/include/*.cpp)
-cppcheck-3:
+CPPCHECK_VLC_CPP = $(wildcard $(srcdir)/src/Vlc*.cpp)
-	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK3_CPP)
+CPPCHECK_EXAMPLES_CPP = $(wildcard $(srcdir)/examples/*/*.cpp)
-cppcheck-4:
+CHECK_CPP = $(CPPCHECK_VERILATOR_CPP) $(CPPCHECK_RUNTIME_CPP) $(CPPCHECK_VLC_CPP) $(CPPCHECK_EXAMPLES_CPP)
-	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK4_CPP)
+CHECK_H = $(wildcard \
-cppcheck-5:
+  $(srcdir)/include/*.h \
-	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK5_CPP)
+  $(srcdir)/src/*.h )
-cppcheck-6:
+CHECK_YL = $(wildcard \
-	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK6_CPP)
+  $(srcdir)/src/*.y \
-cppcheck-7:
+  $(srcdir)/src/*.l )
-	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK7_CPP)
+CPPCHECK = cppcheck
-cppcheck-8:
+CPPCHECK_JOBS = $(shell nproc)
-	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK8_CPP)
+CPPCHECK_CACHE = $(srcdir)/src/obj_dbg/cppcheck-cache
+CPPCHECK_FLAGS = --enable=all
+CPPCHECK_FLAGS += --inline-suppr
+CPPCHECK_FLAGS += --suppressions-list=$(srcdir)/src/cppcheck-suppressions.txt
+CPPCHECK_FLAGS += --cppcheck-build-dir=$(CPPCHECK_CACHE)
+CPPCHECK_FLAGS += -DVL_DEBUG=1 -DVL_CPPCHECK=1 -DINFILTER_PIPE=1 -D__GNUC__=1
+CPPCHECK_FLAGS += -j$(CPPCHECK_JOBS)
+CPPCHECK_INC = -I$(srcdir)/include
+CPPCHECK_INC += -I$(srcdir)/include/gtkwave
+CPPCHECK_INC += -I$(srcdir)/include/vltstd
+CPPCHECK_INC += -I$(srcdir)/src/obj_dbg
+CPPCHECK_INC += -I$(srcdir)/src
+
+$(CPPCHECK_CACHE): $(CHECK_CPP) $(CHECK_H) $(CHECK_YL)
+	/bin/rm -rf $@
+	/bin/mkdir -p $@
+
+cppcheck-verilator: | $(CPPCHECK_CACHE)
+	$(CPPCHECK) $(CPPCHECK_FLAGS) $(CPPCHECK_INC) $(CPPCHECK_VERILATOR_CPP)
+cppcheck-runtime: | $(CPPCHECK_CACHE)
+	$(CPPCHECK) $(CPPCHECK_FLAGS) $(CPPCHECK_INC) $(CPPCHECK_RUNTIME_CPP)
+cppcheck-vlc: | $(CPPCHECK_CACHE)
+	$(CPPCHECK) $(CPPCHECK_FLAGS) $(CPPCHECK_INC) $(CPPCHECK_VLC_CPP)
+cppcheck-examples: | $(CPPCHECK_CACHE)
+	$(CPPCHECK) $(CPPCHECK_FLAGS) $(CPPCHECK_INC) $(CPPCHECK_EXAMPLES_CPP)
+
+cppcheck:
+	$(MAKE) cppcheck-vlc
+	$(MAKE) cppcheck-examples
+	$(MAKE) cppcheck-runtime
+	$(MAKE) cppcheck-verilator
 
 CLANGTIDY = clang-tidy
 CLANGTIDY_FLAGS = -config='' \
-	-header-filter='.*' \
+  -header-filter='.*' \
-	-checks='-fuchsia-*,-cppcoreguidelines-avoid-c-arrays,-cppcoreguidelines-init-variables,-cppcoreguidelines-avoid-goto,-modernize-avoid-c-arrays,-readability-magic-numbers,-readability-simplify-boolean-expr,-cppcoreguidelines-macro-usage' \
+  -checks='-fuchsia-*,-cppcoreguidelines-avoid-c-arrays,-cppcoreguidelines-init-variables,-cppcoreguidelines-avoid-goto,-modernize-avoid-c-arrays,-readability-magic-numbers,-readability-simplify-boolean-expr,-cppcoreguidelines-macro-usage' \
 
 CLANGTIDY_DEP = $(subst .cpp,.cpp.tidy,$(CHECK_CPP))
 CLANGTIDY_DEFS = -DVL_DEBUG=1 -DVL_CPPCHECK=1
@@ -378,74 +459,124 @@ analyzer-include:
 	-rm -rf examples/*/obj*
 	scan-build $(MAKE) -k examples
 
-format: clang-format yapf format-pl-exec
+format:
+	$(MAKE) -j 5 format-c format-cmake format-exec format-py
 
-CLANGFORMAT = clang-format-14
+CLANGFORMAT = clang-format-18
 CLANGFORMAT_FLAGS = -i
 CLANGFORMAT_FILES = $(CHECK_CPP) $(CHECK_H) $(CHECK_YL) test_regress/t/*.c* test_regress/t/*.h
 
-clang-format:
+format-c clang-format:
-	@$(CLANGFORMAT) --version | egrep 14.0 > /dev/null \
+	$(CLANGFORMAT) --version
-		|| echo "*** You are not using clang-format-14, indents may differ from master's ***"
+	@$(CLANGFORMAT) --version | fgrep 'version 18' > /dev/null \
+	|| echo "*** You are not using clang-format-18, indents may differ from master's ***"
 	$(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CLANGFORMAT_FILES)
 
-PY_PROGRAMS = \
+YAMLFIX = YAMLFIX_WHITELINES=1 YAMLFIX_LINE_LENGTH=130 YAMLFIX_preserve_quotes=true yamlfix
-	bin/verilator_ccache_report \
-	bin/verilator_difftree \
-	bin/verilator_gantt \
-	bin/verilator_includer \
-	bin/verilator_profcfunc \
-	examples/xml_py/vl_file_copy \
-	examples/xml_py/vl_hier_graph \
-	docs/guide/conf.py \
-	docs/bin/vl_sphinx_extract \
-	docs/bin/vl_sphinx_fix \
-	src/astgen \
-	src/bisonpre \
-	src/config_rev \
-	src/cppcheck_filtered \
-	src/flexfix \
-	src/vlcovgen \
-	test_regress/t/*.pf \
-	nodist/clang_check_attributes \
-	nodist/code_coverage \
-	nodist/dot_importer \
-	nodist/fuzzer/actual_fail \
-	nodist/fuzzer/generate_dictionary \
-	nodist/install_test \
 
+yamlfix:
+	$(YAMLFIX) .
+
+# CMake files
+CMAKE_FILES = \
+  CMakeLists.txt \
+  examples/*/CMakeLists.txt \
+  src/CMakeLists.txt \
+  test_regress/CMakeLists.txt \
+  *.cmake.in \
+
+# Makefiles
+MAKE_FILES = \
+  Makefile*.in \
+  docs/Makefile* \
+  include/verilated.mk.in \
+  examples/*/Makefile* \
+  src/Makefile*.in \
+  test_regress/Makefile* \
+
+# Python programs, subject to format and lint
+PY_PROGRAMS = \
+  bin/verilator_ccache_report \
+  bin/verilator_difftree \
+  bin/verilator_gantt \
+  bin/verilator_includer \
+  bin/verilator_profcfunc \
+  examples/json_py/vl_file_copy \
+  examples/json_py/vl_hier_graph \
+  docs/guide/conf.py \
+  docs/bin/vl_sphinx_extract \
+  docs/bin/vl_sphinx_fix \
+  src/astgen \
+  src/bisonpre \
+  src/config_rev \
+  src/flexfix \
+  src/vlcovgen \
+  src/.gdbinit.py \
+  test_regress/*.py \
+  test_regress/t/*.pf \
+  nodist/clang_check_attributes \
+  nodist/code_coverage \
+  nodist/dot_importer \
+  nodist/fuzzer/actual_fail \
+  nodist/fuzzer/generate_dictionary \
+  nodist/install_test \
+  nodist/log_changes \
+
+# Python files, subject to format but not lint
 PY_FILES = \
-	$(PY_PROGRAMS) \
+  $(PY_PROGRAMS) \
-	nodist/code_coverage.dat \
+  nodist/code_coverage.dat \
+  test_regress/t/*.py \
+
+# Python files, test_regress tests
+PY_TEST_FILES = test_regress/t/*.py
 
 YAPF = yapf3
-YAPF_FLAGS = -i
+YAPF_FLAGS = -i --parallel
 
-yapf:
+format-py yapf:
+	$(YAPF) --version
 	$(YAPF) $(YAPF_FLAGS) $(PY_FILES)
 
+GERSEMI = gersemi
+GERSEMI_FLAGS = -i --no-warn-about-unknown-commands
+
+format-cmake:
+	$(GERSEMI) $(GERSEMI_FLAGS) $(CMAKE_FILES)
+
+MBAKE = mbake
+MBAKE_FLAGS = format --config ./.bake.toml
+
+format-make:
+	$(MBAKE) $(MBAKE_FLAGS) $(MAKE_FILES)
+
+format-yaml: yamlfix
+
 PYLINT = pylint
-PYLINT_FLAGS = --score=n --disable=R0801
+PYLINT_FLAGS = --recursive=n --score=n --disable=R0801
+PYLINT_TEST_FLAGS = $(PYLINT_FLAGS) --disable=C0103,C0114,C0116,C0209,C0411,C0413,C0301,R0801,R0912,R0915,R0916,R1702,W0511,W0621
 
 RUFF = ruff
 RUFF_FLAGS = check --ignore=E402,E501,E701
 
+# "make -k" so can see all tool result errors
 lint-py:
-	-$(PYLINT) $(PYLINT_FLAGS) $(PY_PROGRAMS)
+	$(MAKE) -k lint-py-pylint lint-py-pylint-tests lint-py-ruff
-	-$(RUFF) $(RUFF_FLAGS) $(PY_PROGRAMS)
 
-format-pl-exec:
+lint-py-pylint:
-	-chmod a+x test_regress/t/*.pl
+	$(PYLINT) $(PYLINT_FLAGS) $(PY_PROGRAMS)
 
-install-msg:
+lint-py-pylint-tests:
-	@echo
+	$(PYLINT) $(PYLINT_TEST_FLAGS) $(PY_TEST_FILES) | $(PYTHON3) nodist/lint_py_test_filter
-	@echo "Installed binaries to $(DESTDIR)$(bindir)/verilator"
+
-	@echo "Installed man to $(DESTDIR)$(mandir)/man1"
+lint-py-ruff:
-	@echo "Installed examples to $(DESTDIR)$(pkgdatadir)/examples"
+	$(RUFF) $(RUFF_FLAGS) $(PY_PROGRAMS)
-	@echo
+
-	@echo "For documentation see 'man verilator' or 'verilator --help'"
+format-exec:
-	@echo "For forums and to report bugs see https://verilator.org"
+	-chmod a+x test_regress/t/*.py
-	@echo
+
+######################################################################
+# Configure
 
 IN_WILD := ${srcdir}/*.in ${srcdir}/*/*.in
 
@@ -466,6 +597,9 @@ else
 	autoconf
 endif
 
+######################################################################
+# Clean
+
 maintainer-clean::
 	@echo "This command is intended for maintainers to use;"
 	@echo "rebuilding the deleted files requires autoconf."
@@ -485,6 +619,8 @@ clean mostlyclean distclean maintainer-clean::
 	rm -f *.tex
 	rm -rf examples/*/obj_dir* examples/*/logs
 	rm -rf test_*/obj_dir
+	rm -rf src/*.tidy include/*.tidy examples/*/*.tidy
+	rm -rf .ruff_cache
 	rm -rf nodist/fuzzer/dictionary
 	rm -rf nodist/obj_dir
 	rm -rf verilator.txt
@@ -496,17 +632,6 @@ distclean maintainer-clean::
 	rm -f bin/verilator_bin* bin/verilator_coverage_bin*
 	rm -f include/verilated.mk include/verilated_config.h
 
-TAGFILES=${srcdir}/*/*.cpp ${srcdir}/*/*.h ${srcdir}/*/*.in \
-	${srcdir}/*.in ${srcdir}/*.pod
-
-TAGS: $(TAGFILES)
-	etags $(TAGFILES)
-
-.PHONY: doxygen
-
-doxygen:
-	$(MAKE) -C docs doxygen
-
 ######################################################################
 # Distributions
 

README.rst

@@ -1,22 +1,22 @@
 .. Github doesn't render images unless absolute URL
 .. Do not know of a conditional tag, "only: github" nor "github display" works
 
-.. image:: https://img.shields.io/badge/Website-Verilator.org-181717.svg
+|badge1| |badge2| |badge3| |badge4| |badge5| |badge7| |badge8|
+
+.. |badge1| image:: https://img.shields.io/badge/Website-Verilator.org-181717.svg
     :target: https://verilator.org
-.. image:: https://img.shields.io/badge/License-LGPL%20v3-blue.svg
+.. |badge2| image:: https://img.shields.io/badge/License-LGPL%20v3-blue.svg
     :target: https://www.gnu.org/licenses/lgpl-3.0
-.. image:: https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg
+.. |badge3| image:: https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg
     :target: https://opensource.org/licenses/Artistic-2.0
-.. image:: https://repology.org/badge/tiny-repos/verilator.svg?header=distro%20packages
+.. |badge4| image:: https://repology.org/badge/tiny-repos/verilator.svg?header=distro%20packages
     :target: https://repology.org/project/verilator/versions
-.. image:: https://img.shields.io/docker/pulls/verilator/verilator
+.. |badge5| image:: https://img.shields.io/docker/pulls/verilator/verilator
     :target: https://hub.docker.com/r/verilator/verilator
-.. image:: https://api.codacy.com/project/badge/Grade/fa78caa433c84a4ab9049c43e9debc6f
+.. |badge7| image:: https://github.com/verilator/verilator/workflows/build/badge.svg
-    :target: https://www.codacy.com/gh/verilator/verilator
-.. image:: https://codecov.io/gh/verilator/verilator/branch/master/graph/badge.svg
-    :target: https://codecov.io/gh/verilator/verilator
-.. image:: https://github.com/verilator/verilator/workflows/build/badge.svg
     :target: https://github.com/verilator/verilator/actions?query=workflow%3Abuild
+.. |badge8| image:: https://img.shields.io/github/actions/workflow/status/verilator/verilator/rtlmeter.yml?branch=master&event=schedule&label=benchmarks
+    :target: https://verilator.github.io/verilator-rtlmeter-results
 
 
 Welcome to Verilator
@@ -66,9 +66,9 @@ executable performs the design simulation. Verilator also supports linking
 Verilated generated libraries, optionally encrypted, into other simulators.
 
 Verilator may not be the best choice if you are expecting a full-featured
-replacement for a closed-source Verilog simulator, needs SDF annotation,
+replacement for a closed-source Verilog simulator, need SDF annotation,
 mixed-signal simulation, or are doing a quick class project (we recommend
-`Icarus Verilog`_ for classwork.)  However, if you are looking for a path
+`Icarus Verilog`_ for classwork).  However, if you are looking for a path
 to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of
 designs, Verilator is the tool for you.
 
@@ -80,17 +80,16 @@ Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather,
 Verilator compiles your code into a much faster optimized and optionally
 thread-partitioned model, which is in turn wrapped inside a C++/SystemC
 module. The results are a compiled Verilog model that executes even on a
-single-thread over 10x faster than standalone SystemC, and on a single
+single thread over 10x faster than standalone SystemC, and on a single
 thread is about 100 times faster than interpreted Verilog simulators such
 as `Icarus Verilog`_. Another 2-10x speedup might be gained from
 multithreading (yielding 200-1000x total over interpreted simulators).
 
-Verilator has typically similar or better performance versus the
+Verilator has typically similar or better performance versus closed-source
-closed-source Verilog simulators (e.g., Carbon Design Systems Carbonator,
+Verilog simulators (e.g., Aldec Riviera-Pro, Cadence Incisive/NC-Verilog,
-Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and
+Mentor ModelSim/Questa, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But,
-Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on
+Verilator is open-sourced, so you can spend on computes rather than
-computes rather than licenses. Thus, Verilator gives you the best
+licenses. Thus, Verilator gives you the best simulation cycles/dollar.
-simulation cycles/dollar.
 
 
 Installation & Documentation
@@ -132,17 +131,17 @@ organizations; please see `Verilator Commercial Support
 Related Projects
 ================
 
-- `GTKwave <http://gtkwave.sourceforge.net/>`_ - Waveform viewer for
+- `GTKwave <https://gtkwave.sourceforge.net/>`_ - Waveform viewer for
   Verilator traces.
 
-- `Icarus Verilog`_ - Icarus is a full-featured interpreted Verilog
+- `Icarus Verilog`_ - Icarus is a highly-featured interpreted Verilog
   simulator. If Verilator does not support your needs, perhaps Icarus may.
 
 
 Open License
 ============
 
-Verilator is Copyright 2003-2023 by Wilson Snyder. (Report bugs to
+Verilator is Copyright 2003-2025 by Wilson Snyder. (Report bugs to
 `Verilator Issues <https://verilator.org/issues>`_.)
 
 Verilator is free software; you can redistribute it and/or modify it under
@@ -150,7 +149,7 @@ the terms of either the GNU Lesser General Public License Version 3 or the
 Perl Artistic License Version 2.0. See the documentation for more details.
 
 .. _CHIPS Alliance: https://chipsalliance.org
-.. _Icarus Verilog: http://iverilog.icarus.com
+.. _Icarus Verilog: https://steveicarus.github.io/iverilog
 .. _Linux Foundation: https://www.linuxfoundation.org
 .. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png
 .. |verilator multithreaded performance| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png

bin/redirect

@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+######################################################################
+#
+# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+#
+######################################################################
+
+require 5.006_001;
+use warnings;
+use FindBin qw($RealBin $RealScript);
+use strict;
+
+my $relpath = RELPATH;  # Substituted during Verilator 'make install'
+
+unshift @ARGV, $RealScript;
+
+exec { "$RealBin/$relpath/$RealScript" } @ARGV;
+die "%Error: Exec failed,";

bin/verilator

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -15,6 +15,7 @@ use Getopt::Long;
 use FindBin qw($RealBin $RealScript);
 use IO::File;
 use Pod::Usage;
+use Cwd qw(realpath);
 
 use strict;
 use vars qw($Debug @Opt_Verilator_Sw);
@@ -32,6 +33,7 @@ my $opt_rr;
 my $opt_gdbbt;
 my $opt_quiet_exit;
 my $opt_unlimited_stack = 1;
+my $opt_valgrind;
 
 # No arguments can't do anything useful.  Give help
 if ($#ARGV < 0) {
@@ -56,15 +58,31 @@ if (! GetOptions(
           # Switches
           "gdb!"             => \$opt_gdb,
           "gdbbt!"           => \$opt_gdbbt,
+          "quiet!"           => \$opt_quiet_exit,  # As -quiet implies -quiet-exit
           "quiet-exit!"      => \$opt_quiet_exit,
           "rr!"              => \$opt_rr,
           "unlimited-stack!" => \$opt_unlimited_stack,
+          "valgrind!"        => \$opt_valgrind,
           # Additional parameters
           "<>"               => sub {},      # Ignored
     )) {
     pod2usage(-exitstatus => 2, -verbose => 0);
 }
 
+# WARNING: $verilator_pkgdatadir_relpath is substituted during Verilator 'make install'
+my $verilator_pkgdatadir_relpath = "..";
+my $verilator_root = realpath("$RealBin/$verilator_pkgdatadir_relpath");
+if (defined $ENV{VERILATOR_ROOT}) {
+    if ((!-d $ENV{VERILATOR_ROOT}) || $verilator_root ne realpath($ENV{VERILATOR_ROOT})) {
+        warn "%Error: verilator: VERILATOR_ROOT is set to inconsistent path. Suggest leaving it unset.\n";
+        warn "%Error: VERILATOR_ROOT=$ENV{VERILATOR_ROOT}\n";
+        exit 1;
+    }
+} else {
+    print "export VERILATOR_ROOT='$verilator_root'\n" if $Debug;
+    $ENV{VERILATOR_ROOT} = $verilator_root;
+}
+
 if ($opt_gdbbt && !gdb_works()) {
     warn "-Info: --gdbbt ignored: gdb doesn't seem to be working\n" if $Debug;
     $opt_gdbbt = 0;
@@ -109,6 +127,18 @@ if ($opt_gdb) {
          . " -ex \"run " . join(' ', @quoted_sw)."\""
          . " -ex 'set width 0'"
          . " -ex 'bt' -ex 'quit'");
+} elsif ($opt_valgrind) {
+    # Run under valgrind
+    my $valgrind_bin = ($ENV{VERILATOR_VALGRIND} || "valgrind --error-exitcode=1 --max-stackframe=2815880"
+        # Magic number suggested by Valgrind, may need to be increased in future
+        # if you get warnings. See: https://valgrind.org/docs/manual/manual-core.html#opt.max-stackframe
+        );
+
+    run (ulimit_stack_unlimited()
+         . aslr_off()
+         . $valgrind_bin
+         . " " . verilator_bin()
+         . " " . join(' ', @quoted_sw));
 } elsif ($Debug) {
     # Debug
     run(ulimit_stack_unlimited()
@@ -137,30 +167,13 @@ sub debug {
 # Builds
 
 sub verilator_bin {
-    my $bin = "";
-    # Use VERILATOR_ROOT if defined, else assume verilator_bin is in the search path
     my $basename = ($ENV{VERILATOR_BIN}
                     || ($Debug ? "verilator_bin_dbg" : "verilator_bin"));
-    if (defined($ENV{VERILATOR_ROOT})) {
+    if (-x "$RealBin/$basename" || -x "$RealBin/$basename.exe") {
-        my $dir = $ENV{VERILATOR_ROOT};
+        return "$RealBin/$basename";
-        if (-x "$dir/bin/$basename"
-            || -x "$dir/bin/$basename.exe") {  # From a "make install" into VERILATOR_ROOT
-            $bin = "$dir/bin/$basename";
-        } else {
-            $bin = "$dir/$basename";  # From pointing to kit directory
-        }
     } else {
-        if (-x "$RealBin/$basename"
+        return $basename;  # Find in PATH
-            || -x "$RealBin/$basename.exe") {
-            $bin = "$RealBin/$basename";  # From path/to/verilator with verilator_bin installed
-        } else {
-            $bin = $basename;  # Find in PATH
-        }
-        # Note we don't look under bin/$basename which would be right if running
-        # in the kit dir. Running that would likely break, since
-        # VERILATOR_ROOT wouldn't be set and Verilator won't find internal files.
     }
-    return $bin;
 }
 
 #######################################################################
@@ -243,7 +256,7 @@ sub sh_escape {
     # This is similar to quotemeta() but less aggressive.
     # There's no need to escape hyphens, periods, or forward slashes
     # for the shell as these have no special meaning to the shell.
-    $arg =~ s/([^0-9a-zA-Z_\-\+\=\.\/])/\\$1/g;
+    $arg =~ s/([^0-9a-zA-Z_\-\+\=\.\/:])/\\$1/g;
     return $arg;
 }
 
@@ -256,8 +269,7 @@ __END__
 
 =head1 NAME
 
-Verilator - Translate and simulate SystemVerilog code using C++/SystemC
+Verilator - Lint, compile and simulate SystemVerilog code using C++/SystemC
-
 
 =head1 SYNOPSIS
 
@@ -298,7 +310,9 @@ detailed descriptions of these arguments.
      +1800-2009ext+<ext>        Use SystemVerilog 2009 with file extension <ext>
      +1800-2012ext+<ext>        Use SystemVerilog 2012 with file extension <ext>
      +1800-2017ext+<ext>        Use SystemVerilog 2017 with file extension <ext>
-    --assert                    Enable all assertions
+     +1800-2023ext+<ext>        Use SystemVerilog 2023 with file extension <ext>
+    --no-assert                 Disable all assertions
+    --no-assert-case            Disable unique/unique0/priority-case assertions
     --autoflush                 Flush streams after all $displays
     --bbox-sys                  Blackbox unknown $system calls
     --bbox-unsup                Blackbox unsupported language features
@@ -307,13 +321,15 @@ detailed descriptions of these arguments.
     --build-dep-bin <filename>  Override build dependency Verilator binary
     --build-jobs <jobs>         Parallelism for --build
     --cc                        Create C++ output
-    --cdc                       Clock domain crossing analysis
      -CFLAGS <flags>            C++ compiler arguments for makefile
     --clk <signal-name>         Mark specified signal as clock
     --no-clk <signal-name>      Prevent marking specified signal as clock
     --compiler <compiler-name>  Tune for specified C++ compiler
+    --compiler-include          Include additional header in the precompiled one
     --converge-limit <loops>    Tune convergence settle time
     --coverage                  Enable all coverage
+    --coverage-expr             Enable expression coverage
+    --coverage-expr-max <value>     Maximum permutations allowed for an expression
     --coverage-line             Enable line coverage
     --coverage-max-width <width>   Maximum array depth for coverage
     --coverage-toggle           Enable toggle coverage
@@ -325,21 +341,28 @@ detailed descriptions of these arguments.
     --no-debug-leak             Disable leaking memory in --debug mode
     --debugi <level>            Enable debugging at a specified level
     --debugi-<srcfile> <level>  Enable debugging a source file at a level
-    --no-decoration             Disable comments and symbol decorations
+    --no-decoration             Disable comments and lower spacing level
+    --decorations <level>       Set output comment and spacing level
     --default-language <lang>   Default language to parse
      +define+<var>=<value>      Set preprocessor define
+    --diagnostics-sarif         Enable SARIF diagnostics output
+    --diagnostics-sarif-output <filename>  Set SARIF diagnostics output file
     --dpi-hdr-only              Only produce the DPI header file
+    --dump-<srcfile>            Enable dumping everything in source file
     --dump-defines              Show preprocessor defines with -E
     --dump-dfg                  Enable dumping DfgGraphs to .dot files
     --dump-graph                Enable dumping V3Graphs to .dot files
     --dump-tree                 Enable dumping Ast .tree files
     --dump-tree-addrids         Use short identifiers instead of addresses
-    --dump-<srcfile>            Enable dumping everything in source file
+    --dump-tree-dot             Enable dumping Ast .tree.dot debug files
+    --dump-tree-json            Enable dumping Ast .tree.json files and .tree.meta.json file
+    --dumpi-<srcfile> <level>   Enable dumping everything in source file at level
     --dumpi-dfg <level>         Enable dumping DfgGraphs to .dot files at level
     --dumpi-graph <level>       Enable dumping V3Graphs to .dot files at level
     --dumpi-tree <level>        Enable dumping Ast .tree files at level
-    --dumpi-<srcfile> <level>   Enable dumping everything in source file at level
+    --dumpi-tree-json <level>   Enable dumping Ast .tree.json files at level
      -E                         Preprocess, but do not compile
+    --emit-accessors            Emit getter and setter methods for model top class
     --error-limit <value>       Abort after this number of errors
     --exe                       Link to create executable
     --expand-limit <value>      Set expand optimization limit
@@ -347,55 +370,69 @@ detailed descriptions of these arguments.
      -f <file>                  Parse arguments from a file
      -FI <file>                 Force include of a file
     --flatten                   Force inlining of all modules, tasks and functions
+    --future0 <option>          Ignore an option for compatibility
+    --future1 <option>          Ignore an option with argument for compatibility
      -fno-<optimization>        Disable internal optimization stage
      -G<name>=<value>           Overwrite top-level parameter
     --gate-stmts <value>        Tune gate optimizer depth
     --gdb                       Run Verilator under GDB interactively
     --gdbbt                     Run Verilator under GDB for backtrace
     --generate-key              Create random key for --protect-key
-    --getenv <var>              Get environment variable with defaults
     --get-supported <feature>   Get if feature is supported
-    --help                      Display this help
+    --getenv <var>              Get environment variable with defaults
+    --help                      Show this help
     --hierarchical              Enable hierarchical Verilation
+    --hierarchical-params-file <name> Internal option that specifies parameters file for hier blocks
+    --hierarchical-threads <threads>  Number of threads for hierarchical scheduling
      -I<dir>                    Directory to search for includes
     --if-depth <value>          Tune IFDEPTH warning
      +incdir+<dir>              Directory to search for includes
     --inline-mult <value>       Tune module inlining
     --instr-count-dpi <value>   Assumed dynamic instruction count of DPI imports
      -j <jobs>                  Parallelism for --build-jobs/--verilate-jobs
+    --no-json-edit-nums         Don't dump editNum in .tree.json files
+    --no-json-ids               Don't use short identifiers instead of addresses/paths in .tree.json
+    --json-only                 Create JSON parser output (.tree.json and .meta.json)
+    --json-only-meta-output <filename>  Set .tree.meta.json output filename
+    --json-only-output <filename>       Set .tree.json output filename
     --l2-name <value>           Verilog scope name of the top module
     --language <lang>           Default language standard to parse
      -LDFLAGS <flags>           Linker pre-object arguments for makefile
     --lib-create <name>         Create a DPI library
      +libext+<ext>+[ext]...     Extensions for finding modules
     --lint-only                 Lint, but do not make output
-    --make <build-tool>         Generate scripts for specified build tool
+    --localize-max-size <value>  Tune localize optimization variable size
-     -MAKEFLAGS <flags>         Arguments to pass to make during --build
     --main                      Generate C++ main() file
     --main-top-name             Specify top name passed to Verilated model in generated C++ main
+    --make <build-tool>         Generate scripts for specified build tool
+     -MAKEFLAGS <flags>         Arguments to pass to make during --build
     --max-num-width <value>     Maximum number width (default: 64K)
     --Mdir <directory>          Name of output object directory
     --MMD                       Create .d dependency files
     --mod-prefix <topname>      Name to prepend to lower classes
     --MP                        Create phony dependency targets
      +notimingchecks            Ignored
+     -o <executable>            Name of final executable
      -O0                        Disable optimizations
      -O3                        High-performance optimizations
      -O<optimization-letter>    Selectable optimizations
-     -o <executable>            Name of final executable
+    --output-groups <numfiles>  Group .cpp files into larger ones
-    --no-order-clock-delay      Disable ordering clock enable assignments
     --output-split <statements>          Split .cpp files into pieces
     --output-split-cfuncs <statements>   Split model functions
     --output-split-ctrace <statements>   Split tracing functions
      -P                         Disable line numbers and blanks with -E
     --pins-bv <bits>            Specify types for top-level ports
+    --pins-inout-enables        Specify that __en and __out signals be created for inouts
     --pins-sc-biguint           Specify types for top-level ports
     --pins-sc-uint              Specify types for top-level ports
+    --pins-sc-uint-bool         Specify types for top-level ports
     --pins-uint8                Specify types for top-level ports
     --no-pins64                 Don't use uint64_t's for 33-64 bit sigs
     --pipe-filter <command>     Filter all input through a script
     --pp-comments               Show preprocessor comments with -E
     --prefix <topname>          Name of top-level class
+    --preproc-resolve           Include all found modules in the output with -E
+    --preproc-token-limit       Maximum tokens on a line allowed by preprocessor
     --private                   Debugging; see docs
     --prof-c                    Compile C++ code with profiling
     --prof-cfuncs               Name functions for profiling
@@ -404,43 +441,54 @@ detailed descriptions of these arguments.
     --protect-ids               Hash identifier names for obscurity
     --protect-key <key>         Key for symbol protection
     --protect-lib <name>        Create a DPI protected library
-    --public                    Debugging; see docs
+    --public                    Mark signals as public; see docs
-    --public-params             Mark all parameters as public_flat
+    --public-depth <level>      Mark public to specified module depth
     --public-flat-rw            Mark all variables, etc as public_flat_rw
+    --public-ignore             Ignore all public comment markings
+    --public-params             Mark all parameters as public_flat
      -pvalue+<name>=<value>     Overwrite toplevel parameter
+    --quiet                     Minimize additional printing
     --quiet-exit                Don't print the command on failure
+    --quiet-stats               Don't print statistics
     --relative-includes         Resolve includes relative to current file
-    --reloop-limit              Minimum iterations for forming loops
+    --reloop-limit <value>      Minimum iterations for forming loops
     --report-unoptflat          Extra diagnostics for UNOPTFLAT
     --rr                        Run Verilator and record with rr
+    --runtime-debug             Enable model runtime debugging
     --savable                   Enable model save-restore
     --sc                        Create SystemC output
     --no-skip-identical         Disable skipping identical output
     --stats                     Create statistics file
     --stats-vars                Provide statistics on variables
-    --no-std                    Prevent parsing standard library
+    --no-std                    Prevent loading standard files
+    --no-std-package            Prevent parsing standard package
+    --no-std-waiver             Prevent parsing standard lint waivers
+    --no-stop-fail              Do not call $stop when assertion fails
     --structs-packed            Convert all unpacked structures to packed structures
      -sv                        Enable SystemVerilog parsing
-     +systemverilogext+<ext>    Synonym for +1800-2017ext+<ext>
+     +systemverilogext+<ext>    Synonym for +1800-2023ext+<ext>
     --threads <threads>         Enable multithreading
     --threads-dpi <mode>        Enable multithreaded DPI
     --threads-max-mtasks <mtasks>  Tune maximum mtask partitioning
-    --timing                    Enable timing support
-    --no-timing                 Disable timing support
     --timescale <timescale>     Sets default timescale
     --timescale-override <timescale>  Overrides all timescales
+    --timing                    Enable timing support
+    --no-timing                 Disable timing support
     --top <topname>             Alias of --top-module
     --top-module <topname>      Name of top-level input module
-    --trace                     Enable waveform creation
+    --trace                     Enable VCD waveform creation
     --trace-coverage            Enable tracing of coverage
     --trace-depth <levels>      Depth of tracing
     --trace-fst                 Enable FST waveform creation
-    --trace-max-array <depth>   Maximum bit width for tracing
+    --trace-max-array <depth>   Maximum array depth for tracing
-    --trace-max-width <width>   Maximum array depth for tracing
+    --trace-max-width <width>   Maximum bit width for tracing
     --trace-params              Enable tracing of parameters
+    --trace-saif                Enable SAIF file creation
     --trace-structs             Enable tracing structure names
     --trace-threads <threads>   Enable FST waveform creation on separate threads
+    --no-trace-top              Do not emit traces for signals in the top module generated by verilator
     --trace-underscore          Enable tracing of _signals
+    --trace-vcd                 Enable VCD waveform creation
      -U<var>                    Undefine preprocessor define
     --no-unlimited-stack        Don't disable stack size limit
     --unroll-count <loops>      Tune maximum loop iterations
@@ -448,13 +496,15 @@ detailed descriptions of these arguments.
     --unused-regexp <regexp>    Tune UNUSED lint signals
      -V                         Verbose version and config
      -v <filename>              Verilog library
-    --verilate-jobs             Job threads for Verilation stage
+    --valgrind                  Run Verilator under valgrind
     --no-verilate               Skip Verilation and just compile previously Verilated code
+    --verilate-jobs             Job threads for Verilation stage
      +verilog1995ext+<ext>      Synonym for +1364-1995ext+<ext>
      +verilog2001ext+<ext>      Synonym for +1364-2001ext+<ext>
-    --version                   Displays program version and exits
+    --version                   Show program version and exits
     --vpi                       Enable VPI compiles
-    --waiver-output <filename>  Create a waiver file based on the linter warnings
+    --waiver-multiline          Create multiline --match for waivers
+    --waiver-output <filename>  Create a waiver file based on linter warnings
      -Wall                      Enable all style warnings
      -Werror-<message>          Convert warnings to errors
      -Wfuture-<message>         Disable unknown message warnings
@@ -463,6 +513,7 @@ detailed descriptions of these arguments.
      -Wno-fatal                 Disable fatal exit on warnings
      -Wno-lint                  Disable all lint warnings
      -Wno-style                 Disable all style warnings
+     -work <libname>            Set config library for following files
      -Wpedantic                 Warn on compliance-test issues
      -Wwarn-<message>           Enable specified warning message
      -Wwarn-lint                Enable lint warning message
@@ -481,26 +532,28 @@ description of these arguments.
 
 =for VL_SPHINX_EXTRACT "_build/gen/args_verilated.rst"
 
-     +verilator+debug                  Enable debugging
+     +verilator+coverage+file+<filename>   Set coverage output filename
-     +verilator+debugi+<value>         Enable debugging at a level
+     +verilator+debug                      Enable debugging
-     +verilator+error+limit+<value>    Set error limit
+     +verilator+debugi+<value>             Enable debugging at a level
-     +verilator+help                   Display help
+     +verilator+error+limit+<value>        Set error limit
-     +verilator+noassert               Disable assert checking
+     +verilator+help                       Show help
+     +verilator+noassert                   Disable assert checking
      +verilator+prof+exec+file+<filename>  Set execution profile filename
      +verilator+prof+exec+start+<value>    Set execution profile starting point
      +verilator+prof+exec+window+<value>   Set execution profile duration
      +verilator+prof+vlt+file+<filename>   Set PGO profile filename
-     +verilator+rand+reset+<value>     Set random reset technique
+     +verilator+quiet                      Minimize additional printing
-     +verilator+seed+<value>           Set random seed
+     +verilator+rand+reset+<value>         Set random reset technique
-     +verilator+V                      Verbose version and config
+     +verilator+seed+<value>               Set random seed
-     +verilator+version                Show version and exit
+     +verilator+V                          Show verbose version and config
+     +verilator+version                    Show version and exit
 
 
 =head1 DISTRIBUTION
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2023 by Wilson Snyder. This program is free software; you can
+Copyright 2003-2025 by Wilson Snyder. This program is free software; you can
 redistribute it and/or modify the Verilator internals under the terms of
 either the GNU Lesser General Public License Version 3 or the Perl Artistic
 License Version 2.0.

bin/verilator_ccache_report

@@ -16,8 +16,7 @@ parser = argparse.ArgumentParser(
 
     For documentation see
     https://verilator.org/guide/latest/exe_verilator_ccache_report.html""",
-    epilog=
+    epilog="""Copyright 2002-2025 by Wilson Snyder. This program is free software; you
-    """Copyright 2002-2023 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
@@ -67,30 +66,23 @@ else:
     wnames = max(len(_) for _ in results) + 1
     wresults = max(len(_) for _ in results.values()) + 1
     for k in sorted(results.keys()):
-        args.o.write("{:{wnames}} : {:{wresults}} : {}s\n".format(
+        args.o.write("{:{wnames}} : {:{wresults}} : {}s\n".format(k,
-            k,
+                                                                  results[k],
-            results[k],
+                                                                  elapsed[k].total_seconds(),
-            elapsed[k].total_seconds(),
+                                                                  wnames=wnames,
-            wnames=wnames,
+                                                                  wresults=wresults))
-            wresults=wresults))
 
     args.o.write("\nSummary:\n")
     counts = collections.Counter(_ for _ in results.values())
     total = sum(counts.values())
     for k in sorted(counts.keys()):
         c = counts[k]
-        args.o.write("{:{width}}| {} ({:.2%})\n".format(k,
+        args.o.write("{:{width}}| {} ({:.2%})\n".format(k, c, c / total, width=wresults))
-                                                        c,
-                                                        c / total,
-                                                        width=wresults))
 
     args.o.write("\nLongest:\n")
-    longest = sorted(list(elapsed.items()),
+    longest = sorted(list(elapsed.items()), key=lambda kv: -kv[1].total_seconds())
-                     key=lambda kv: -kv[1].total_seconds())
     for i, (k, v) in enumerate(longest):
-        args.o.write("{:{width}}| {}s\n".format(k,
+        args.o.write("{:{width}}| {}s\n".format(k, v.total_seconds(), width=wnames))
-                                                v.total_seconds(),
-                                                width=wnames))
         if i > 4:
             break
 

bin/verilator_coverage

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -154,9 +154,9 @@ verilator_coverage - Verilator coverage analyzer
 
     verilator_coverage --annotate <obj>
 
-    verilator_coverage  -write merged.dat -read <datafiles>...
+    verilator_coverage  -write merged.dat <datafiles>...
 
-    verilator_coverage  -write-info merged.info -read <datafiles>...
+    verilator_coverage  -write-info merged.info <datafiles>...
 
 Verilator_coverage processes Verilated model-generated coverage reports.
 
@@ -170,6 +170,7 @@ L<https://verilator.org/guide/latest/exe_verilator_coverage.html>.
     --annotate-all                All files should be shown.
     --annotate-min <count>        Minimum occurrence count for uncovered.
     --annotate-points             Annotates info from each coverage point.
+    --filter-type <regex>         Keep only records of given coverage type.
     --help                        Displays this message and version and exits.
     --rank                        Compute relative importance of tests.
     --unlink                      With --write, unlink all inputs
@@ -177,18 +178,18 @@ L<https://verilator.org/guide/latest/exe_verilator_coverage.html>.
     --write <filename>            Write aggregate coverage results.
     --write-info <filename.info>  Write lcov .info.
 
-    +libext+I<ext>+I<ext>...      Extensions for Verilog files.
+    +libext+<ext>+<ext>...        Extensions for Verilog files.
-    +define+I<var>+I<value>       Defines the given variable.
+    +define+<var>+<value>         Defines the given variable.
-    -DI<var>=I<value>             Defines the given variable.
+    -D<var>=<value>               Defines the given variable.
-    +incdir+I<dir>                Add directory for finding include files.
+    +incdir+<dir>                 Add directory for finding include files.
-    -II<dir>                      Add directory for finding include files.
+    -I<dir>                       Add directory for finding include files.
-    -y I<dir>                     Specifies module search directory.
+    -y <dir>                      Specifies module search directory.
 
 =head1 DISTRIBUTION
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2023 by Wilson Snyder. This program is free software; you
+Copyright 2003-2025 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.

bin/verilator_difftree

@@ -47,8 +47,7 @@ def diff_dir(a, b):
         diff_file(a, b)
         anyfile = True
     if not anyfile:
-        sys.stderr.write(
+        sys.stderr.write("%Warning: No .tree files found that have similar base names\n")
-            "%Warning: No .tree files found that have similar base names\n")
 
 
 def diff_file(a, b):
@@ -109,18 +108,14 @@ parser = argparse.ArgumentParser(
 Verilator_difftree is used for debugging Verilator tree output files.
 It performs a diff between two files, or all files common between two
 directories, ignoring irrelevant pointer differences.""",
-    epilog=
+    epilog="""Copyright 2005-2025 by Wilson Snyder. This program is free software; you
-    """Copyright 2005-2023 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
 
 SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
-parser.add_argument('--debug',
+parser.add_argument('--debug', action='store_const', const=9, help='enable debug')
-                    action='store_const',
-                    const=9,
-                    help='enable debug')
 parser.add_argument('--no-lineno',
                     action='store_false',
                     help='do not show differences in line numbering')

bin/verilator_gantt

@@ -1,52 +1,65 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0116,C0209,C0301,R0914,R0912,R0915,W0511,eval-used
+# pylint: disable=C0103,C0114,C0116,C0209,C0301,R0914,R0912,R0915,W0511,W0603,eval-used
 ######################################################################
 
 import argparse
+import bisect
 import collections
 import math
 import re
 import statistics
+from collections import OrderedDict
 # from pprint import pprint
 
-Threads = collections.defaultdict(lambda: collections.defaultdict(lambda: {}))
+Sections = OrderedDict()
-Mtasks = collections.defaultdict(lambda: {})
+LongestVcdStrValueLength = 0
-Evals = collections.defaultdict(lambda: {})
+Threads = collections.defaultdict(lambda: [])  # List of records per thread id
-EvalLoops = collections.defaultdict(lambda: {})
+Mtasks = collections.defaultdict(lambda: {'elapsed': 0, 'end': 0})
+Cpus = collections.defaultdict(lambda: {'mtask_time': 0})
 Global = {
     'args': {},
     'cpuinfo': collections.defaultdict(lambda: {}),
-    'rdtsc_cycle_time': 0,
+    'info': {
+        'numa': 'no data'
+    },
     'stats': {}
 }
+ElapsedTime = None  # total elapsed time
+ExecGraphTime = 0  # total elapsed time executing an exec graph
+WaitingTime = 0  # total elapsed time waiting for mtasks
+ExecGraphIntervals = []  # list of (start, end) pairs
+ThreadScheduleWaitIntervals = []  # list of (start, tick, ecpu) pairs
 
 ######################################################################
 
 
-def process(filename):
-    read_data(filename)
-    report()
-
-
 def read_data(filename):
     with open(filename, "r", encoding="utf8") as fh:
         re_thread = re.compile(r'^VLPROFTHREAD (\d+)$')
         re_record = re.compile(r'^VLPROFEXEC (\S+) (\d+)(.*)$')
+        # The hierBlock argument is optional
         re_payload_mtaskBegin = re.compile(
-            r'id (\d+) predictStart (\d+) cpu (\d+)')
+            r'id (\d+) predictStart (\d+) cpu (\d+)(?: hierBlock)?\s*(\w+)?')
-        re_payload_mtaskEnd = re.compile(r'id (\d+) predictCost (\d+)')
+        re_payload_mtaskEnd = re.compile(r'predictCost (\d+)')
+        re_payload_wait = re.compile(r'cpu (\d+)')
 
         re_arg1 = re.compile(r'VLPROF arg\s+(\S+)\+([0-9.]*)\s*')
         re_arg2 = re.compile(r'VLPROF arg\s+(\S+)\s+([0-9.]*)\s*$')
-        re_stat = re.compile(r'VLPROF stat\s+(\S+)\s+([0-9.]+)')
+        re_info = re.compile(r'VLPROF info\s+(\S+)\s+(.*)$')
-        re_time = re.compile(r'rdtsc time = (\d+) ticks')
+        re_stat = re.compile(r'VLPROF stat\s+(\S+)\s+(\S+)')
         re_proc_cpu = re.compile(r'VLPROFPROC processor\s*:\s*(\d+)\s*$')
         re_proc_dat = re.compile(r'VLPROFPROC ([a-z_ ]+)\s*:\s*(.*)$')
         cpu = None
-        thread = None
+        thread = 0
 
-        lastEvalBeginTick = None
+        global LongestVcdStrValueLength
-        lastEvalLoopBeginTick = None
+        global ExecGraphTime
+        global WaitingTime
+
+        ExecGraphStack = []
+        SectionStack = []
+        MtasksStack = []
+        ThreadScheduleWait = collections.defaultdict(list)
 
         for line in fh:
             recordMatch = re_record.match(line)
@@ -54,47 +67,66 @@ def read_data(filename):
                 kind, tick, payload = recordMatch.groups()
                 tick = int(tick)
                 payload = payload.strip()
-                if kind == "EVAL_BEGIN":
+                if kind == "SECTION_PUSH":
-                    Evals[tick]['start'] = tick
+                    LongestVcdStrValueLength = max(LongestVcdStrValueLength, len(payload))
-                    lastEvalBeginTick = tick
+                    SectionStack.append(payload)
-                elif kind == "EVAL_END":
+                    Sections[thread].append((tick, tuple(SectionStack)))
-                    Evals[lastEvalBeginTick]['end'] = tick
+                elif kind == "SECTION_POP":
-                    lastEvalBeginTick = None
+                    assert SectionStack, "SECTION_POP without SECTION_PUSH"
-                elif kind == "EVAL_LOOP_BEGIN":
+                    SectionStack.pop()
-                    EvalLoops[tick]['start'] = tick
+                    Sections[thread].append((tick, tuple(SectionStack)))
-                    lastEvalLoopBeginTick = tick
-                elif kind == "EVAL_LOOP_END":
-                    EvalLoops[lastEvalLoopBeginTick]['end'] = tick
-                    lastEvalLoopBeginTick = None
                 elif kind == "MTASK_BEGIN":
-                    mtask, predict_start, ecpu = re_payload_mtaskBegin.match(
+                    mtask, predict_start, ecpu, hier_block = re_payload_mtaskBegin.match(
                         payload).groups()
+                    hier_block = "" if hier_block is None else hier_block
                     mtask = int(mtask)
                     predict_start = int(predict_start)
                     ecpu = int(ecpu)
-                    Threads[thread][tick]['mtask'] = mtask
+                    records = Threads[thread]
-                    Threads[thread][tick]['predict_start'] = predict_start
+                    records.append({
-                    Threads[thread][tick]['cpu'] = ecpu
+                        'start': tick,
-                    if 'elapsed' not in Mtasks[mtask]:
+                        'mtask': mtask,
-                        Mtasks[mtask] = {'end': 0, 'elapsed': 0}
+                        'predict_start': predict_start,
-                    Mtasks[mtask]['begin'] = tick
+                        'hier_block': hier_block,
-                    Mtasks[mtask]['thread'] = thread
+                        'cpu': ecpu
-                    Mtasks[mtask]['predict_start'] = predict_start
+                    })
+                    Mtasks[(hier_block, mtask)]['begin'] = tick
+                    Mtasks[(hier_block, mtask)]['predict_start'] = predict_start
+                    Mtasks[(hier_block, mtask)]['thread'] = thread
+                    MtasksStack.append((hier_block, mtask, records[-1]))
                 elif kind == "MTASK_END":
-                    mtask, predict_cost = re_payload_mtaskEnd.match(
+                    predict_cost, = re_payload_mtaskEnd.match(payload).groups()
-                        payload).groups()
                     mtask = int(mtask)
+                    hier_block, mtask, record = MtasksStack.pop()
                     predict_cost = int(predict_cost)
-                    begin = Mtasks[mtask]['begin']
+                    begin = Mtasks[(hier_block, mtask)]['begin']
-                    Threads[thread][begin]['end'] = tick
+                    record['end'] = tick
-                    Threads[thread][begin]['predict_cost'] = predict_cost
+                    assert record and records[-1]['start'] <= records[-1]['end'] <= tick
-                    Mtasks[mtask]['elapsed'] += tick - begin
+                    record['predict_cost'] = predict_cost
-                    Mtasks[mtask]['predict_cost'] = predict_cost
+                    Mtasks[(hier_block, mtask)]['elapsed'] += tick - begin
-                    Mtasks[mtask]['end'] = max(Mtasks[mtask]['end'], tick)
+                    Mtasks[(hier_block, mtask)]['predict_cost'] = predict_cost
+                    Mtasks[(hier_block, mtask)]['end'] = max(Mtasks[(hier_block, mtask)]['end'],
+                                                             tick)
+                elif kind == "THREAD_SCHEDULE_WAIT_BEGIN":
+                    ecpu = int(re_payload_wait.match(payload).groups()[0])
+                    ThreadScheduleWait[ecpu].append(tick)
+                elif kind == "THREAD_SCHEDULE_WAIT_END":
+                    ecpu = int(re_payload_wait.match(payload).groups()[0])
+                    start = ThreadScheduleWait[ecpu].pop()
+                    WaitingTime += tick - start
+                    ThreadScheduleWaitIntervals.append((start, tick, ecpu))
+                elif kind == "EXEC_GRAPH_BEGIN":
+                    ExecGraphStack.append(tick)
+                elif kind == "EXEC_GRAPH_END":
+                    assert ExecGraphStack, "EXEC_GRAPH_END without EXEC_GRAPH_BEGIN"
+                    execGraphStart = ExecGraphStack.pop()
+                    ExecGraphTime += tick - execGraphStart
+                    ExecGraphIntervals.append((execGraphStart, tick))
                 elif Args.debug:
                     print("-Unknown execution trace record: %s" % line)
             elif re_thread.match(line):
                 thread = int(re_thread.match(line).group(1))
+                Sections[thread] = []
             elif re.match(r'^VLPROF(THREAD|VERSION)', line):
                 pass
             elif re_arg1.match(line):
@@ -103,13 +135,16 @@ def read_data(filename):
             elif re_arg2.match(line):
                 match = re_arg2.match(line)
                 Global['args'][match.group(1)] = match.group(2)
+            elif re_info.match(line):
+                match = re_info.match(line)
+                Global['info'][match.group(1)] = match.group(2)
             elif re_stat.match(line):
                 match = re_stat.match(line)
                 Global['stats'][match.group(1)] = match.group(2)
             elif re_proc_cpu.match(line):
                 match = re_proc_cpu.match(line)
                 cpu = int(match.group(1))
-            elif cpu and re_proc_dat.match(line):
+            elif cpu is not None and re_proc_dat.match(line):
                 match = re_proc_dat.match(line)
                 term = match.group(1)
                 value = match.group(2)
@@ -121,11 +156,6 @@ def read_data(filename):
                 pass
             elif Args.debug:
                 print("-Unk: %s" % line)
-            # TODO -- this is parsing text printed by a client.
-            # Really, verilator proper should generate this
-            # if it's useful...
-            if re_time.match(line):
-                Global['rdtsc_cycle_time'] = re_time.group(1)
 
 
 def re_match_result(regexp, line, result_to):
@@ -144,34 +174,57 @@ def report():
         plus = "+" if re.match(r'^\+', arg) else " "
         print("  %s%s%s" % (arg, plus, Global['args'][arg]))
 
-    nthreads = int(Global['stats']['threads'])
+    for records in Threads.values():
-    Global['cpus'] = {}
+        for record in records:
-    for thread in Threads:
+            cpu = record['cpu']
-        # Make potentially multiple characters per column
+            elapsed = record['end'] - record['start']
-        for start in Threads[thread]:
+            Cpus[cpu]['mtask_time'] += elapsed
-            if not Threads[thread][start]:
-                continue
-            cpu = Threads[thread][start]['cpu']
-            elapsed = Threads[thread][start]['end'] - start
-            if cpu not in Global['cpus']:
-                Global['cpus'][cpu] = {'cpu_time': 0}
-            Global['cpus'][cpu]['cpu_time'] += elapsed
 
-    measured_mt_mtask_time = 0
+    global ElapsedTime
-    predict_mt_mtask_time = 0
+    ElapsedTime = int(Global['stats']['ticks'])
-    long_mtask_time = 0
+    nthreads = int(Global['stats']['threads'])
-    measured_last_end = 0
+    ncpus = max(len(Cpus), 1)
-    predict_last_end = 0
+
-    for mtask in Mtasks:
+    print("\nSummary:")
-        measured_mt_mtask_time += Mtasks[mtask]['elapsed']
+    print("  Total elapsed time = {} rdtsc ticks".format(ElapsedTime))
-        predict_mt_mtask_time += Mtasks[mtask]['predict_cost']
+    print("  Parallelized code  = {:.2%} of elapsed time".format(ExecGraphTime / ElapsedTime))
-        measured_last_end = max(measured_last_end, Mtasks[mtask]['end'])
+    print("  Waiting time       = {:.2%} of elapsed time".format(WaitingTime / ElapsedTime))
-        predict_last_end = max(
+    print("  Total threads      = %d" % nthreads)
-            predict_last_end,
+    print("  Total CPUs used    = %d" % ncpus)
-            Mtasks[mtask]['predict_start'] + Mtasks[mtask]['predict_cost'])
+    print("  Total mtasks       = %d" % len(Mtasks))
-        long_mtask_time = max(long_mtask_time, Mtasks[mtask]['elapsed'])
+    print("  Total yields       = %d" % int(Global['stats'].get('yields', 0)))
-    Global['measured_last_end'] = measured_last_end
+
-    Global['predict_last_end'] = predict_last_end
+    report_numa()
+    report_mtasks()
+    report_cpus()
+    report_sections()
+
+    if nthreads > ncpus:
+        print()
+        print("%%Warning: There were fewer CPUs (%d) than threads (%d)." % (ncpus, nthreads))
+        print("        : See docs on use of numactl.")
+    else:
+        if 'cpu_socket_cores_warning' in Global:
+            print()
+            print("%Warning: Multiple threads scheduled on same hyperthreaded core.")
+            print("        : See docs on use of numactl.")
+        if 'cpu_sockets_warning' in Global:
+            print()
+            print("%Warning: Threads scheduled on multiple sockets.")
+            print("        : See docs on use of numactl.")
+    print()
+
+
+def report_numa():
+    print("\nNUMA assignment:")
+    print("  NUMA status        = %s" % Global['info']['numa'])
+
+
+def report_mtasks():
+    if not Mtasks:
+        return
+
+    nthreads = int(Global['stats']['threads'])
 
     # If we know cycle time in the same (rdtsc) units,
     # this will give us an actual utilization number,
@@ -181,130 +234,136 @@ def report():
     # serial mode, to estimate the overhead of data sharing,
     # which will show up in the total elapsed time. (Overhead
     # of synchronization and scheduling should not.)
-    print("\nAnalysis:")
+    total_mtask_time = 0
-    print("  Total threads             = %d" % nthreads)
+    thread_mtask_time = collections.defaultdict(lambda: 0)
-    print("  Total mtasks              = %d" % len(Mtasks))
+    long_mtask_time = 0
-    ncpus = max(len(Global['cpus']), 1)
+    long_mtask = None
-    print("  Total cpus used           = %d" % ncpus)
+    long_mtask_hier_block = None
-    print("  Total yields              = %d" %
+    predict_mtask_time = 0
-          int(Global['stats'].get('yields', 0)))
+    predict_elapsed = 0
-    print("  Total evals               = %d" % len(Evals))
+    for (hier_block, mtask_id) in Mtasks:
-    print("  Total eval loops          = %d" % len(EvalLoops))
+        record = Mtasks[(hier_block, mtask_id)]
-    if Mtasks:
+        predict_mtask_time += record['predict_cost']
-        print("  Total eval time           = %d rdtsc ticks" %
+        total_mtask_time += record['elapsed']
-              Global['measured_last_end'])
+        thread_mtask_time[record['thread']] += record['elapsed']
-        print("  Longest mtask time        = %d rdtsc ticks" % long_mtask_time)
+        predict_end = record['predict_start'] + record['predict_cost']
-        print("  All-thread mtask time     = %d rdtsc ticks" %
+        predict_elapsed = max(predict_elapsed, predict_end)
-              measured_mt_mtask_time)
+        if record['elapsed'] > long_mtask_time:
-        long_efficiency = long_mtask_time / (Global.get(
+            long_mtask_time = record['elapsed']
-            'measured_last_end', 1) or 1)
+            long_mtask = mtask_id
-        print("  Longest-thread efficiency = %0.1f%%" %
+            long_mtask_hier_block = hier_block
-              (long_efficiency * 100.0))
+    Global['predict_last_end'] = predict_elapsed
-        mt_efficiency = measured_mt_mtask_time / (
-            Global.get('measured_last_end', 1) * nthreads or 1)
-        print("  All-thread efficiency     = %0.1f%%" %
-              (mt_efficiency * 100.0))
-        print("  All-thread speedup        = %0.1f" %
-              (mt_efficiency * nthreads))
-        if Global['rdtsc_cycle_time'] > 0:
-            ut = measured_mt_mtask_time / Global['rdtsc_cycle_time']
-            print("tot_mtask_cpu=" + measured_mt_mtask_time + " cyc=" +
-                  Global['rdtsc_cycle_time'] + " ut=" + ut)
 
-        predict_mt_efficiency = predict_mt_mtask_time / (
+    serialTime = ElapsedTime - ExecGraphTime
-            Global.get('predict_last_end', 1) * nthreads or 1)
-        print("\nPrediction (what Verilator used for scheduling):")
-        print("  All-thread efficiency     = %0.1f%%" %
-              (predict_mt_efficiency * 100.0))
-        print("  All-thread speedup        = %0.1f" %
-              (predict_mt_efficiency * nthreads))
 
-        p2e_ratios = []
+    def subReport(elapsed, work):
-        min_p2e = 1000000
+        print("  Thread utilization = {:7.2%}".format(work / (elapsed * nthreads)))
-        min_mtask = None
+        print("  Speedup            = {:6.3}x".format(work / elapsed))
-        max_p2e = -1000000
-        max_mtask = None
 
-        for mtask in sorted(Mtasks.keys()):
+    print("\nParallelized code, measured:")
-            if Mtasks[mtask]['elapsed'] > 0:
+    subReport(ExecGraphTime, total_mtask_time)
-                if Mtasks[mtask]['predict_cost'] == 0:
-                    Mtasks[mtask]['predict_cost'] = 1  # don't log(0) below
-                p2e_ratio = math.log(Mtasks[mtask]['predict_cost'] /
-                                     Mtasks[mtask]['elapsed'])
-                p2e_ratios.append(p2e_ratio)
 
-                if p2e_ratio > max_p2e:
+    print("\nParallelized code, predicted during static scheduling:")
-                    max_p2e = p2e_ratio
+    subReport(predict_elapsed, predict_mtask_time)
-                    max_mtask = mtask
-                if p2e_ratio < min_p2e:
-                    min_p2e = p2e_ratio
-                    min_mtask = mtask
 
-        print("\nMTask statistics:")
+    print("\nAll code, measured:")
-        print("  min log(p2e) = %0.3f" % min_p2e, end="")
+    subReport(ElapsedTime, serialTime + total_mtask_time)
-        print("  from mtask %d (predict %d," %
-              (min_mtask, Mtasks[min_mtask]['predict_cost']),
-              end="")
-        print(" elapsed %d)" % Mtasks[min_mtask]['elapsed'])
-        print("  max log(p2e) = %0.3f" % max_p2e, end="")
-        print("  from mtask %d (predict %d," %
-              (max_mtask, Mtasks[max_mtask]['predict_cost']),
-              end="")
-        print(" elapsed %d)" % Mtasks[max_mtask]['elapsed'])
 
-        stddev = statistics.pstdev(p2e_ratios)
+    print("\nAll code, measured, scaled by predicted speedup:")
-        mean = statistics.mean(p2e_ratios)
+    expectedParallelSpeedup = predict_mtask_time / predict_elapsed
-        print("  mean = %0.3f" % mean)
+    scaledElapsed = serialTime + total_mtask_time / expectedParallelSpeedup
-        print("  stddev = %0.3f" % stddev)
+    subReport(scaledElapsed, serialTime + total_mtask_time)
-        print("  e ^ stddev = %0.3f" % math.exp(stddev))
 
-    report_cpus()
+    p2e_ratios = []
+    min_p2e = 1000000
+    min_mtask = None
+    max_p2e = -1000000
+    max_mtask = None
 
-    if nthreads > ncpus:
+    min_hier_block = None
-        print()
+    max_hier_block = None
-        print("%%Warning: There were fewer CPUs (%d) then threads (%d)." %
+
-              (ncpus, nthreads))
+    for (hier_block, mtask_id) in sorted(Mtasks.keys()):
-        print("        : See docs on use of numactl.")
+        mtask = Mtasks[(hier_block, mtask_id)]
+        if mtask['elapsed'] > 0:
+            if mtask['predict_cost'] == 0:
+                mtask['predict_cost'] = 1  # don't log(0) below
+            p2e_ratio = math.log(mtask['predict_cost'] / mtask['elapsed'])
+            p2e_ratios.append(p2e_ratio)
+
+            if p2e_ratio > max_p2e:
+                max_p2e = p2e_ratio
+                max_mtask = mtask_id
+                max_hier_block = hier_block
+            if p2e_ratio < min_p2e:
+                min_p2e = p2e_ratio
+                min_mtask = mtask_id
+                min_hier_block = hier_block
+
+    print("\nMTask statistics:")
+    if long_mtask_hier_block:
+        print("  Longest mtask id = {} from hier_block '{}'".format(long_mtask,
+                                                                    long_mtask_hier_block))
     else:
-        if 'cpu_socket_cores_warning' in Global:
+        print("  Longest mtask id = {}".format(long_mtask))
-            print()
+    print("  Longest mtask time = {:.2%} of time elapsed in parallelized code".format(
-            print(
+        long_mtask_time / ExecGraphTime))
-                "%Warning: Multiple threads scheduled on same hyperthreaded core."
+    print("  min log(p2e) = %0.3f" % min_p2e, end="")
-            )
+
-            print("        : See docs on use of numactl.")
+    if min_hier_block:
-        if 'cpu_sockets_warning' in Global:
+        print("  from hier_block '%s' mtask %d (predict %d," %
-            print()
+              (min_hier_block, min_mtask, Mtasks[(min_hier_block, min_mtask)]['predict_cost']),
-            print("%Warning: Threads scheduled on multiple sockets.")
+              end="")
-            print("        : See docs on use of numactl.")
+    else:
-    print()
+        print("  from mtask %d (predict %d," %
+              (min_mtask, Mtasks[(min_hier_block, min_mtask)]['predict_cost']),
+              end="")
+    print(" elapsed %d)" % Mtasks[(min_hier_block, min_mtask)]['elapsed'])
+    print("  max log(p2e) = %0.3f" % max_p2e, end="")
+    if max_hier_block:
+        print("  from hier_block '%s' mtask %d (predict %d," %
+              (max_hier_block, max_mtask, Mtasks[(max_hier_block, max_mtask)]['predict_cost']),
+              end="")
+    else:
+        print("  from mtask %d (predict %d," %
+              (max_mtask, Mtasks[(max_hier_block, max_mtask)]['predict_cost']),
+              end="")
+    print(" elapsed %d)" % Mtasks[(max_hier_block, max_mtask)]['elapsed'])
+
+    stddev = statistics.pstdev(p2e_ratios)
+    mean = statistics.mean(p2e_ratios)
+    print("  mean = %0.3f" % mean)
+    print("  stddev = %0.3f" % stddev)
+    print("  e ^ stddev = %0.3f" % math.exp(stddev))
 
 
 def report_cpus():
-    print("\nCPUs:")
+    print("\nCPU info:")
 
     Global['cpu_sockets'] = collections.defaultdict(lambda: 0)
     Global['cpu_socket_cores'] = collections.defaultdict(lambda: 0)
 
-    for cpu in sorted(Global['cpus'].keys()):
+    print("   Id | Time spent executing MTask | Socket | Core | Model")
-        print("  cpu %d: " % cpu, end='')
+    print("      | % of elapsed ticks / ticks |        |      |")
-        print("cpu_time=%d" % Global['cpus'][cpu]['cpu_time'], end='')
+    print("  ====|============================|========|======|======")
-
+    for cpu in sorted(Cpus):
-        socket = None
+        socket = ""
+        core = ""
+        model = ""
         if cpu in Global['cpuinfo']:
             cpuinfo = Global['cpuinfo'][cpu]
             if 'physical_id' in cpuinfo and 'core_id' in cpuinfo:
-                socket = int(cpuinfo['physical_id'])
+                socket = cpuinfo['physical_id']
                 Global['cpu_sockets'][socket] += 1
-                print(" socket=%d" % socket, end='')
+                core = cpuinfo['core_id']
-
+                Global['cpu_socket_cores'][socket + "__" + core] += 1
-                core = int(cpuinfo['core_id'])
-                Global['cpu_socket_cores'][str(socket) + "__" + str(core)] += 1
-                print(" core=%d" % core, end='')
 
             if 'model_name' in cpuinfo:
                 model = cpuinfo['model_name']
-                print("  %s" % model, end='')
+
-        print()
+        print("  {:3d} | {:7.2%} / {:16d} | {:>6s} | {:>4s} | {}".format(
+            cpu, Cpus[cpu]['mtask_time'] / ElapsedTime, Cpus[cpu]['mtask_time'], socket, core,
+            model))
 
     if len(Global['cpu_sockets']) > 1:
         Global['cpu_sockets_warning'] = True
@@ -313,25 +372,72 @@ def report_cpus():
                 Global['cpu_socket_cores_warning'] = True
 
 
+def report_sections():
+    for thread, section in Sections.items():
+        if section:
+            print(f"\nSection profile for thread {thread}:")
+            report_section(section)
+
+
+def report_section(section):
+    totalTime = collections.defaultdict(lambda: 0)
+    selfTime = collections.defaultdict(lambda: 0)
+
+    sectionTree = [0, {}, 1]  # [selfTime, childTrees, numberOfTimesEntered]
+    prevTime = 0
+    prevStack = ()
+    for time, stack in section:
+        if len(stack) > len(prevStack):
+            scope = sectionTree
+            for item in stack:
+                scope = scope[1].setdefault(item, [0, {}, 0])
+            scope[2] += 1
+        dt = time - prevTime
+        assert dt >= 0
+        scope = sectionTree
+        for item in prevStack:
+            scope = scope[1].setdefault(item, [0, {}, 0])
+        scope[0] += dt
+
+        if prevStack:
+            for name in prevStack:
+                totalTime[name] += dt
+            selfTime[prevStack[-1]] += dt
+        prevTime = time
+        prevStack = stack
+
+    def treeSum(tree):
+        n = tree[0]
+        for subTree in tree[1].values():
+            n += treeSum(subTree)
+        return n
+
+    # Make sure the tree sums to the elapsed time
+    sectionTree[0] += ElapsedTime - treeSum(sectionTree)
+
+    def printTree(prefix, name, entries, tree):
+        print("  {:7.2%} | {:7.2%} | {:8} | {:10.2f} | {}".format(
+            treeSum(tree) / ElapsedTime, tree[0] / ElapsedTime, tree[2], tree[2] / entries,
+            prefix + name))
+        for k in sorted(tree[1], key=lambda _: -treeSum(tree[1][_])):
+            printTree(prefix + "  ", k, tree[2], tree[1][k])
+
+    print(" Total    | Self    | Total    | Relative   | Section")
+    print(" time     | time    | entries  | entries    |  name  ")
+    print("==========|=========|==========|============|========")
+    printTree("", "*TOTAL*", 1, sectionTree)
+
+
 ######################################################################
 
 
 def write_vcd(filename):
     print("Writing %s" % filename)
     with open(filename, "w", encoding="utf8") as fh:
-        vcd = {
+        # dict of dicts of hierarchy elements/signal name  -> (code, width)
-            'values':
+        scopeSigs = {}
-            collections.defaultdict(lambda: {}),  # {<time>}{<code>} = value
+        # map from time -> code -> value
-            'sigs': {
+        values = collections.defaultdict(lambda: {})
-                'predicted_threads': {},
-                'measured_threads': {},
-                'cpus': {},
-                'evals': {},
-                'mtasks': {},
-                'Stats': {}
-            }  # {<module>}{<sig}} = code
-        }
-        code = 0
 
         parallelism = {
             'measured': collections.defaultdict(lambda: 0),
@@ -340,132 +446,151 @@ def write_vcd(filename):
         parallelism['measured'][0] = 0
         parallelism['predicted'][0] = 0
 
-        # Measured graph
+        nextFreeCode = 0
-        for thread in sorted(Threads.keys()):
-            sig = "thread%d_mtask" % thread
-            if sig not in vcd['sigs']['measured_threads']:
-                vcd['sigs']['measured_threads'][sig] = code
-                code += 1
-            mcode = vcd['sigs']['measured_threads'][sig]
 
-            for start in sorted(Threads[thread]):
+        def getCode(width, *names):
-                mtask = Threads[thread][start]['mtask']
+            nonlocal nextFreeCode
-                end = Threads[thread][start]['end']
+            scope = scopeSigs
-                cpu = Threads[thread][start]['cpu']
+            *path, name = names
-                vcd['values'][start][mcode] = mtask
+            for item in path:
-                vcd['values'][end][mcode] = None
+                scope = scope.setdefault(item, {})
+            code, oldWidth = scope.setdefault(name, (nextFreeCode, width))
+            assert oldWidth == width
+            if code == nextFreeCode:
+                nextFreeCode += 1
+            return code
+
+        def addValue(code, time, val):
+            if isinstance(val, str):
+                buf = ""
+                for c in val:
+                    buf += bin(ord(c))[2:].rjust(8, "0")
+                val = buf.ljust(LongestVcdStrValueLength * 8, "0")
+            values[time][code] = val
+
+        def addXValue(code, time):
+            values[time][code] = 'x'
+
+        # Measured graph
+        for thread in sorted(Threads):
+            mcode = getCode(32, 'measured', 't%d_mtask' % thread)
+            for record in Threads[thread]:
+                start = record['start']
+                mtask = record['mtask']
+                end = record['end']
+                cpu = record['cpu']
+                addValue(mcode, start, mtask)
+                addValue(mcode, end, None)
                 parallelism['measured'][start] += 1
                 parallelism['measured'][end] -= 1
 
-                sig = "cpu%d_thread" % cpu
+                code = getCode(32, 'measured', 'cpu%d_thread' % cpu)
-                if sig not in vcd['sigs']['cpus']:
+                addValue(code, start, thread)
-                    vcd['sigs']['cpus'][sig] = code
+                addValue(code, end, None)
-                    code += 1
-                ccode = vcd['sigs']['cpus'][sig]
-                vcd['values'][start][ccode] = thread
-                vcd['values'][end][ccode] = None
 
-                sig = "mtask%d_cpu" % mtask
+                code = getCode(32, 'measured', 'cpu%d_mtask' % cpu)
-                if sig not in vcd['sigs']['mtasks']:
+                addValue(code, start, mtask)
-                    vcd['sigs']['mtasks'][sig] = code
+                addValue(code, end, None)
-                    code += 1
-                ccode = vcd['sigs']['mtasks'][sig]
-                vcd['values'][start][ccode] = cpu
-                vcd['values'][end][ccode] = None
 
-        # Eval graph
+        tStart = sorted(_['start'] for records in Threads.values() for _ in records)
-        vcd['sigs']['evals']["eval"] = code
+        tEnd = sorted(_['end'] for records in Threads.values() for _ in records)
-        elcode = code
-        code += 1
-        n = 0
-        for eval_start in Evals:
-            eval_end = Evals[eval_start]['end']
-            n += 1
-            vcd['values'][eval_start][elcode] = n
-            vcd['values'][eval_end][elcode] = None
 
-        # Eval_loop graph
+        # Measured waiting time
-        vcd['sigs']['evals']["eval_loop"] = code
+        for (start, end, cpu) in ThreadScheduleWaitIntervals:
-        elcode = code
+            mcode = getCode(32, 'measured', 'cpu%d_waiting' % cpu)
-        code += 1
+            addXValue(mcode, start)
-        n = 0
+            addValue(mcode, end, None)
-        for eval_start in EvalLoops:
-            eval_end = EvalLoops[eval_start]['end']
-            n += 1
-            vcd['values'][eval_start][elcode] = n
-            vcd['values'][eval_end][elcode] = None
 
-        if Mtasks:
+        # Predicted graph
-            # Predicted graph
+        for start, end in ExecGraphIntervals:
-            for eval_start in EvalLoops:
+            # Find the earliest MTask start after the start point, and the
-                eval_end = EvalLoops[eval_start]['end']
+            # latest MTask end before the end point, so we can scale to the
-                # Compute scale so predicted graph is of same width as eval
+            # same range
-                measured_scaling = (eval_end -
+            tStartIdx = bisect.bisect_left(tStart, start)
-                                    eval_start) / Global['predict_last_end']
+            if tStartIdx >= len(tStart):
-                # Predict mtasks that fill the time the eval occupied
+                continue
-                for mtask in Mtasks:
+            start = tStart[tStartIdx]
-                    thread = Mtasks[mtask]['thread']
+            end = tEnd[bisect.bisect_right(tEnd, end) - 1]
-                    pred_scaled_start = eval_start + int(
+            # Compute scale so predicted graph is of same width as interval
-                        Mtasks[mtask]['predict_start'] * measured_scaling)
+            measured_scaling = (end - start) / Global['predict_last_end']
-                    pred_scaled_end = eval_start + int(
+            # Predict mtasks that fill the time the execution occupied
-                        (Mtasks[mtask]['predict_start'] +
+            for (hier_block, mtask_id) in Mtasks:
-                         Mtasks[mtask]['predict_cost']) * measured_scaling)
+                mtask = Mtasks[(hier_block, mtask_id)]
-                    if pred_scaled_start == pred_scaled_end:
+                thread = mtask['thread']
-                        continue
+                pred_scaled_start = start + int(mtask['predict_start'] * measured_scaling)
+                pred_scaled_end = start + int(
+                    (mtask['predict_start'] + mtask['predict_cost']) * measured_scaling)
+                if pred_scaled_start == pred_scaled_end:
+                    continue
 
-                    sig = "predicted_thread%d_mtask" % thread
+                mcode = getCode(32, 'predicted', 't%d_mtask' % thread)
-                    if sig not in vcd['sigs']['predicted_threads']:
+                addValue(mcode, pred_scaled_start, mtask_id)
-                        vcd['sigs']['predicted_threads'][sig] = code
+                addValue(mcode, pred_scaled_end, None)
-                        code += 1
-                    mcode = vcd['sigs']['predicted_threads'][sig]
 
-                    vcd['values'][pred_scaled_start][mcode] = mtask
+                parallelism['predicted'][pred_scaled_start] += 1
-                    vcd['values'][pred_scaled_end][mcode] = None
+                parallelism['predicted'][pred_scaled_end] -= 1
 
-                    parallelism['predicted'][pred_scaled_start] += 1
+        # Parallelism graph
-                    parallelism['predicted'][pred_scaled_end] -= 1
+        for measpred in ('measured', 'predicted'):
+            pcode = getCode(32, 'stats', '%s_parallelism' % measpred)
+            value = 0
+            for time in sorted(parallelism[measpred].keys()):
+                value += parallelism[measpred][time]
+                addValue(pcode, time, value)
 
-            # Parallelism graph
+        # Section graph
-            for measpred in ('measured', 'predicted'):
+        for thread, section in Sections.items():
-                vcd['sigs']['Stats']["%s_parallelism" % measpred] = code
+            if section:
-                pcode = code
+                scode = getCode(LongestVcdStrValueLength * 8, "section", f"t{thread}_trace")
-                code += 1
+                dcode = getCode(32, "section", f"t{thread}_depth")
-                value = 0
+                for time, stack in section:
-                for time in sorted(parallelism[measpred].keys()):
+                    addValue(scode, time, stack[-1] if stack else None)
-                    value += parallelism[measpred][time]
+                    addValue(dcode, time, len(stack))
-                    vcd['values'][time][pcode] = value
 
         # Create output file
         fh.write("$version Generated by verilator_gantt $end\n")
         fh.write("$timescale 1ns $end\n")
         fh.write("\n")
 
-        all_codes = {}
+        all_codes = set()
+
+        def writeScope(scope):
+            assert isinstance(scope, dict)
+            for key in sorted(scope):
+                val = scope[key]
+                if isinstance(val, dict):
+                    fh.write("  $scope module %s $end\n" % key)
+                    writeScope(val)
+                    fh.write("  $upscope $end\n")
+                else:
+                    (code, width) = val
+                    all_codes.add(code)
+                    fh.write("   $var wire %d v%x %s [%d:0] $end\n" %
+                             (width, code, key, width - 1))
+
         fh.write(" $scope module gantt $end\n")
-        for module in sorted(vcd['sigs'].keys()):
+        writeScope(scopeSigs)
-            fh.write("  $scope module %s $end\n" % module)
-            for sig in sorted(vcd['sigs'][module].keys()):
-                code = vcd['sigs'][module][sig]
-                fh.write("   $var wire 32 v%x %s [31:0] $end\n" % (code, sig))
-                all_codes[code] = 1
-            fh.write("  $upscope $end\n")
         fh.write(" $upscope $end\n")
         fh.write("$enddefinitions $end\n")
         fh.write("\n")
 
         first = True
-        for time in sorted(vcd['values']):
+        for time in sorted(values):
             if first:
                 first = False
                 # Start with Z for any signals without time zero data
-                for code in sorted(all_codes.keys()):
+                for code in sorted(all_codes):
-                    if code not in vcd['values'][time]:
+                    if code not in values[time]:
-                        vcd['values'][time][code] = None
+                        addValue(code, time, None)
             fh.write("#%d\n" % time)
-            for code in sorted(vcd['values'][time].keys()):
+            for code in sorted(values[time]):
-                value = vcd['values'][time][code]
+                value = values[time][code]
                 if value is None:
                     fh.write("bz v%x\n" % code)
+                elif value == 'x':
+                    fh.write("bx v%x\n" % code)
+                elif isinstance(value, str):
+                    fh.write("b%s v%x\n" % (value, code))
                 else:
                     fh.write("b%s v%x\n" % (format(value, 'b'), code))
 
@@ -475,7 +600,7 @@ def write_vcd(filename):
 parser = argparse.ArgumentParser(
     allow_abbrev=False,
     formatter_class=argparse.RawDescriptionHelpFormatter,
-    description="""Create Gantt chart of multi-threaded execution.
+    description="""Create Gantt chart of Verilator multi-threaded execution
 
 Verilator_gantt creates a visual representation to help analyze Verilator
 #xmultithreaded simulation performance, by showing when each macro-task
@@ -483,8 +608,7 @@ Verilator_gantt creates a visual representation to help analyze Verilator
 
 For documentation see
 https://verilator.org/guide/latest/exe_verilator_gantt.html""",
-    epilog=
+    epilog="""Copyright 2018-2025 by Wilson Snyder. This program is free software; you
-    """Copyright 2018-2023 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
@@ -492,19 +616,16 @@ Version 2.0.
 SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
 parser.add_argument('--debug', action='store_true', help='enable debug')
-parser.add_argument('--no-vcd',
+parser.add_argument('--no-vcd', help='disable creating vcd', action='store_true')
-                    help='disable creating vcd',
+parser.add_argument('--vcd', help='filename for vcd output', default='profile_exec.vcd')
-                    action='store_true')
-parser.add_argument('--vcd',
-                    help='filename for vcd outpue',
-                    default='profile_exec.vcd')
 parser.add_argument('filename',
                     help='input profile_exec.dat filename to process',
                     default='profile_exec.dat')
 
 Args = parser.parse_args()
 
-process(Args.filename)
+read_data(Args.filename)
+report()
 if not Args.no_vcd:
     write_vcd(Args.vcd)
 

bin/verilator_includer

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 # pylint: disable=C0114,C0209
 #
-# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify the Verilator internals under the terms
 # of either the GNU Lesser General Public License Version 3 or the Perl
 # Artistic License Version 2.0.

bin/verilator_profcfunc

@@ -34,9 +34,8 @@ def profcfunc(filename):
 
             # Older gprofs have no call column for single-call functions
             #                  %time      cumesec   selfsec      {stuff}   name
-            match = re.match(
+            match = re.match(r'^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$',
-                r'^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$',
+                             line)
-                line)
             if match:
                 pct = float(match.group(1))
                 sec = float(match.group(2))
@@ -136,19 +135,15 @@ def profcfunc(filename):
 
     design_width = 1
     for func, func_item in vfuncs.items():
-        if design_width < len(func_item['design']):
+        design_width = max(design_width, len(func_item['design']))
-            design_width = len(func_item['design'])
 
     print("Verilog code profile:")
     print("   These are split into three categories:")
     print("      C++:     Time in non-Verilated C++ code")
     print("      Prof:    Time in profile overhead")
-    print("      VBlock:  Time attributable to a block in a" +
+    print("      VBlock:  Time attributable to a block in a" + " Verilog file and line")
-          " Verilog file and line")
+    print("      VCommon: Time in a Verilated module," + " due to all parts of the design")
-    print("      VCommon: Time in a Verilated module," +
+    print("      VLib:    Time in Verilated common libraries," + " called by the Verilated code")
-          " due to all parts of the design")
-    print("      VLib:    Time in Verilated common libraries," +
-          " called by the Verilated code")
     print()
 
     print("  %   cumulative   self              ")
@@ -156,13 +151,11 @@ def profcfunc(filename):
            "s  type      filename and line number") % "design")
 
     cume = 0
-    for func in sorted(vfuncs.keys(),
+    for func in sorted(vfuncs.keys(), key=lambda f: vfuncs[f]['sec'], reverse=True):
-                       key=lambda f: vfuncs[f]['sec'],
-                       reverse=True):
         cume += vfuncs[func]['sec']
         print(("%6.2f %9.2f %8.2f %10d   %-" + str(design_width) + "s  %s") %
-              (vfuncs[func]['pct'], cume, vfuncs[func]['sec'],
+              (vfuncs[func]['pct'], cume, vfuncs[func]['sec'], vfuncs[func]['calls'],
-               vfuncs[func]['calls'], vfuncs[func]['design'], func))
+               vfuncs[func]['design'], func))
 
 
 ######################################################################
@@ -171,7 +164,7 @@ def profcfunc(filename):
 parser = argparse.ArgumentParser(
     allow_abbrev=False,
     formatter_class=argparse.RawDescriptionHelpFormatter,
-    description="""Read gprof report created with --prof-cfuncs.
+    description="""Read gprof report created with Verilator --prof-cfuncs
 
 Verilator_profcfunc reads a profile report created by gprof.  The names of
 the functions are then transformed, assuming the user used Verilator's
@@ -180,18 +173,14 @@ in each Verilog block.
 
 For documentation see
 https://verilator.org/guide/latest/exe_verilator_profcfunc.html""",
-    epilog=
+    epilog="""Copyright 2002-2025 by Wilson Snyder. This program is free software; you
-    """Copyright 2002-2023 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
 
 SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
-parser.add_argument('--debug',
+parser.add_argument('--debug', action='store_const', const=9, help='enable debug')
-                    action='store_const',
-                    const=9,
-                    help='enable debug')
 parser.add_argument('filename', help='input gprof output to process')
 
 Args = parser.parse_args()

ci/ci-ccache-maint.bash

@@ -26,4 +26,5 @@ if git log --format=%B -n 1 "$COMMIT" | grep -q -i '\[CI\s\+ccache\s\+clear\]';
 fi
 
 # Dump stats, then zero stats
+# 22.04: ccache -s -v -z
 ccache -s -z

ci/ci-install.bash

@@ -27,12 +27,6 @@ fatal() {
   echo "ERROR: $(basename "$0"): $1" >&2; exit 1;
 }
 
-if [ "$CI_M32" = "0" ]; then
-  unset CI_M32
-elif [ "$CI_M32" != "1" ]; then
-  fatal "\$CI_M32 must be '0' or '1'";
-fi
-
 if [ "$CI_OS_NAME" = "linux" ]; then
   MAKE=make
 elif [ "$CI_OS_NAME" = "osx" ]; then
@@ -46,7 +40,7 @@ fi
 install-vcddiff() {
   TMP_DIR="$(mktemp -d)"
   git clone https://github.com/veripool/vcddiff "$TMP_DIR"
-  git -C "${TMP_DIR}" checkout e5664be5fe39d353bf3fcb50aa05214ab7ed4ac4
+  git -C "${TMP_DIR}" checkout dca845020668887fd13498c772939814d9264fd5
   "$MAKE" -C "${TMP_DIR}"
   sudo cp "${TMP_DIR}/vcddiff" /usr/local/bin
 }
@@ -61,25 +55,18 @@ if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then
     sudo apt-get update
     sudo apt-get install ccache help2man libfl-dev ||
     sudo apt-get install ccache help2man libfl-dev
-    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ]; then
+    if [[ ! "$CI_RUNS_ON" =~ "ubuntu-22.04" ]]; then
       # Some conflict of libunwind verison on 22.04, can live without it for now
       sudo apt-get install libgoogle-perftools-dev ||
       sudo apt-get install libgoogle-perftools-dev
     fi
-    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ] || [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then
+    if [[ "$CI_RUNS_ON" =~ "ubuntu-20.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then
       sudo apt-get install libsystemc libsystemc-dev ||
       sudo apt-get install libsystemc libsystemc-dev
     fi
-    if [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then
+    if [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then
-      sudo apt-get install mold ||
+      sudo apt-get install bear mold ||
-      sudo apt-get install mold
+      sudo apt-get install bear mold
-    fi
-    if [ "$COVERAGE" = 1 ]; then
-      yes yes | sudo cpan -fi Parallel::Forker
-    fi
-    if [ "$CI_M32" = 1 ]; then
-      sudo apt-get install gcc-multilib g++-multilib ||
-      sudo apt-get install gcc-multilib g++-multilib
     fi
   elif [ "$CI_OS_NAME" = "osx" ]; then
     brew update
@@ -102,38 +89,31 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
     sudo apt-get update ||
     sudo apt-get update
     # libfl-dev needed for internal coverage's test runs
-    sudo apt-get install gdb gtkwave lcov libfl-dev ccache ||
+    sudo apt-get install gdb gtkwave lcov libfl-dev ccache jq z3 ||
-    sudo apt-get install gdb gtkwave lcov libfl-dev ccache
+    sudo apt-get install gdb gtkwave lcov libfl-dev ccache jq z3
-    # Required for test_regress/t/t_dist_attributes.pl
+    # Required for test_regress/t/t_dist_attributes.py
-    if [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then
+    if [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then
-      sudo apt-get install libclang-dev mold ||
+      sudo apt-get install python3-clang mold ||
-      sudo apt-get install libclang-dev mold
+      sudo apt-get install python3-clang mold
-      pip3 install clang==14.0
     fi
-    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ] || [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then
+    if [[ "$CI_RUNS_ON" =~ "ubuntu-20.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then
       sudo apt-get install libsystemc-dev ||
       sudo apt-get install libsystemc-dev
     fi
-    if [ "$CI_M32" = 1 ]; then
-      sudo apt-get install lib32z1-dev gcc-multilib g++-multilib ||
-      sudo apt-get install lib32z1-dev gcc-multilib g++-multilib
-    fi
   elif [ "$CI_OS_NAME" = "osx" ]; then
     brew update
     # brew cask install gtkwave # fst2vcd hangs at launch, so don't bother
-    brew install ccache perl
+    brew install ccache perl jq z3
   elif [ "$CI_OS_NAME" = "freebsd" ]; then
     # fst2vcd fails with "Could not open '<input file>', exiting."
-    sudo pkg install -y ccache gmake perl5 python3
+    sudo pkg install -y ccache gmake perl5 python3 jq z3
   else
     fatal "Unknown os: '$CI_OS_NAME'"
   fi
   # Common installs
-  if [ "$CI_RUNS_ON" != "ubuntu-14.04" ]; then
-    CI_CPAN_REPO=https://cpan.org
-  fi
-  yes yes | sudo cpan -M $CI_CPAN_REPO -fi Parallel::Forker
   install-vcddiff
+  # Workaround -fsanitize=address crash
+  sudo sysctl -w vm.mmap_rnd_bits=28
 else
   ##############################################################################
   # Unknown build stage

ci/ci-script.bash

@@ -21,12 +21,6 @@ fatal() {
   echo "ERROR: $(basename "$0"): $1" >&2; exit 1;
 }
 
-if [ "$CI_M32" = "0" ]; then
-  unset CI_M32
-elif [ "$CI_M32" != "1" ]; then
-  fatal "\$CI_M32 must be '0' or '1'";
-fi
-
 if [ "$CI_OS_NAME" = "linux" ]; then
   export MAKE=make
   NPROC=$(nproc)
@@ -39,6 +33,7 @@ elif [ "$CI_OS_NAME" = "freebsd" ]; then
 else
   fatal "Unknown os: '$CI_OS_NAME'"
 fi
+NPROC=$(expr $NPROC '+' 1)
 
 if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then
   ##############################################################################
@@ -46,9 +41,10 @@ if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then
 
   if [ "$COVERAGE" != 1 ]; then
     autoconf
-    ./configure --enable-longtests --enable-ccwarn ${CI_M32:+--enable-m32}
+    ./configure --enable-longtests --enable-ccwarn --prefix="$INSTALL_DIR"
     ccache -z
     "$MAKE" -j "$NPROC" -k
+    # 22.04: ccache -s -v
     ccache -s
     if [ "$CI_OS_NAME" = "osx" ]; then
       file bin/verilator_bin
@@ -66,6 +62,7 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
   # Run tests
 
   export VERILATOR_TEST_NO_CONTRIBUTORS=1  # Separate workflow check
+  export VERILATOR_TEST_NO_LINT_PY=1  # Separate workflow check
 
   if [ "$CI_OS_NAME" = "osx" ]; then
     export VERILATOR_TEST_NO_GDB=1  # Pain to get GDB to work on OS X
@@ -89,26 +86,48 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
     export VERILATOR_TEST_NO_GPROF=1 # gprof is a bit different on FreeBSD, disable
   fi
 
-  # Run sanitize on Ubuntu 20.04 only
+  # Run sanitize on Ubuntu 22.04 only
-  [ "$CI_RUNS_ON" = 'ubuntu-20.04' ] && [ "$CI_M32" = "" ] && sanitize='--sanitize' || sanitize=''
+  ( [[ "$CI_RUNS_ON" =~ 'ubuntu-22.04' ]] || [[ "$CI_RUNS_ON" =~ 'ubuntu-24.04' ]] ) && sanitize='--sanitize' || sanitize=''
+
+  TEST_REGRESS=test_regress
+  if [ "$CI_RELOC" == 1 ]; then
+     # Testing that the installation is relocatable.
+     "$MAKE" install
+     mkdir -p "$RELOC_DIR"
+     mv "$INSTALL_DIR" "$RELOC_DIR/relocated-install"
+     export VERILATOR_ROOT="$RELOC_DIR/relocated-install/share/verilator"
+     TEST_REGRESS="$RELOC_DIR/test_regress"
+     mv test_regress "$TEST_REGRESS"
+     NODIST="$RELOC_DIR/nodist"
+     mv nodist "$NODIST"
+     # Feeling brave?
+     find . -delete
+     ls -la .
+  fi
 
   # Run the specified test
   ccache -z
   case $TESTS in
     dist-vlt-0)
-      "$MAKE" -C test_regress SCENARIOS="--dist --vlt $sanitize" DRIVER_HASHSET=--hashset=0/3
+      "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt --driver-clean $sanitize" DRIVER_HASHSET=--hashset=0/4
       ;;
     dist-vlt-1)
-      "$MAKE" -C test_regress SCENARIOS="--dist --vlt $sanitize" DRIVER_HASHSET=--hashset=1/3
+      "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt --driver-clean $sanitize" DRIVER_HASHSET=--hashset=1/4
       ;;
     dist-vlt-2)
-      "$MAKE" -C test_regress SCENARIOS="--dist --vlt $sanitize" DRIVER_HASHSET=--hashset=2/3
+      "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt --driver-clean $sanitize" DRIVER_HASHSET=--hashset=2/4
+      ;;
+    dist-vlt-3)
+      "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt --driver-clean $sanitize" DRIVER_HASHSET=--hashset=3/4
       ;;
     vltmt-0)
-      "$MAKE" -C test_regress SCENARIOS=--vltmt DRIVER_HASHSET=--hashset=0/2
+      "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt --driver-clean" DRIVER_HASHSET=--hashset=0/3
       ;;
     vltmt-1)
-      "$MAKE" -C test_regress SCENARIOS=--vltmt DRIVER_HASHSET=--hashset=1/2
+      "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt --driver-clean" DRIVER_HASHSET=--hashset=1/3
+      ;;
+    vltmt-2)
+      "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt --driver-clean" DRIVER_HASHSET=--hashset=2/3
       ;;
     coverage-all)
       nodist/code_coverage --stages 1-
@@ -180,12 +199,12 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
       fatal "Unknown test: $TESTS"
       ;;
   esac
+
+  # To see load average (1 minute, 5 minute, 15 minute)
+  uptime
+  # 22.04: ccache -s -v
   ccache -s
 
-  # Upload coverage data
-  if [[ $TESTS == coverage-* ]]; then
-    bash <(cat ci/coverage-upload.sh) -f nodist/obj_dir/coverage/app_total.info
-  fi
 else
   ##############################################################################
   # Unknown build stage

ci/ci-win-compile.ps1

@@ -1,13 +1,26 @@
+# DESCRIPTION: Verilator: CI Windows Power Shell - Compile Verilator
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+#
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+################################################################################
+
+Set-PSDebug -Trace 1
+
 if (-Not (Test-Path $PWD/../.ccache/win_bison.exe)) {
-	git clone --depth 1 https://github.com/lexxmark/winflexbison
+    git clone --depth 1 https://github.com/lexxmark/winflexbison
-	cd winflexbison
+    cd winflexbison
-	mkdir build
+    mkdir build
-	cd build
+    cd build
-	cmake .. --install-prefix $PWD/../../../.ccache
+    cmake .. --install-prefix $PWD/../../../.ccache
-	cmake --build . --config Release -j 3
+    cmake --build . --config Release -j 3
-	cmake --install . --prefix $PWD/../../../.ccache
+    cmake --install . --prefix $PWD/../../../.ccache
-	cd ../..
+    cd ../..
 }
+
 mkdir build
 cd build
 cmake .. --install-prefix $PWD/../install

ci/ci-win-test.ps1

@@ -1,3 +1,16 @@
+# DESCRIPTION: Verilator: CI Windows Power Shell - Verilate a test
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+#
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+################################################################################
+
+
+Set-PSDebug -Trace 1
+
 cd install
 $Env:VERILATOR_ROOT=$PWD
 cd examples/cmake_tracing_c
@@ -5,6 +18,9 @@ mkdir build
 cd build
 cmake ..
 cmake --build . --config Release -j 3
-Release/example.exe
+
+# TODO put this back in, see issue# 5163
+# Release/example.exe
+
 cd ..
 Remove-Item -path build -recurse

ci/docker/buildenv/Dockerfile

@@ -6,7 +6,17 @@
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-FROM ubuntu:22.04
+FROM ubuntu:24.04
+
+# Create the user
+RUN groupadd verilator \
+    && useradd -g verilator -m verilator -s /bin/bash \
+    && apt-get update \
+    && apt-get install --no-install-recommends -y sudo \
+    && apt-get clean \
+    && rm -rf /var/lib/apt/lists/* \
+    && echo verilator ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/verilator \
+    && chmod 0440 /etc/sudoers.d/verilator
 
 RUN apt-get update \
     && DEBIAN_FRONTEND=noninteractive \
@@ -26,14 +36,16 @@ RUN apt-get update \
                         help2man \
                         libfl2 \
                         libfl-dev \
+                        libclang-rt-18-dev \
                         libgoogle-perftools-dev \
                         libsystemc \
                         libsystemc-dev \
                         numactl \
                         perl \
                         python3 \
+                        python3-distro \
                         wget \
-                        zlibc \
+                        z3 \
                         zlib1g \
                         zlib1g-dev \
     && apt-get clean \
@@ -41,8 +53,6 @@ RUN apt-get update \
 
 WORKDIR /tmp
 
-RUN cpan install -fi Parallel::Forker
-
 RUN git clone https://github.com/veripool/vcddiff.git && \
     make -C vcddiff && \
     cp -p vcddiff/vcddiff /usr/local/bin/vcddiff && \
@@ -52,6 +62,8 @@ COPY build.sh /tmp/build.sh
 
 ENV VERILATOR_AUTHOR_SITE=1
 
+USER verilator
+
 WORKDIR /work
 
 ENTRYPOINT [ "/tmp/build.sh" ]

ci/docker/buildenv/README.rst

@@ -1,6 +1,8 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
+.. _Verilator Build Docker Container:
+
 Verilator Build Docker Container
 ================================
 
@@ -11,7 +13,7 @@ Verilator build. It uses the following parameters:
 
 -  Source revision (default: master)
 
--  Compiler (GCC 10.3.0, clang 10.0.0, default: 10.3.0)
+-  Compiler (GCC 13.3.0, clang 18.1.3, default: 13.3.0)
 
 The container is published as ``verilator/verilator-buildenv`` on `docker
 hub
@@ -29,18 +31,18 @@ To also run tests:
 
    docker run -ti verilator/verilator-buildenv test
 
-To change the compiler:
+To change the compiler use the `-e` switch to pass environment variables:
 
 ::
 
-   docker run -ti -e CC=clang-10 -e CXX=clang++-10 verilator/verilator-buildenv test
+   docker run -ti -e CC=clang-18 -e CXX=clang++-18 verilator/verilator-buildenv test
 
-The tests that involve gdb are not working due to security restrictions.
+The tests, that involve numactl are not working due to security restrictions.
-To run those too:
+To run those too, add the CAP_SYS_NICE capability during the start of the container:
 
 ::
 
-   docker run -ti -e CC=clang-10 -e CXX=clang++-10 --cap-add=SYS_PTRACE --security-opt seccomp=unconfined verilator/verilator-buildenv test
+   docker run -ti --cap-add=CAP_SYS_NICE verilator/verilator-buildenv test
 
 Rather then building using a remote git repository you may prefer to use a
 working copy on the local filesystem. Mount the local working copy path as
@@ -50,7 +52,7 @@ top of a repository:
 
 ::
 
-   docker run -ti -v ${PWD}:/tmp/repo -e REPO=/tmp/repo -e REV=`git rev-parse --short HEAD` --cap-add=SYS_PTRACE --security-opt seccomp=unconfined verilator/verilator-buildenv test
+   docker run -ti -v ${PWD}:/tmp/repo -e REPO=/tmp/repo -e REV=`git rev-parse --short HEAD` verilator/verilator-buildenv test
 
 
 Rebuilding

ci/docker/run/Dockerfile

@@ -6,7 +6,7 @@
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-FROM ubuntu:22.04
+FROM ubuntu:24.04
 
 RUN apt-get update \
     && DEBIAN_FRONTEND=noninteractive \
@@ -48,7 +48,8 @@ RUN git clone "${REPO}" verilator && \
     make && \
     make install && \
     cd .. && \
-    rm -r verilator
+    rm -r verilator && \
+    ccache -C
 
 COPY verilator-wrap.sh /usr/local/bin/verilator-wrap.sh
 

ci/docker/run/README.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 Verilator Executable Docker Container
@@ -11,10 +11,11 @@ easily as a docker image, e.g.:
 
    docker run -ti verilator/verilator:latest --version
 
-This will install the container, run the latest Verilator and print
+This will pull the container from `docker hub
+<https://hub.docker.com/r/verilator/verilator>`_, run the latest Verilator and print
 Verilator's version.
 
-Containers are automatically built for all released versions, so you may
+Containers are automatically built and pushed to docker hub for all released versions, so you may
 easily compare results across versions, e.g.:
 
 ::

codecov.yml

@@ -1,6 +1,7 @@
+---
 # DESCRIPTION: codecov.io config
 #
-# Copyright 2020-2023 by Wilson Snyder. This program is free software; you
+# Copyright 2020-2025 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -8,31 +9,28 @@
 ####################
 # Validate:
 #  curl --data-binary @codecov.yml https://codecov.io/validate
-
+#
 codecov:
-  require_ci_to_pass: no
+  require_ci_to_pass: false
-
 coverage:
   precision: 2
   round: down
-  range: "50...100"
+  range: 50...100
   ignore:
-    - "ci"
+    - "ci"  #
-    - "docs"
+    - "docs"  #
-    - "examples"
+    - "examples"  #
-    - "include/gtkwave"
+    - "include/gtkwave"  #
-    - "include/vltstd"
+    - "include/vltstd"  #
-    - "test_regress"
+    - "test_regress"  #
-
 parsers:
   gcov:
     branch_detection:
-      conditional: yes
+      conditional: true
-      loop: yes
+      loop: true
-      method: no
+      method: false
-      macro: no
+      macro: false
-
 comment:
   layout: "reach,diff,flags,tree"
   behavior: default
-  require_changes: yes
+  require_changes: true

configure.ac

@@ -1,16 +1,17 @@
 # DESCRIPTION: Process this file with autoconf to produce a configure script.
 #
-# Copyright 2003-2023 by Wilson Snyder. Verilator is free software; you
+# Copyright 2003-2025 by Wilson Snyder. Verilator is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU Lesser
 # General Public License Version 3 or the Perl Artistic License Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-# When releasing, also update header of Changes file, and CmakeLists.txt,
+# When releasing, also update header of Changes file, and CMakeLists.txt,
 # and commit using "devel release" or "Version bump" message
+# Then 'make distclean' 'autoconf' './configure' 'make' 'make test'
 # Then 'make maintainer-dist'
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[5.014 2023-08-06],
+AC_INIT([Verilator],[5.040 2025-08-30],
         [https://verilator.org],
         [verilator],[https://verilator.org])
 
@@ -24,6 +25,13 @@ AC_SUBST(PACKAGE_VERSION_NUMBER)
 AC_DEFINE_UNQUOTED([PACKAGE_VERSION_NUMBER_STRING],["$PACKAGE_VERSION_NUMBER"],[Package version as a number])
 VERILATOR_VERSION_INTEGER=`AS_ECHO("$PACKAGE_VERSION") | [sed 's/\([0-9]\)\.\([0-9][0-9][0-9]\) .*/\1\2000/g']`
 AC_SUBST(VERILATOR_VERSION_INTEGER)
+AC_DEFINE_UNQUOTED([PACKAGE_VERSION_STRING_CHAR],
+        [static const char* const PACKAGE_STRING_UNUSED = "$PACKAGE_STRING";],
+        [Package version as a number])
+AC_SUBST(PACKAGE_VERSION_STRING_CHAR)
+
+######################################################################
+## Arguments/flag checking
 
 # Ignore automake flags passed by Ubuntu builds
 AC_ARG_ENABLE([dependency-tracking],
@@ -61,22 +69,9 @@ AC_ARG_ENABLE([tcmalloc],
                 *)   AC_MSG_ERROR([bad value '${enableval}' for --enable-tcmalloc]) ;;
                esac],
               [CFG_WITH_TCMALLOC=check;])
+AC_SUBST(CFG_WITH_TCMALLOC)
 AC_MSG_RESULT($CFG_WITH_TCMALLOC)
 
-# Flag to enable -m32 build
-AC_MSG_CHECKING(whether to use -m32)
-AC_ARG_ENABLE([m32],
-              [AS_HELP_STRING([--enable-m32],
-                              [Use -m32 for all compilation and link,
-                               including Verilator and generated models.])],
-              [case "${enableval}" in
-                yes) CFG_ENABLE_M32=yes ;;
-                no)  CFG_ENABLE_M32=no ;;
-                *)   AC_MSG_ERROR([bad value '${enableval}' for --enable-m32]) ;;
-               esac],
-               CFG_ENABLE_M32=no)
-AC_MSG_RESULT($CFG_ENABLE_M32)
-
 # Flag to enable coverage build
 AC_MSG_CHECKING(whether to build for coverage collection)
 AC_ARG_ENABLE([coverage],
@@ -144,6 +139,33 @@ AC_ARG_ENABLE([longtests],
 AC_SUBST(CFG_WITH_LONGTESTS)
 AC_MSG_RESULT($CFG_WITH_LONGTESTS)
 
+AC_CHECK_PROG(HAVE_Z3,z3,yes)
+AC_CHECK_PROG(HAVE_CVC5,cvc5,yes)
+AC_CHECK_PROG(HAVE_CVC4,cvc4,yes)
+
+# Special Substitutions - CFG_WITH_SOLVER
+AC_MSG_CHECKING(for SMT solver)
+AC_ARG_WITH([solver],
+              [AS_HELP_STRING([--with-solver='z3 --in'],
+                              [set default SMT solver for constrained randomization])],
+              [CFG_WITH_SOLVER="${withval}"],
+              [CFG_WITH_SOLVER=no
+               if test "x$HAVE_Z3" = "xyes"; then
+                CFG_WITH_SOLVER="z3 --in"
+               elif test "x$HAVE_CVC5" = "xyes"; then
+                CFG_WITH_SOLVER="cvc5 --incremental"
+               elif test "x$HAVE_CVC4" = "xyes"; then
+                CFG_WITH_SOLVER="cvc4 --lang=smt2 --incremental"
+               fi]
+              )
+AC_SUBST(CFG_WITH_SOLVER)
+AC_MSG_RESULT($CFG_WITH_SOLVER)
+
+######################################################################
+## Compiler checks
+
+AC_MSG_RESULT([compiler CXX inbound is set to... $CXX])
+
 # Compiler flags (ensure they are not empty to avoid configure defaults)
 CFLAGS="$CFLAGS "
 CPPFLAGS="$CPPFLAGS "
@@ -156,8 +178,10 @@ AC_PROG_CXX
 AC_PROG_INSTALL
 
 AC_LANG_PUSH(C++)
-cxx_version=$($CXX --version | head -1)
+CFG_CXX_VERSION=`$CXX --version | head -1`
-AC_MSG_RESULT([compiler is $CXX --version = $cxx_version])
+AC_MSG_RESULT([compiler version... $CXX --version = $CFG_CXX_VERSION])
+AC_SUBST(CFG_CXX_VERSION)
+
 AC_MSG_CHECKING([that C++ compiler can compile simple program])
 AC_RUN_IFELSE(
    [AC_LANG_SOURCE([int main() { return 0; }])],
@@ -170,24 +194,26 @@ if test "x$AR" = "x" ; then
    AC_MSG_ERROR([Cannot find "ar" in your PATH, please install it])
 fi
 
-AC_PATH_PROG(PERL,perl)
+AC_CHECK_PROG(PERL,perl,perl)
 if test "x$PERL" = "x" ; then
    AC_MSG_ERROR([Cannot find "perl" in your PATH, please install it])
 fi
 
-AC_PATH_PROG(PYTHON3,python3)
+AC_CHECK_PROG(PYTHON3,python3,python3)
 if test "x$PYTHON3" = "x" ; then
    AC_MSG_ERROR([Cannot find "python3" in your PATH, please install it])
 fi
+python3_version=$($PYTHON3 --version | head -1)
+AC_MSG_RESULT([$PYTHON3 --version = $python3_version])
 
-AC_PATH_PROG(LEX,flex)
+AC_CHECK_PROG(LEX,flex,flex)
 if test "x$LEX" = "x" ; then
    AC_MSG_ERROR([Cannot find "flex" in your PATH, please install it])
 fi
 flex_version=$($LEX --version | head -1)
 AC_MSG_RESULT([$LEX --version = $flex_version])
 
-AC_PATH_PROG(YACC,bison)
+AC_CHECK_PROG(YACC,bison,bison)
 if test "x$YACC" = "x" ; then
    AC_MSG_ERROR([Cannot find "bison" in your PATH, please install it])
 fi
@@ -276,6 +302,43 @@ AC_DEFUN([_MY_CXX_CHECK_OPT],
     _MY_CXX_CHECK_IFELSE($2, $1="$$1 $2")
    ])
 
+AC_DEFUN([_MY_CXX_CHECK_CORO_SET],
+   [# _MY_CXX_CHECK_CORO_SET(variable,option)
+    # Check if compiler supports coroutines with specific option. If it does,
+    # set variable to option, only if not previously set.
+    # Define HAVE_COROUTINES if supported.
+    if test "$$1" = ""; then
+      if test "$2" != ""; then
+        _my_msg_opt=" with $2"
+      else
+        _my_msg_opt=""
+      fi
+      AC_MSG_CHECKING([whether coroutines are supported by $CXX$_my_msg_opt])
+      ACO_SAVE_CXXFLAGS="$CXXFLAGS"
+      CXXFLAGS="$CXXFLAGS $2"
+      AC_LINK_IFELSE(
+         [AC_LANG_PROGRAM([
+            #if defined(__clang__) && !defined(__cpp_impl_coroutine)
+            #define __cpp_impl_coroutine 1
+            #endif
+            #include <coroutine>
+          ],[[std::coroutine_handle<> h;]])],
+         [_my_result=yes],
+         [AC_LINK_IFELSE(
+             [AC_LANG_PROGRAM(
+                [#include <experimental/coroutine>],
+                [[std::experimental::coroutine_handle<> h;]])],
+             [_my_result=yes],
+             [_my_result=no])])
+      AC_MSG_RESULT($_my_result)
+      CXXFLAGS="$ACO_SAVE_CXXFLAGS"
+      if test "$_my_result" = "yes" ; then
+        $1="$2"
+        AC_DEFINE([HAVE_COROUTINES],[1],[Defined if coroutines are supported by $CXX])
+      fi
+    fi
+  ])
+
 AC_DEFUN([_MY_LDLIBS_CHECK_FLAG],
    [# _MY_LDLIBS_CHECK_FLAG(flag) -- Check if linker supports specific options
     # Set $_my_result appropriately
@@ -315,15 +378,7 @@ AC_DEFUN([_MY_LDLIBS_CHECK_OPT],
     _MY_LDLIBS_CHECK_IFELSE($2, $1="$$1 $2")
    ])
 
-# When using -m32. Check this first as later checks may fail with the -m32 flag.
+# Add the coverage flags early as they influence later checks.
-if test "$CFG_ENABLE_M32" = "yes"; then
-  _MY_CXX_CHECK_IFELSE(
-    -m32,
-    [CXX="$CXX -m32"],
-    [AC_MSG_ERROR([--enable-m32 was given but compiler does not support -m32])])
-fi
-
-# Similarly, add the coverage flags early as they influence later checks.
 if test "$CFG_ENABLE_COVERAGE" = "yes"; then
   _MY_CXX_CHECK_OPT(CXX,--coverage)
   # Otherwise inline may not show as uncovered
@@ -350,7 +405,7 @@ AC_SUBST(CFG_CXXFLAGS_PROFILE)
 # Macros work such that first option that passes is the one we take
 # Currently enable c++17/c++14 due to packaged SystemC dependency
 # c++17 is the newest that Verilator is regularly tested to support
-# c++11 is the oldest that Verilator supports
+# c++14 is the oldest that Verilator supports
 # gnu is required for Cygwin to compile verilated.h successfully
 #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++20)
 #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++20)
@@ -358,8 +413,6 @@ _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++17)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++14)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++14)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++11)
 AC_SUBST(CFG_CXXFLAGS_STD_NEWEST)
 
 # Flags for compiling Verilator internals including parser, and Verilated files
@@ -371,40 +424,20 @@ _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_WEXTRA,-Wthread-safety)
 AC_SUBST(CFG_CXXFLAGS_WEXTRA)
 
 # Flags for coroutine support for dynamic scheduling
-_MY_CXX_CHECK_IFELSE(
+_MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES, "")
-  -fcoroutines-ts,
+_MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES,-fcoroutines-ts)
-  [CFG_CXXFLAGS_COROUTINES="-fcoroutines-ts"],
+_MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES,-fcoroutines)
-  [CFG_CXXFLAGS_COROUTINES="-fcoroutines"])
+_MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES,-fcoroutines-ts -Wno-deprecated-experimental-coroutine)
+_MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES,-std=gnu++20)
 AC_SUBST(CFG_CXXFLAGS_COROUTINES)
-
-# HAVE_COROUTINES
-# Check if coroutines are supported at all
-AC_MSG_CHECKING([whether coroutines are supported by $CXX])
-ACO_SAVE_CXXFLAGS="$CXXFLAGS"
-CXXFLAGS="$CXXFLAGS $CFG_CXXFLAGS_COROUTINES"
-AC_LINK_IFELSE(
-    [AC_LANG_PROGRAM([
-#ifdef __clang__
-#define __cpp_impl_coroutine 1
-#endif
-#include <coroutine>
-    ],[[]])],
-    [_my_result=yes
-     AC_DEFINE([HAVE_COROUTINES],[1],[Defined if coroutines are supported by $CXX])],
-    [AC_LINK_IFELSE(
-        [AC_LANG_PROGRAM([#include <experimental/coroutine>],[[]])],
-        [_my_result=yes
-         AC_DEFINE([HAVE_COROUTINES],[1],[Defined if coroutines are supported by $CXX])],
-        [_my_result=no])])
-AC_MSG_RESULT($_my_result)
-CXXFLAGS="$ACO_SAVE_CXXFLAGS"
 AC_SUBST(HAVE_COROUTINES)
 
 # Flags for compiling Verilator internals including parser always
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Qunused-arguments)
-_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-faligned-new)
-_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-unused-parameter)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-shadow)
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-unused-parameter)
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Xclang -fno-pch-timestamp)
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-faligned-new)
 AC_SUBST(CFG_CXXFLAGS_SRC)
 
 # Flags for compiling Verilator parser always (in addition to above CFG_CXXFLAGS_SRC)
@@ -439,17 +472,25 @@ CFG_CXX_FLAGS_CMAKE="-faligned-new"
 m4_foreach([cflag],[
         [-fbracket-depth=4096],
         [-fcf-protection=none],
+        [-Xclang -fno-pch-timestamp],
         [-mno-cet],
         [-Qunused-arguments],
         [-Wno-bool-operation],
-        [-Wno-tautological-bitwise-compare],
+        [-Wno-c++11-narrowing],
+        [-Wno-constant-logical-operand],
+        [-Wno-int-in-bool-context],
+        [-Wno-non-pod-varargs],
         [-Wno-parentheses-equality],
+        [-Wno-shadow],
         [-Wno-sign-compare],
+        [-Wno-subobject-linkage],
+        [-Wno-tautological-bitwise-compare],
+        [-Wno-tautological-compare],
         [-Wno-uninitialized],
+        [-Wno-unused-but-set-parameter],
         [-Wno-unused-but-set-variable],
         [-Wno-unused-parameter],
-        [-Wno-unused-variable],
+        [-Wno-unused-variable]],[
-        [-Wno-shadow]],[
     _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,cflag)
     # CMake will test what flags work itself, so pass all flags through to it
     CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE cflag"
@@ -479,7 +520,7 @@ if test "$CFG_ENABLE_PARTIAL_STATIC" = "yes"; then
   _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -static-libgcc)
   _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -static-libstdc++)
   _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -Xlinker -gc-sections)
-  LTCMALLOC=-l:libtcmalloc_minimal.a
+  LTCMALLOC="-Wl,--whole-archive -l:libtcmalloc_minimal.a -Wl,--no-whole-archive"
 else
   LTCMALLOC=-ltcmalloc_minimal
 fi
@@ -491,6 +532,7 @@ AC_SUBST(CFG_LDFLAGS_VERILATED)
 # pthreads is harmless otherwise.
 CFG_LIBS="$LIBS $CFG_LIBS"
 _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lpthread)
+_MY_LDLIBS_CHECK_OPT(CFG_LIBS, -latomic)
 
 # Check libraries for MingW
 _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lbcrypt)
@@ -502,25 +544,27 @@ _MY_LDLIBS_CHECK_IFELSE(
   [if test "$CFG_WITH_TCMALLOC" != "no"; then
     CFG_LIBS="$LTCMALLOC $CFG_LIBS";
     # If using tcmalloc, add some extra options to make the compiler not assume
-    # it is using it's own versions of the standard library functions
+    # it is using its own versions of the standard library functions
     _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-malloc)
     _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-calloc)
     _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-realloc)
     _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-free)
+    AC_DEFINE([HAVE_TCMALLOC],[1],[Defined if have tcmalloc])
    fi],
   [if test "$CFG_WITH_TCMALLOC" = "yes"; then
     AC_MSG_ERROR([--enable-tcmalloc was given but test for ${LTCMALLOC} failed])
    fi])
+AC_SUBST(HAVE_TCMALLOC)
 AC_SUBST(CFG_LIBS)
 
-# Need C++11 at least
+# Need C++14 at least
-#Alternative: AX_CXX_COMPILE_STDCXX([11])
+#Alternative: AX_CXX_COMPILE_STDCXX([14])
 AC_DEFUN([_MY_CXX_CHECK_CXX_VER],
-   [# _MY_CXX_CHECK_CXX_VER(flag) -- Check if compiler runs C++11
+   [# _MY_CXX_CHECK_CXX_VER(flag) -- Check if compiler runs C++14
     # Set $_my_result
     AC_LINK_IFELSE(
      [AC_LANG_PROGRAM([#include <thread>
-#if (__cplusplus < 201103L)
+#if (__cplusplus < 201402L)
 # error "Too old"
 #endif
     ], [[ ]])],
@@ -536,13 +580,13 @@ AC_DEFUN([_MY_CXX_CHECK_CXX_VER],
 # Add $CFG_CXXFLAGS_STD only if can't compile correctly otherwise,
 # as adding std= when not needed can cause errors with the C++ std library.
 CFG_CXXFLAGS_STD=$CFG_CXXFLAGS_STD_NEWEST
-AC_MSG_CHECKING(whether $CXX supports C++11)
+AC_MSG_CHECKING(whether $CXX supports C++14)
 _MY_CXX_CHECK_CXX_VER()
 AC_MSG_RESULT($_my_result)
 if test "$_my_result" = "no" ; then
    CXXFLAGS="$CXXFLAGS $CFG_CXXFLAGS_STD"
    CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE $CFG_CXXFLAGS_STD"
-   AC_MSG_CHECKING(whether $CXX supports C++11 with $CFG_CXXFLAGS_STD)
+   AC_MSG_CHECKING(whether $CXX supports C++14 with $CFG_CXXFLAGS_STD)
    _MY_CXX_CHECK_CXX_VER()
    AC_MSG_RESULT($_my_result)
 else
@@ -552,13 +596,28 @@ else
 fi
 if test "$_my_result" = "no" ; then
    AC_MSG_NOTICE([[]])
-   AC_MSG_ERROR([[the $CXX compiler appears to not support C++11.
+   AC_MSG_ERROR([[the $CXX compiler appears to not support C++14.
 
-Verilator requires a C++11 or newer compiler.]])
+Verilator requires a C++14 or newer compiler.]])
 
 fi
 AC_SUBST(CFG_CXXFLAGS_STD)
 
+# Compiler precompiled header options (assumes either gcc or clang++)
+AC_MSG_CHECKING([for $CXX precompile header include option])
+if $CXX --help | grep include-pch >/dev/null 2>/dev/null ; then
+   # clang
+   CFG_CXXFLAGS_PCH_I=-include-pch
+   CFG_GCH_IF_CLANG=.gch
+else
+   # GCC
+   CFG_CXXFLAGS_PCH_I=-include
+   CFG_GCH_IF_CLANG=
+fi
+AC_MSG_RESULT($CFG_CXXFLAGS_PCH_I)
+AC_SUBST(CFG_CXXFLAGS_PCH_I)
+AC_SUBST(CFG_GCH_IF_CLANG)
+
 # Checks for library functions.
 AC_CHECK_MEMBER([struct stat.st_mtim.tv_nsec],
     [AC_DEFINE([HAVE_STAT_NSEC],[1],[Defined if struct stat has st_mtim.tv_nsec])],
@@ -573,7 +632,7 @@ ACO_SAVE_LIBS="$LIBS"
 LIBS="$LIBS -lsystemc"
 AC_LINK_IFELSE(
     [AC_LANG_PROGRAM([[#include <systemc.h>
-                     extern "C" int sc_main(int argc, char* argv[]) {}
+                     extern "C" int sc_main(int argc, char* argv[]) { return 0; }
                      ]],[[sc_version()]])],
     [_my_result=yes
      AC_DEFINE([HAVE_SYSTEMC],[1],[Defined if have SystemC library])],
@@ -584,6 +643,9 @@ AC_SUBST(HAVE_SYSTEMC)
 
 # Checks for system services
 
+######################################################################
+## Output
+
 # Other install directories
 pkgdatadir=${datadir}/verilator
 AC_SUBST(pkgdatadir)

docs/CONTRIBUTING.rst

@@ -7,8 +7,8 @@ This contributing document contains some suggestions that may make
 contributions flow more efficiently.
 
 
-Did you find a bug?
+Did you find a Verilator bug?
--------------------
+-----------------------------
 
 - Please **ensure the bug was not already reported** by searching
   `Verilator Issues <https://verilator.org/issues>`__.
@@ -28,8 +28,8 @@ Did you find a bug?
     <https://github.com/verilator/verilator/blob/master/docs/internals.rst>`__.
 
 
-Did you write a patch that fixes a bug?
+Did you write a patch that fixes a Verilator bug?
----------------------------------------
+-------------------------------------------------
 
 - Please `Open a new Verilator issue <https://verilator.org/issues/new>`__
   if there is not one already describing the bug.
@@ -72,8 +72,8 @@ Did you write a patch that fixes a bug?
 - Most important is we get your patch.
 
 
-Do you have questions?
+Do you have questions on Verilator?
-----------------------
+-----------------------------------
 
 - Please see FAQ section and rest of the `Verilator
   manual <https://verilator.org/verilator_doc.html>`__, or `Verilator

docs/CONTRIBUTORS

@@ -3,52 +3,83 @@ under the Developer Certificate of Origin (https://developercertificate.org/).
 
 Please see the Verilator manual for 200+ additional contributors. Thanks to all.
 
+404allen404
 Adam Bagley
+Adrian Sampson
 Adrien Le Masle
 Ahmed El-Mahmoudy
+Aidan McNay
 Aleksander Kiryk
 Alex Chadwick
-Àlex Torregrosa
+Alex Solomatnikov
 Aliaksei Chapyzhenka
 Ameya Vikram Singh
+Andrea Calabrese
 Andreas Kuster
 Andrei Kostovski
 Andrew Miloradovsky
 Andrew Nolte
+Andrew Voznytsa
 Anthony Donlon
+Anthony Moore
 Arkadiusz Kozdra
+Arthur Rosa
+Artur Bieniek
 Aylon Chaim Porat
+Bartłomiej Chmiel
+Brian Li
 Cameron Kirk
+Chih-Mao Chen
+Chris Bachhuber
 Chris Randall
+Christopher Taylor
 Chuxuan Wang
+Chykon
+Congcong Cai
 Conor McCullough
 Dan Petrisko
+Danny Oler
 Daniel Bates
+Dave Sargeant
 David Horton
+David Ledger
 David Metz
 David Stanford
 David Turner
+Dercury
+Diego Roux
+Dominick Grochowina
 Don Williamson
 Drew Ranck
 Drew Taussig
 Driss Hafdi
 Edgar E. Iglesias
+Eric Müller
 Eric Rippey
 Ethan Sifferman
 Eyck Jentzsch
+Fabian Keßler
 Fan Shupei
-february cozzocrea
 Felix Neumärker
 Felix Yan
+Frans Skarman
+Fuad Ismail
+Furqan Nadir
 G-A. Kamendje
 Garrett Smith
+George Polack
 Geza Lore
 Gianfranco Costamagna
+Gijs Burghoorn
+Gilberto Abram
 Glen Gibb
-Gökçe Aydos
 Graham Rushton
+Greg Davill
 Guokai Chen
+Gus Smith
 Gustav Svensk
+Gökçe Aydos
+Han Qi
 Harald Heckmann
 Hennadii Chernyshchyk
 Howard Su
@@ -56,11 +87,14 @@ Huang Rui
 Huanghuang Zhou
 HungMingWu
 HyungKi Jeong
+Ibrahim Burak Yorulmaz
+Igor Zaworski
 Ilya Barkov
 Iru Cai
 Ivan Vnučec
 Iztok Jeras
 Jake Merdich
+James Bailey
 James Hanlon
 James Hutchinson
 James Pallister
@@ -74,12 +108,19 @@ Jesse Taube
 Jevin Sweval
 Jiacheng Qian
 Jiamin Zhu
+Jiangjie Weng
+Jinyan Xu
+Jitesh Nayak
 Jiuyang Liu
+Joel Bodenmann
 Joey Liu
 John Coiner
 John Demme
+John Khoo
 John Wehle
 Jonathan Drolet
+Jonathan Schröter
+Jordan McConnon
 Jose Loyola
 Josep Sans
 Joseph Nwabueze
@@ -87,17 +128,25 @@ Josh Redford
 Julian Daube
 Julie Schwartz
 Julien Margetts
+Justin Thiel
 Kaleb Barrett
 Kamil Rakoczy
 Kanad Kanhere
+Kefa Chen
 Keith Colbert
 Kevin Kiningham
+Kevin Nygaard
 Kritik Bhimani
 Krzysztof Bieganski
 Krzysztof Boronski
 Krzysztof Boroński
+Krzysztof Obłonczek
+Krzysztof Starecki
+Krzysztof Sychla
 Kuba Ober
 Larry Doolittle
+Liam Braun
+Luca Colagrande
 Ludwig Rogiers
 Lukasz Dalek
 Maarten De Braekeleer
@@ -110,58 +159,90 @@ Marlon James
 Marshal Qiao
 Martin Schmidt
 Martin Stadler
+Mateusz Gancarz
 Matthew Ballance
+Max Wipfli
+Michael Bedford Taylor
+Michael Bikovitsky
 Michael Killough
+Michal Czyz
 Michaël Lefebvre
 Mike Popoloski
 Miodrag Milanović
 Mladen Slijepcevic
 Morten Borup Petersen
 Mostafa Gamal
+Moubarak Jeje
 Nandu Raj
+Natan Kreimer
+Nathan Graybeal
 Nathan Kohagen
 Nathan Myers
+Nick Brereton
+Nolan Poe
 Oleh Maksymenko
 Patrick Stewart
+Paul Bowen-Huggett
+Paul Swirhun
 Paul Wright
+Pawel Jewstafjew
 Pawel Sagan
+Pengcheng Xu
+Peter Birch
 Peter Debacker
 Peter Horvath
 Peter Monsson
+Petr Nohavica
+Philip Axer
 Philipp Wagner
 Pierre-Henri Horrein
 Pieter Kapsenberg
 Piotr Binkowski
 Qingyao Sun
+Quentin Corradi
 Rafal Kapuscik
+Rasfunk
 Raynard Qiao
+Ricardo Barbedo
 Richard Myers
 Risto Pejašinović
 Robert Balas
+Robin Heinemann
+Rodrigo Batista de Moraes
 Rupert Swarbrick
+Ryan Ziegler
 Ryszard Rozak
 Samuel Riedel
 Sean Cross
 Sebastien Van Cauwenberghe
+Sergey Fedorov
 Sergi Granell
+Seth Pellegrino
+Shou-Li Hsu
 Srinivasan Venkataramanan
 Stefan Wallentowitz
 Stephen Henry
 Steven Hugg
+Szymon Gizler
 Sören Tempel
 Teng Huang
 Tim Hutt
 Tim Snyder
+Tobias Jensen
 Tobias Rosenkranz
 Tobias Wölfel
 Todd Strader
+Tom Manner
 Tomasz Gorochowik
 Topa Topino
 Toru Niina
+Trung Nguyen
 Tudor Timi
 Tymoteusz Blazejczyk
+Udaya Raj Subedi
 Udi Finkelstein
 Unai Martinez-Corral
+Valentin Atepalikhin
 Varun Koyyalagunta
 Vassilis Papaefstathiou
 Veripool API Bot
@@ -170,6 +251,9 @@ Vito Gamberini
 William D. Jones
 Wilson Snyder
 Xi Zhang
+Yan Xu
+Yangyu Chen
+Yilou Wang
 Yinan Xu
 Yoda Lee
 Yossi Nivin
@@ -178,5 +262,11 @@ Yuri Victorovich
 Yutetsu TAKATSUKASA
 Yves Mathieu
 Zhanglei Wang
+Zhen Yan
+Zhou Shen
+Zhouyi Shen
 Zixi Li
-أحمد المحمودي
+february cozzocrea
+sumpster
+Àlex Torregrosa
+Ícaro Lima

docs/Makefile

@@ -5,7 +5,7 @@
 #
 # Code available from: https://verilator.org
 #
-# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -23,9 +23,9 @@ SPHINXBUILD ?= sphinx-build
 SOURCEDIR = guide
 BUILDDIR = _build
 
-SPHINXOPTS ?= -c guide
+SPHINXOPTS ?= -c guide -j 4
 ifneq ($(VERILATOR_ANALYTICS_ID),)
-SPHINXOPTS += -D html_theme_options.analytics_id=$(VERILATOR_ANALYTICS_ID)
+  SPHINXOPTS += -D html_theme_options.analytics_id=$(VERILATOR_ANALYTICS_ID)
 endif
 
 ######################################################################
@@ -68,15 +68,21 @@ pdf:
 
 ######################################################################
 
-html latex linkcheck spelling::
+html latex linkcheck::
 	$(MAKE) vl-extract
 	$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS)
 	$(PYTHON3) bin/vl_sphinx_fix _build
 
+spelling::
+	$(MAKE) vl-extract
+	$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS)
+	sort -o guide/spelling.txt guide/spelling.txt
+
 help:
 	@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS)
 
 clean mostlyclean distclean maintainer-clean::
+	rm -rf _build
 	rm -f $(SCRIPTS) *.tmp
 	rm -f *.aux *.cp *.cps *.dvi *.fn *.fns *.ky *.kys *.log
 	rm -f *.pg *.pgs *.toc *.tp *.tps *.vr *.vrs *.idx

docs/README.rst

@@ -0,0 +1,21 @@
+Verilator Documentation
+=======================
+
+This folder contains sources for Verilator documentation.
+
+For formatted documentation see:
+
+- `Verilator README <https://github.com/verilator/verilator>`_
+
+- `Verilator installation and package directory structure
+  <https://verilator.org/install>`_
+
+- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_,
+  or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
+
+- `Subscribe to Verilator announcements
+  <https://github.com/verilator/verilator-announce>`_
+
+- `Verilator forum <https://verilator.org/forum>`_
+
+- `Verilator issues <https://verilator.org/issues>`_

docs/bin/vl_sphinx_extract

@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0112,C0114,C0115,C0116,C0209,C0301,R0201,R0903
+# pylint: disable=C0112,C0114,C0115,C0116,C0209,C0301,R0903
 # -*- Python -*- See copyright, etc below
 ######################################################################
 
@@ -23,9 +23,7 @@ class VlSphinxExtract:
                     outname = match.group(1)
                     print("Writing %s" % outname)
                     fhw = open(outname, "w", encoding="utf8")  # pylint: disable=consider-using-with
-                    fhw.write(
+                    fhw.write(".. comment: generated by vl_sphinx_extract from " + filename + "\n")
-                        ".. comment: generated by vl_sphinx_extract from " +
-                        filename + "\n")
                     fhw.write(".. code-block::\n")
                 elif re.match(r'^[=a-zA-Z0-9_]', line):
                     fhw = None
@@ -39,18 +37,14 @@ parser = argparse.ArgumentParser(
     allow_abbrev=False,
     formatter_class=argparse.RawDescriptionHelpFormatter,
     description="""Read a file and extract documentation data.""",
-    epilog=
+    epilog=""" Copyright 2021-2025 by Wilson Snyder.  This package is free software;
-    """ Copyright 2021-2023 by Wilson Snyder.  This package is free software;
 you can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
 
 SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
-parser.add_argument('--debug',
+parser.add_argument('--debug', action='store_const', const=9, help='enable debug')
-                    action='store_const',
-                    const=9,
-                    help='enable debug')
 parser.add_argument('path', help='path to extract from')
 Args = parser.parse_args()
 

docs/bin/vl_sphinx_fix

@@ -18,8 +18,7 @@ class VlSphinxFix:
         if os.path.isdir(path):
             for basefile in os.listdir(path):
                 file = os.path.join(path, basefile)
-                if ((basefile != ".") and (basefile != "..")
+                if ((basefile != ".") and (basefile != "..") and basefile not in self.SkipBasenames
-                        and basefile not in self.SkipBasenames
                         and not os.path.islink(file)):
                     self.process(file)
         elif re.search(r'\.(html|tex)$', path):
@@ -54,18 +53,14 @@ parser = argparse.ArgumentParser(
     allow_abbrev=False,
     formatter_class=argparse.RawDescriptionHelpFormatter,
     description="""Post-process Sphinx HTML.""",
-    epilog=
+    epilog=""" Copyright 2021-2025 by Wilson Snyder.  This package is free software;
-    """ Copyright 2021-2023 by Wilson Snyder.  This package is free software;
 you can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
 
 SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
-parser.add_argument('--debug',
+parser.add_argument('--debug', action='store_const', const=9, help='enable debug')
-                    action='store_const',
-                    const=9,
-                    help='enable debug')
 parser.add_argument('path', help='path to edit')
 Args = parser.parse_args()
 

docs/gen/ex_ALWNEVER_faulty.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_event_control_star_never_bad
+.. code-block:: sv
+
+     always @* a = 100;

docs/gen/ex_ALWNEVER_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_event_control_star_never_bad
+.. code-block::
+
+   %Warning-ALWNEVER: example.v:1:3 'always @*' will never execute as expression list is empty (no variables read)

docs/gen/ex_BADVLTPRAGMA_faulty.rst

@@ -0,0 +1,5 @@
+.. comment: generated by t_lint_badvltpragma_bad
+.. code-block:: sv
+   :emphasize-lines: 1
+
+      // verilator lintt_off WIDTH  //<--- Warning (lint_off misspelled)

docs/gen/ex_BADVLTPRAGMA_msg.rst

@@ -0,0 +1,7 @@
+.. comment: generated by t_lint_badvltpragma_bad
+.. code-block::
+   :emphasize-lines: 1,2
+
+   %Error-BADVLTPRAGMA: example.v:1:4 Unknown verilator comment: '/*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/'
+       7 |    /*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/
+         |    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

docs/gen/ex_DIDNOTCONVERGE_msg.rst

@@ -1,5 +1,5 @@
 .. comment: generated by t_lint_didnotconverge_bad
 .. code-block::
 
-   -V{t#,#}         'stl' region trigger index 1 is active: @([hybrid] a)
+   -V{t#,#}         'stl' region trigger index 1 is active: @([hybrid] b)
    %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge.

docs/gen/ex_PARAMNODEFAULT_faulty.rst

@@ -0,0 +1,7 @@
+.. comment: generated by t_lint_paramnodefault_bad
+.. code-block:: sv
+   :linenos:
+   :emphasize-lines: 2
+
+   module sub;
+     parameter NODEF;  //<--- Warning

docs/gen/ex_PARAMNODEFAULT_msg.rst

@@ -0,0 +1,6 @@
+.. comment: generated by t_lint_paramnodefault_bad
+.. code-block::
+
+   %Error-PARAMNODEFAULT: example.v:1:13 Parameter without default requires ANSI-style parameter list (IEEE 1800-2023 6.20.1): 'NODEF'
+       8 |   parameter NODEF;
+         |             ^~~~~

docs/gen/ex_PINMISSING_faulty.rst

@@ -0,0 +1,11 @@
+.. comment: generated by t_lint_pinmissing_bad
+.. code-block:: sv
+   :linenos:
+   :emphasize-lines: 2
+
+   module t;
+      sub sub();  // <--- Warning
+   endmodule
+   module sub
+     (output port);
+   endmodule

docs/gen/ex_PINMISSING_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_lint_pinmissing_bad
+.. code-block::
+
+   %Warning-PINMISSING: example.v:1:8 Instance has missing pin: 'port'

docs/gen/ex_PROCASSINIT_faulty.rst

@@ -0,0 +1,12 @@
+.. comment: generated by t_lint_procassinit_bad
+.. code-block:: sv
+   :linenos:
+   :emphasize-lines: 1,5
+
+      logic flop_out = 1;  // <--- Warning
+
+      always @(posedge clk, negedge reset_l) begin
+         if (enable) begin
+            flop_out <= ~in;  // <--- Use of initialized
+         end
+      end

docs/gen/ex_PROCASSINIT_fixed.rst

@@ -0,0 +1,15 @@
+.. comment: generated by t_lint_procassinit_bad
+.. code-block:: sv
+   :linenos:
+   :emphasize-lines: 5
+
+      logic flop2_out;
+
+      always @(posedge clk, negedge reset_l) begin
+         if (!reset_l) begin
+            flop2_out <= '1;  // <--- Added reset init
+         end
+         else if (enable) begin
+            flop2_out <= ~in;
+         end
+      end

docs/gen/ex_PROCASSINIT_msg.rst

@@ -0,0 +1,12 @@
+.. comment: generated by t_lint_procassinit_bad
+.. code-block::
+
+   %Warning-PROCASSINIT: example.v:1:21 Procedural assignment to declaration with initial value: 'flop_out'
+                                                         : ... note: In instance 't'
+                                                         : ... Location of variable initialization
+      26 |    logic flop_out = 1;
+         |                     ^
+                         example.v:1:10 ... Location of variable process write
+                                                         : ... Perhaps should initialize instead using a reset in this process
+      30 |          flop_out <= ~in;
+         |          ^~~~~~~~

docs/gen/ex_WIDTHEXPAND_1_faulty.rst

@@ -3,6 +3,6 @@
    :linenos:
    :emphasize-lines: 3
 
-      int array[5];
+     logic [31:0] array[5];
-      bit [1:0] rd_addr;
+     bit [1:0] rd_addr;
-      wire int rd_value = array[rd_addr];  //<--- Warning
+     wire [31:0] rd_value = array[rd_addr];  //<--- Warning

docs/gen/ex_WIDTHEXPAND_1_fixed.rst

@@ -2,4 +2,4 @@
 .. code-block:: sv
    :emphasize-lines: 1
 
-      wire int rd_value = array[{1'b0, rd_addr}];  //<--- Fixed
+     wire [31:0] rd_value = array[{1'b0, rd_addr}];  //<--- Fixed

docs/gen/ex_WIDTHEXPAND_1_msg.rst

@@ -1,4 +1,4 @@
 .. comment: generated by t_lint_widthexpand_docs_bad
 .. code-block::
 
-   %Warning-WIDTHEXPAND: example.v:3:29 Bit extraction of array[4:0] requires 3 bit index, not 2 bits.
+   %Warning-WIDTHEXPAND: example.v:3:31 Bit extraction of array[4:0] requires 3 bit index, not 2 bits.

docs/guide/changes.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ****************

docs/guide/conf.py

@@ -1,7 +1,7 @@
 # pylint: disable=C0103,C0114,C0116,C0301,E0402,W0622
 #
 # Configuration file for Verilator's Sphinx documentation builder.
-# Copyright 2003-2023 by Wilson Snyder.
+# Copyright 2003-2025 by Wilson Snyder.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 # This file only contains overridden options. For a full list:
@@ -23,8 +23,7 @@ def get_vlt_version():
     filename = "../../Makefile"
     with open(filename, "r", encoding="utf8") as fh:
         for line in fh:
-            match = re.search(r"PACKAGE_VERSION *= *([a-z0-9.]+) +([-0-9]+)",
+            match = re.search(r"PACKAGE_VERSION *= *([a-z0-9.]+) +([-0-9]+)", line)
-                              line)
             if match:
                 return match.group(1), match.group(2)
             match = re.search(r"PACKAGE_VERSION *= *([a-z0-9.]+) +devel", line)
@@ -45,7 +44,7 @@ def setup(app):
 # -- Project information
 
 project = 'Verilator'
-copyright = '2022 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0'
+copyright = '2024 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0'
 author = 'Wilson Snyder'
 
 # The master toctree document.
@@ -75,8 +74,7 @@ extensions = []
 # directories to ignore when looking for source files.
 # This pattern also affects html_static_path and html_extra_path.
 exclude_patterns = [
-    '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst', 'gen/ex_*',
+    '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst', 'gen/ex_*', 'CONTRIBUTING.rst'
-    'CONTRIBUTING.rst'
 ]
 
 # Warn about refs
@@ -171,15 +169,7 @@ latex_elements = {
 # Grouping the document tree into LaTeX files. List of tuples
 # (source start file, target name, title,
 #  author, documentclass [howto, manual, or own class]).
-# latex_documents = [
+# latex_documents = [ ... ]
-#    (
-#        master_doc,
-#        "Verilog-to-Routing.tex",
-#        "Verilog-to-Routing Documentation",
-#        "VTR Developers",
-#        "manual",
-#    ),
-# ]
 
 # For "manual" documents, if this is true, then toplevel headings are parts,
 # not chapters.
@@ -230,4 +220,4 @@ spelling_ignore_contributor_names = True
 
 breathe_projects = {"verilated": "_build/doxygen/verilated/xml/"}
 breathe_default_project = "verilated"
-breathe_default_members = ('members')
+breathe_default_members = 'members'

docs/guide/connecting.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Connecting:
@@ -73,8 +73,8 @@ often inlined into the root scope) will need to be updated as follows:
     :code:`$` character, i.e.: :code:`rootp` points to the Verilated
     SystemVerilog :code:`$root` scope.
 
-  * Replace :code:`modelp->internal->member->lookup` references with
+  * Replace :code:`modelp->internal->member` references with
-    :code:`modelp->rootp->internal->member->lookup` references, which
+    :code:`modelp->rootp->internal->member` references, which
     contain one additional indirection via the :code:`rootp` pointer.
 
 
@@ -128,6 +128,43 @@ in the distribution.  These headers use Doxygen comments, `///` and `//<`,
 to indicate and document those functions that are part of the Verilated
 public API.
 
+Process-Level Clone APIs
+--------------------------
+
+Modern operating systems support process-level clone (a.k.a copying, forking)
+with system call interfaces in C/C++, e.g., :code:`fork()` in Linux.
+
+However, after cloning a parent process, some resources cannot be inherited
+in the child process. For example, in POSIX systems, when you fork a process,
+the child process inherits all the memory of the parent process. However,
+only the thread that called fork is replicated in the child process. Other
+threads are not.
+
+Therefore, to support the process-level clone mechanisms, Verilator supports
+:code:`prepareClone()` and :code:`atClone()` APIs to allow the user to manually
+re-construct the model in the child process. The two APIs handle all necessary
+resources required for releasing and re-initializing before and after cloning.
+
+The two APIs are supported in the verilated models. Here is an example of usage
+with Linux :code:`fork()` and :code:`pthread_atfork` APIs:
+
+.. code-block:: C++
+
+    // static function pointers to fit pthread_atfork
+    static auto prepareClone = [](){ topp->prepareClone(); };
+    static auto atClone = [](){ topp->atClone(); };
+
+    // in main function, register the handlers:
+    pthread_atfork(prepareClone, atClone, atClone);
+
+For better flexibility, you can also manually call the handlers before and
+after :code:`fork()`.
+
+With the process-level clone APIs, users can create process-level snapshots
+for the verilated models. While the Verilator save/restore option provides
+persistent and circuit-dependent snapshots, the process-level clone APIs
+enable in-memory, circuit-transparent, and highly efficient snapshots.
+
 
 Direct Programming Interface (DPI)
 ==================================
@@ -370,6 +407,16 @@ only a couple of instructions.
 For signal callbacks to work the main loop of the program must call
 :code:`VerilatedVpi::callValueCbs()`.
 
+Verilator also tracks when the model state has been modified via the VPI with
+an :code:`evalNeeded` flag.  This flag can be checked with :code:`VerilatedVpi::evalNeeded()`
+and it can be cleared with :code:`VerilatedVpi::clearEvalNeeded()`.  Used together
+it is possible to skip :code:`eval()` calls if no model state has been changed
+since the last :code:`eval()`.
+
+Any data written via :code:`vpi_put_value` with :code:`vpiInertialDelay` will
+be deferred for later.  These delayed values can be flushed to the model with
+:code:`VerilatedVpi::doInertialPuts()`.
+
 
 .. _VPI Example:
 
@@ -463,7 +510,7 @@ the user should call:
      any delayed events pending,
    * :code:`designp->nextTimeSlot()`, which returns the simulation time of the
      next delayed event. This method can only be called if
-     :code:`designp->nextTimeSlot()` returned :code:`true`.
+     :code:`designp->eventsPending()` returned :code:`true`.
 
 Call :code:`eventsPending()` to check if you should continue with the
 simulation, and then :code:`nextTimeSlot()` to move simulation time forward.

docs/guide/contributing.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *******************************
@@ -23,24 +23,24 @@ Next, try the :vlopt:`--debug` option.  This will enable additional
 internal assertions, and may help identify the problem.
 
 Finally, reduce your code to the smallest possible routine that exhibits
-the bug.  Even better, create a test in the :file:`test_regress/t`
+the bug (see: :ref:`Minimizing bug-inducing code`).  Even better, create
-directory, as follows:
+a test in the :file:`test_regress/t` directory, as follows:
 
 .. code-block:: bash
 
        cd test_regress
-       cp -p t/t_EXAMPLE.pl t/t_BUG.pl
+       cp -p t/t_EXAMPLE.py t/t_BUG.py
        cp -p t/t_EXAMPLE.v t/t_BUG.v
 
 There are many hints on how to write a good test in the
-:file:`test_regress/driver.pl` documentation which can be seen by running:
+:file:`test_regress/driver.py` documentation which can be seen by running:
 
 .. code-block:: bash
 
        cd $VERILATOR_ROOT  # Need the original distribution kit
-       test_regress/driver.pl --help
+       test_regress/driver.py --help
 
-Edit :file:`t/t_BUG.pl` to suit your example; you can do anything you want
+Edit :file:`t/t_BUG.py` to suit your example; you can do anything you want
 in the Verilog code there; just make sure it retains the single clk input
 and no outputs.  Now, the following should fail:
 
@@ -48,20 +48,42 @@ and no outputs.  Now, the following should fail:
 
        cd $VERILATOR_ROOT  # Need the original distribution kit
        cd test_regress
-       t/t_BUG.pl  # Run on Verilator
+       t/t_BUG.py  # Run on Verilator
-       t/t_BUG.pl --debug # Run on Verilator, passing --debug to Verilator
+       t/t_BUG.py --debug # Run on Verilator, passing --debug to Verilator
-       t/t_BUG.pl --vcs  # Run on VCS simulator
+       t/t_BUG.py --vcs  # Run on VCS simulator
-       t/t_BUG.pl --nc|--iv|--ghdl  # Likewise on other simulators
+       t/t_BUG.py --nc|--iv|--ghdl  # Likewise on other simulators
 
 The test driver accepts a number of options, many of which mirror the main
 Verilator options. For example the previous test could have been run with
 debugging enabled.  The full set of test options can be seen by running
-:command:`driver.pl --help` as shown above.
+:command:`driver.py --help` as shown above.
 
 Finally, report the bug at `Verilator Issues
 <https://verilator.org/issues>`_.  The bug will become publicly visible; if
 this is unacceptable, mail the bug report to ``[email protected]``.
 
+.. _Minimizing bug-inducing code:
+
+Minimizing bug-inducing code
+============================
+
+In some cases, the part of the code that causes the bug is clearly visible
+and the design can be easily manually reduced. In other cases, the bug is
+caused by a complex interaction of many parts of the design, and it is not
+clear which parts are necessary to reproduce the bug. In these cases, an
+Open Source tool called `sv-bugpoint
+<https://github.com/antmicro/sv-bugpoint>`_ can be used to automatically
+reduce a SystemVerilog design to the smallest possible reproducer.
+It can be used to automatically reduce a design with hundreds of thousands of
+lines to a minimal test case while preserving the bug-inducing behavior.
+
+With :vlopt:`--debug`, Verilator will write a *{prefix}*\ __inputs\ .vpp
+file which has all of the individual input files combined and
+pre-processed, this is often useful as the input design into `sv-bugpoint`.
+
+Please refer to `sv-bugpoint README
+<https://github.com/antmicro/sv-bugpoint/blob/main/README.md>`_ for more
+information on how to use `sv-bugpoint`.
 
 .. Contributing
 .. ============

docs/guide/contributors.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ************************
@@ -23,111 +23,151 @@ Contributors
 Many people have provided ideas and other assistance with Verilator.
 
 Verilator is receiving significant development support from the `CHIPS
-Alliance <https://chipsalliance.org>`_, `Antmicro Ltd
+Alliance <https://chipsalliance.org>`_, and `Antmicro Ltd
-<https://antmicro.com>`_ and `Shunyao CAD <https://shunyaocad.com>`_.
+<https://antmicro.com>`_.
 
 Previous major corporate sponsors of Verilator, by providing significant
-contributions of time or funds include: Atmel Corporation, Cavium
+contributions of time or funds include: Antmicro Ltd., Atmel Corporation,
-Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd.,
+Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Hicamp
-Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune
+Systems, Intel Corporation, Marvell Inc., Mindspeed Technologies Inc.,
-Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc.,
+MicroTune Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus
-SiCortex Inc, and Shunyao CAD.
+Networks Inc., SiCortex Inc, Shunyao CAD, and Western Digital Inc.
 
-The contributors of major functionality are: Krzysztof
+The contributors of major functionality are: Jeremy Bennett, Krzysztof
-Bieganski, Byron Bradley, Jeremy Bennett, Lane Brooks, John Coiner, Duane
+Bieganski, Byron Bradley, Lane Brooks, John Coiner, Duane Galbi, Arkadiusz
-Galbi, Geza Lore, Todd Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu,
+Kozdra, Geza Lore, Todd Strader, Yutetsu Takatsukasa, Stefan Wallentowitz,
-and Wilson Snyder.  Major testers included Jeff Dutton, Jonathon Donaldson,
+Paul Wasson, Jie Xu, and Wilson Snyder.
-Ralf Karge, David Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov,
-Sebastien Van Cauwenberghe, Gene Weber, and Clifford Wolf.
 
 Some of the people who have provided ideas, and feedback for Verilator
 include:
 
-David Addison, Tariq B. Ahmad, Nikana Anastasiadis, Vasu Arasanipalai, Jens
+David Addison, Tariq B. Ahmad, Nikana Anastasiadis, John David Anglin,
-Arm, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew Barr, Geoff
+Frederic Antonin, Hans Van Antwerpen, Vasu Arasanipalai, Jens Arm, Rohan
-Barrett, Kaleb Barrett, Julius Baxter, Jeremy Bennett, Michael Berman, Jean
+Arshid, Valentin Atepalikhin, Philip Axer, Gökçe Aydos, Chris Bachhuber,
-Berniolles, Victor Besyakov, Moinak Bhattacharyya, Krzysztof Bieganski,
+Filip Badáň, Adam Bagley, Sharad Bagri, James Bailey, Robert Balas, Marco
-David Binderman, Piotr Binkowski, Johan Bjork, David Black, Tymoteusz
+Balboni, Matthew Ballance, Ricardo Barbedo, Andrew Bardsley, Ilya Barkov,
-Blazejczyk, Daniel Bone, Gregg Bouchard, Christopher Boumenot, Nick Bowler,
+Matthew Barr, Geoff Barrett, Kaleb Barrett, Daniel Bates, Julius Baxter,
-Byron Bradley, Bryan Brady, Maarten De Braekeleer, Charlie Brej, J Briquet,
+Michael Berman, Jean Berniolles, Victor Besyakov, Narayan Bhagavatula,
-Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, Tony Bybell, Iru
+Moinak Bhattacharyya, Kritik Bhimani, David Biancolin, Krzysztof Bieganski,
-Cai, Ted Campbell, Chris Candler, Lauren Carlson, Donal Casey, Alex
+Michael Bikovitsky, David Binderman, Piotr Binkowski, Johan Björk, David
-Chadwick, Marcel Chang, Aliaksei Chapyzhenka, Guokai Chen, Terry Chen,
+Black, Tymoteusz Blazejczyk, Scott Bleiweiss, David van der Bokke, Daniel
-Yi-Chung Chen, Enzo Chi, Robert A. Clark, Ryan Clarke, Allan Cochrane, John
+Bone, Guy Bonneau, Krzysztof Boroński, Gregg Bouchard, Christopher
-Coiner, Keith Colbert, Gianfranco Costamagna, Sean Cross, George Cuan, Joe
+Boumenot, Paul Bowen-Huggett, Nick Bowler, Bryan Brady, Maarten De
-DErrico, Lukasz Dalek, Gunter Dannoritzer, Ashutosh Das, Bernard Deadman,
+Braekeleer, Liam Braun, Charlie Brej, J Briquet, John Brownlee, KC
-John Demme, Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben
+Buckenmaier, Gijs Burghoorn, Jeff Bush, Lawrence Butcher, Tony Bybell, Iru
-Diez, Danny Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Larry
+Cai, Ted Campbell, Anthony Campos, Chris Candler, Lauren Carlson, Gregory
-Doolittle, Sebastian Dressler, Jonathan Drolet, Alex Duller, Jeff Dutton,
+Carver, Donal Casey, Sebastien Van Cauwenberghe, Alex Chadwick, Greg
+Chadwick, Marcel Chang, Aliaksei Chapyzhenka, Chih-Mao Chen, Guokai Chen,
+Kefa Chen, Terry Chen, Yangyu Chen, Yi-Chung Chen, Yurii Cherkasov,
+Hennadii Chernyshchyk, Enzo Chi, Bartłomiej Chmiel, Robert A. Clark, Ryan
+Clarke, Allan Cochrane, Keith Colbert, Quentin Corradi, Nassim Corteggiani,
+Gianfranco Costamagna, February Cozzocrea, Sean Cross, George Cuan, Michal
+Czyz, Joe DErrico, Jim Dai, Lukasz Dalek, Laurens van Dam, Gunter
+Dannoritzer, Ashutosh Das, Julian Daube, Greg Davill, Bernard Deadman,
+Peter Debacker, Josse Van Delm, John Demme, Mike Denio, John Deroo, Philip
+Derrick, Aadi Desai, John Dickol, Ruben Diez, Danny Ding, Jacko Dirks, Ivan
+Djordjevic, Brad Dobbie, Paul Donahue, Jonathon Donaldson, Anthony Donlon,
+Caleb Donovick, Larry Doolittle, Leendert van Doorn, Sebastian Dressler,
+Jonathan Drolet, Justin Yao Du, Maciej Dudek, Alex Duller, Jeff Dutton,
 Tomas Dzetkulic, Usuario Eda, Charles Eddleston, Chandan Egbert, Joe Eiler,
-Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Robert Farrell, Eugen
+Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Robert Farrell, Julien
-Fekete, Fabrizio Ferrandi, Udi Finkelstein, Brian Flachs, Bill Flynn,
+Faucher, Olivier Faure, Eugene Feinberg, Eugen Fekete, Fabrizio Ferrandi,
-Andrea Foletto, Bob Fredieu, Duane Galbi, Mostafa Gamal, Benjamin Gartner,
+Udi Finkelstein, Brian Flachs, Bill Flynn, Andrea Foletto, Alex Forencich,
-Christian Gelinek, Richard E George, Peter Gerst, Glen Gibb, Michael
+Aurelien Francillon, Bob Fredieu, Manuel Freiberger, Mostafa Gamal, Vito
-Gielda, Barbara Gigerl, Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam
+Gamberini, Mostafa Garnal, Benjamin Gartner, Christian Gelinek, Richard E
-Gladstone, Mariusz Glebocki, Andrew Goessling, Amir Gonnen, Chitlesh
+George, Peter Gerst, Glen Gibb, Michael Gielda, Barbara Gigerl, Nimrod
-Goorah, Tomasz Gorochowik, Kai Gossner, Sergi Granell, Al Grant, Nathan
+Gileadi, Shankar Giri, Dan Gisselquist, Szymon Gizler, Petr Gladkikh, Sam
-Graybeal, Alexander Grobman, Graham Rushton, Xuan Guo, Driss Hafdi, Neil
+Gladstone, Mariusz Glebocki, Embedded Go, Andrew Goessling, Amir Gonnen,
-Hamilton, James Hanlon, Oyvind Harboe, Jannis Harder, Junji Hashimoto,
+Chitlesh Goorah, Tomasz Gorochowik, Kai Gossner, Tarik Graba, Sergi
-Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert Henry, Stephen
+Granell, Al Grant, Nathan Graybeal, Alexander Grobman, Qian Gu, Xuan Guo,
-Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew Holme, Hiroki
+Prabhat Gupta, Deniz Güzel, Driss Hafdi, Abdul Hameed, Neil Hamilton, James
-Honda, Alex Hornung, Pierre-Henri Horrein, David Horton, Peter Horvath, Jae
+Hanlon, Tang Haojin, Øyvind Harboe, Jannis Harder, David Harris, Junji
-Hossell, Kuoping Hsu, Teng Huang, Steven Hugg, Alan Hunter, James
+Hashimoto, Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert Henry,
-Hutchinson, Ehab Ibrahim, Edgar E. Iglesias, Jamie Iles, Vighnesh Iyer, Ben
+Stephen Henry, Sebastian Hesselbarth, David Hewson, Jamey Hicks, Joel
-Jackson, Shareef Jalloq, Marlon James, Krzysztof Jankowski, HyungKi Jeong,
+Holdsworth, Andrew Holme, Peter Holmes, Hiroki Honda, Alex Hornung,
-Iztok Jeras, Alexandre Joannou, James Johnson, Christophe Joly, Franck
+Pierre-Henri Horrein, David Horton, Peter Horvath, Jae Hossell, Kuoping
-Jullien, James Jung, Mike Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand
+Hsu, Shou-Li Hsu, Teng Huang, Steven Hugg, Alan Hunter, James Hutchinson,
-Kamendje, Vasu Kandadi, Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg,
+Tim Hutt, Ehab Ibrahim, Edgar E. Iglesias, Shahid Ikram, Jamie Iles, Fuad
-Rafal Kapuscik, Ralf Karge, Per Karlsson, Dan Katz, Sol Katzman, Ian
+Ismail, Vighnesh Iyer, Ben Jackson, Daniel Jacques, Shareef Jalloq, Marlon
-Kennedy, Michael Killough, Sun Kim, Jonathan Kimmitt, Olof Kindgren, Kevin
+James, Krzysztof Jankowski, Eyck Jentzsch, HyungKi Jeong, Iztok Jeras,
-Kiningham, Dan Kirkham, Aleksander Kiryk, Sobhan Klnv, Gernot Koch, Jack
+Pawel Jewstafjew, Alexandre Joannou, James Johnson, Christophe Joly, Justin
-Koenig, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce, Will
+Jones, William D. Jones, Abe Jordan, Larry Darryl Lee Jr., Franck Jullien,
-Korteland, Wojciech Koszek, Varun Koyyalagunta, Arkadiusz Kozdra, Markus
+James Jung, Mike Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje,
-Krause, David Kravitz, Roland Kruse, Andreas Kuster, Sergey Kvachonok,
+Vasu Kandadi, Yoshitomo Kaneda, Kanad Kanhere, Patricio Kaplan, Pieter
-Charles Eric LaForest, Ed Lander, Steve Lang, Stephane Laurent, Walter
+Kapsenberg, Rafal Kapuscik, Ralf Karge, Per Karlsson, Dan Katz, Sol
-Lavino, Christian Leber, Larry Lee, Yoda Lee, Michaël Lefebvre, Igor Lesik,
+Katzman, Ian Kennedy, Ami Keren, Fabian Keßler, Michael Killough, Sun Kim,
-John Li, Eivind Liland, Yu Sheng Lin, Charlie Lind, Andrew Ling, Jiuyang
+Jonathan Kimmitt, Olof Kindgren, Kevin Kiningham, Cameron Kirk, Dan
-Liu, Paul Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan
+Kirkham, Aleksander Kiryk, Sobhan Klnv, Gernot Koch, Jack Koenig, Soon Koh,
-Ludwig, Dan Lussier, Fred Ma, Duraid Madina, Affe Mao, Julien Margetts,
+Nathan Kohagen, Steve Kolecki, Brett Koonce, Will Korteland, Andrei
-Mark Marshall, Alfonso Martinez, Unai Martinez-Corral, Adrien Le Masle,
+Kostovski, Wojciech Koszek, Varun Koyyalagunta, Arkadiusz Kozdra, Markus
-Yves Mathieu, Patrick Maupin, Conor McCullough, Jason McMullan, Elliot
+Krause, David Kravitz, Adam Krolnik, Roland Kruse, Mahesh Kumashikar,
-Mednick, David Metz, Wim Michiels, Miodrag Milanovic, Kevin Millis, Wai Sum
+Andreas Kuster, Sergey Kvachonok, Charles Eric LaForest, Kevin Laeufer, Ed
-Mong, Peter Monsson, Sean Moore, Dennis Muhlestein, John Murphy, Matt
+Lander, Steve Lang, Pierre Laroche, Stephane Laurent, Walter Lavino,
-Myers, Nathan Myers, Richard Myers, Dimitris Nalbantis, Peter Nelson, Bob
+Christian Leber, David Ledger, Alex Lee, Larry Lee, Yoda Lee, Michaël
-Newgard, Rachit Nigam, Paul Nitza, Yossi Nivin, Pete Nixon, Lisa Noack,
+Lefebvre, Dag Lem, Igor Lesik, John Li, Kay Li, Zixi Li, Davide Libenzi,
-Mark Nodine, Kuba Ober, Andreas Olofsson, Baltazar Ortiz, Aleksander Osman,
+Nandor Licker, Eivind Liland, Ícaro Lima, Kevin Lin, Yu-Sheng Lin, Charlie
-Don Owen, James Pallister, Vassilis Papaefstathiou, Brad Parker, Morten
+Lind, Andrew Ling, Jiuyang Liu, Joey Liu, Paul Liu, Derek Lockhart, Jake
-Borup Petersen, Dan Petrisko, Maciej Piechotka, David Pierce, Cody
+Longo, Geza Lore, Arthur Low, Jose Loyola, Stefan Ludwig, Dan Lussier,
-Piersall, Michael Platzer, Dominic Plunkett, David Poole, Mike Popoloski,
+Konstantin Lübeck, Fred Ma, Liwei Ma, Duraid Madina, Oleh Maksymenko, Affe
-Roman Popov, Rich Porter, Stefan Post, Niranjan Prabhu, Damien Pretet, Usha
+Mao, Julien Margetts, Chick Markley, Alexis Marquet, Mark Marshall, Alfonso
-Priyadharshini, Mark Jackson Pulver, Prateek Puri, Marshal Qiao, Nandu Raj,
+Martinez, Unai Martinez-Corral, Adrien Le Masle, Yves Mathieu, Vladimir
-Kamil Rakoczy, Danilo Ramos, Drew Ranck, Chris Randall, Anton Rapp, Josh
+Matveyenko, Patrick Maupin, Stan Mayer, Jordan McConnon, Conor McCullough,
-Redford, Odd Magne Reitan, Frederic Requin, Dustin Richmond, Samuel Riedel,
+Jason McMullan, Elliot Mednick, Yuan Mei, Andy Meier, Luiza de Melo,
-Alberto Del Rio, Eric Rippey, Oleg Rodionov, Ludwig Rogiers, Paul Rolfe,
+Rodrigo A. Melo, Benjamin Menküc, Jake Merdich, David Metz, Wim Michiels,
-Arjen Roodselaar, Tobias Rosenkranz, Ryszard Rozak, Huang Rui, Graham
+Miodrag Milanović, Darryl Miles, Kevin Millis, Andrew Miloradovsky, David
-Rushton, Jan Egil Ruud, Denis Rystsov, John Sanguinetti, Martin Schmidt,
+Moberg, Wai Sum Mong, Peter Monsson, Anthony Moore, Sean Moore, Stuart
-Julie Schwartz, Galen Seitz, Joseph Shaker, Salman Sheikh, Hao Shi, Mike
+Morris, Dennis Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard
-Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Fan Shupei, Anderson Ignacio
+Myers, Alex Mykyta, Eric Müller, Dimitris Nalbantis, Peter Nelson, Felix
-da Silva, Rodney Sinclair, Ameya Vikram Singh, Steven Slatter, Mladen
+Neumärker, Bob Newgard, Cong Van Nguyen, Rachit Nigam, Toru Niina, Paul
-Slijepcevic, Brian Small, Garrett Smith, Tim Snyder, Wilson Snyder, Maciej
+Nitza, Yossi Nivin, Pete Nixon, Lisa Noack, Mark Nodine, Michael Nolan,
-Sobkowski, Stan Sokorac, Alex Solomatnikov, Flavien Solt, Wei Song, Trefor
+Andrew Nolte, Joseph Nwabueze, Kevin Nygaard, Kuba Ober, Krzysztof
-Southwell, Martin Stadler, Art Stamness, David Stanford, John Stevenson,
+Obłonczek, Andreas Olofsson, Baltazar Ortiz, Aleksander Osman, Don Owen,
-Pete Stevenson, Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel,
+Tim Paine, Deepa Palaniappan, James Pallister, Vassilis Papaefstathiou,
-Sven Stucki, Howard Su, Emerson Suguimoto, Gene Sullivan, Qingyao Sun,
+Sanggyu Park, Brad Parker, Risto Pejašinović, Seth Pellegrino, Morten Borup
-Renga Sundararajan, Gustav Svensk, Rupert Swarbrick, Yutetsu Takatsukasa,
+Petersen, Dan Petrisko, Wesley Piard, Maciej Piechotka, David Pierce, Cody
-Thierry Tambe, Drew Taussig, Jose Tejada, Peter Tengstrand, Wesley
+Piersall, T. Platz, Michael Platzer, Dominic Plunkett, Nolan Poe, David
-Terpstra, Rui Terra, Stefan Thiede, Gary Thomas, Ian Thompson, Kevin
+Poole, Michael Popoloski, Roman Popov, Aylon Chaim Porat, Oron Port, Rich
-Thompson, Mike Thyer, Hans Tichelaar, Viktor Tomov, Steve Tong, Topa
+Porter, Rick Porter, Stefan Post, Niranjan Prabhu, Damien Pretet, Harald
-Topino, Alex Torregrosa, Michael Tresidder, David Turner, Neil Turton, Mike
+Pretl, Bill Pringlemeir, Usha Priyadharshini, Mark Jackson Pulver, Prateek
-Urbach, Hans Van Antwerpen, Sebastien Van Cauwenberghe, Laurens van Dam,
+Puri, Han Qi, Jiacheng Qian, Marshal Qiao, Raynard Qiao, Yujia Qiao, Jasen
-Leendert van Doorn, Cong Van Nguyen, Jan Van Winkel, Srini Vemuri, Yuri
+Qin, Frank Qiu, Nandu Raj, Kamil Rakoczy, Danilo Ramos, Drew Ranck, Chris
-Victorovich, Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Stefan
+Randall, Anton Rapp, Josh Redford, Odd Magne Reitan, Frédéric Requin,
-Wallentowitz, Shawn Wang, Zhanglei Wang, Paul Wasson, Greg Waters, Thomas
+Dustin Richmond, Samuel Riedel, Alberto Del Rio, Eric Rippey, Narcis Rodas,
-Watts, Eugene Weber, David Welch, Thomas J Whatson, Martin Whitaker, Marco
+Oleg Rodionov, Ludwig Rogiers, Paul Rolfe, Michail Rontionov, Arjen
-Widmer, Leon Wildman, Daniel Wilkerson, Gerald Williams, Trevor Williams,
+Roodselaar, Arthur Rosa, Tobias Rosenkranz, Yernagula Roshit, Ryszard
-Jeff Winston, Joshua Wise, Clifford Wolf, Tobias Wolfel, Johan Wouters,
+Rozak, Huang Rui, Graham Rushton, Jan Egil Ruud, Denis Rystsov, Pawel
-Paul Wright, Junyi Xi, Ding Xiaoliang, Jie Xu, Mandy Xu, Yinan Xu, Luke
+Sagan, Robert Sammelson, Adrian Sampson, John Sanguinetti, Josep Sans, Luca
-Yang, Amir Yazdanbakhsh, Keyi Zhang, and Xi Zhang.
+Sasselli, Martin Scharrer, Martin Schmidt, Jonathan Schröter, Julie
+Schwartz, Galen Seitz, Sam Shahrestani, Joseph Shaker, Mark Shaw, Salman
+Sheikh, Zhou Shen, Hao Shi, James Shi, Michael Shinkarovsky, Rafael
+Shirakawa, Jeffrey Short, S Shuba, Fan Shupei, Ethan Sifferman, Anderson
+Ignacio da Silva, Rodney Sinclair, Ameya Vikram Singh, Sanjay Singh, Frans
+Skarman, Nate Slager, Steven Slatter, Mladen Slijepcevic, Brian Small,
+Garrett Smith, Gus Smith, Tim Snyder, Maciej Sobkowski, Stan Sokorac, Alex
+Solomatnikov, Flavien Solt, Wei Song, Trefor Southwell, Martin Stadler, Art
+Stamness, David Stanford, Krzysztof Starecki, Baruch Sterin, John
+Stevenson, Pete Stevenson, Patrick Stewart, Rob Stoddard, Tood Strader,
+John Stroebel, Ray Strouble, Sven Stucki, Howard Su, Udaya Raj Subedi,
+Emerson Suguimoto, Gene Sullivan, Qingyao Sun, Renga Sundararajan, Kuba
+Sunderland-Ober, Gustav Svensk, Rupert Swarbrick, Jevin Sweval, Paul
+Swirhun, Shinya T-Y, Thierry Tambe, Jesse Taube, Drew Taussig, Christopher
+Taylor, Greg Taylor, Jose Tejada, Sören Tempel, Peter Tengstrand, Wesley
+Terpstra, Rui Terra, Stefan Thiede, Justin Thiel, Gary Thomas, Ian
+Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar, Tudor Timi, Viktor
+Tomov, Steve Tong, Topa Topino, Àlex Torregrosa, Topa Tota, Michael
+Tresidder, Lenny Truong, David Turner, Neil Turton, Hideto Ueno, Mike
+Urbach, Joel Vandergriendt, Srini Vemuri, Srinivasan Venkataramanan, Yuri
+Victorovich, Ivan Vnučec, Bogdan Vukobratovic, Holger Waechtler, Philipp
+Wagner, Stefan Wallentowitz, Johannes Walter, CY Wang, Chuxuan Wang, Shawn
+Wang, Yilou Wang, Zhanglei Wang, Greg Waters, Thomas Watts, Eugene Weber,
+John Wehle, Tianrui Wei, David Welch, Thomas J Whatson, Martin Whitaker,
+Marco Widmer, Leon Wildman, Daniel S. Wilkerson, Daniel Wilkerson, Gerald
+Williams, Trevor Williams, Don Williamson, Jan Van Winkel, Jeff Winston,
+Joshua Wise, Clifford Wolf, Johan Wouters, Paul Wright, Tobias Wölfel,
+Junyi Xi, Ding Xiaoliang, Liu Xiaoyi, Jinyan Xu, Mandy Xu, Pengcheng Xu,
+Shanshan Xu, Yan Xu, Yinan Xu, SU YANG, Felix Yan, Jiaxun Yang, Luke Yang,
+Amir Yazdanbakhsh, Chentai (Seven) Yuan, Florian Zaruba, Mat Zeno, Keyi
+Zhang, Xi Zhang, Huanghuang Zhou, Yike Zhou, Jiamin Zhu, Ryan Ziegler.
 
 Thanks to them, and all those we've missed mentioning above, and to those
 whom have wished to remain anonymous.

docs/guide/copyright.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *********
@@ -8,7 +8,7 @@ Copyright
 The latest version of Verilator is available from `https://verilator.org
 <https://verilator.org>`_.
 
-Copyright 2003-2023 by Wilson Snyder. This program is free software; you
+Copyright 2003-2025 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.

docs/guide/deprecations.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 Deprecations
@@ -6,34 +6,17 @@ Deprecations
 
 The following deprecated items are scheduled for future removal:
 
-C++11 compiler support
+C++14 compiler support
   Verilator currently requires a C++20 or newer compiler for timing, and a
-  C++11 or newer compiler for no-timing.
+  C++14 or newer compiler for both compiling Verilator and compiling
-
+  Verilated models with --no-timing.
-  Verilator will require C++14 or newer compilers for both compiling
-  Verilator and compiling Verilated models with --no-timing no sooner than
-  January 2023.
 
   Verilator will require C++20 or newer compilers for both compiling
-  Verilator and compiling all Verilated models no sooner than January 2025.
+  Verilator and compiling all Verilated models no sooner than May 2025.
+  (Likely to be removed shortly after GitHub removes Ubuntu 20.04
+  continuous-integration action runners, which are used to test the older
+  C++ standard).
 
-32-bit compiler support
+XML output
-  Verilator currently regresses both 64-bit and 32-bit pointer modes (GCC's
+  Verilator currently supports XML parser output (enabled with `--xml-only`).
-  `-m64` and `-m32`).  Support for 32-bit `-m32` mode will be deprecated no
+  Support for `--xml-*` options will be deprecated no sooner than January 2026.
-  sooner than January 2024.
-
-Option `-O<letter>`
-  The debug `-O<letter>` options have been replaced with
-  `-fno-<optimization>` debug options to match GCC. The old options are
-  planned for removal no sooner than June 2023.
-
-Option `--prof-threads`
-  The `--prof-threads` option has been superseded by the `--prof-exec` and
-  `--prof-pgo` options and is planned for removal no sooner than April 2023.
-
-Verilated model options `+verilator+prof+threads+*`
-  The `+verilator+prof+threads+start`, `+verilator+prof+threads+window` and
-  `+verilator+prof+threads+file` options have been superseded by the
-  `+verilator+prof+exec+start`, `+verilator+prof+exec+window` and
-  `+verilator+prof+exec+file` options respectively and are planned for removal
-  no sooner than April 2023.

docs/guide/environment.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 Environment
@@ -29,7 +29,7 @@ associated programs.
 .. option:: OBJCACHE
 
    Optionally specifies a caching or distribution program to place in front
-   of all runs of the C++ compiler.  For example, "ccache".  If using
+   of all runs of the C++ compiler.  For example, "ccache" or "sccache".  If using
    :command:`distcc` or :command:`icecc`/:command:`icecream`, they would
    generally be run under :command:`ccache`; see the documentation for
    those programs.  If OBJCACHE is not set, and at configure time ccache
@@ -117,3 +117,57 @@ associated programs.
    ``VERILATOR_ROOT`` to point to the new version.
 
    See :ref:`Installation` for more details.
+
+.. option:: VERILATOR_SOLVER
+
+   If set, the command to run as a constrained randomization backend, such
+   as :command:`cvc4 --lang=smt2 --incremental`.  If not specified, it will use
+   the one supplied or found during configure, or :command:`z3 --in` if empty.
+
+.. option:: VERILATOR_VALGRIND
+
+   If set, the command to run when using the :vlopt:`--valgrind` option, such as
+   "valgrind --tool=callgrind".  If not specified, it will use "valgrind".
+
+
+Make Variables
+==============
+
+This section describes the make variables used by Verilator. These may be
+set by passing them to make e.g. ``make CXX=my-gcc ...``.
+
+.. option:: AR
+
+   Optionally overrides the default :command:`ar` (archive) binary used by
+   the Verilated makefiles. If AR is not set, the version found at
+   configure time is used.
+
+.. option:: CXX
+
+   Optionally overrides the default compiler binary used by the Verilated
+   makefiles. If CXX is not set, the version found at configure time is
+   used.  Note the default flags passed to the compiler are determined at
+   configuration time, so changing the CXX compiler version using this
+   variable, as opposed to passing it at configuration time, may not give
+   desired results.
+
+.. option:: LINK
+
+   Optionally overrides the default linker binary used by the Verilated
+   makefiles. If LINK is not set, the version found at configure time is
+   used.  Note the default flags passed to the linker are determined at
+   configuration time, so changing the LINK version using this variable, as
+   opposed to passing it at configuration time, may not give desired
+   results.
+
+.. option:: PERL
+
+   Optionally overrides the default :command:`perl` binary used by the
+   Verilated makefiles. If PERL is not set, the version found at configure
+   time, and compiled into the Verilator binary, is used.
+
+.. option:: PYTHON3
+
+   Optionally overrides the default :command:`python3` binary used by the
+   Verilated makefiles. If PYTHON3 is not set, the version found at
+   configure time is used.

docs/guide/example_binary.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Example Create-Binary Execution:

docs/guide/example_cc.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Example C++ Execution:

docs/guide/example_common_install.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 First you need Verilator installed, see :ref:`Installation`.  In brief, if

docs/guide/example_dist.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Examples in the Distribution:

docs/guide/example_sc.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Example SystemC Execution:
@@ -28,6 +28,7 @@ Now, let's create an example Verilog, and SystemC wrapper file:
 
      cat >sc_main.cpp <<'EOF'
        #include "Vour.h"
+       using namespace sc_core;
        int sc_main(int argc, char** argv) {
            Verilated::commandArgs(argc, argv);
            sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};

docs/guide/examples.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Examples:
@@ -9,6 +9,7 @@ Examples
 
 This section covers the following examples:
 
+* :ref:`Example Create-Binary Execution`
 * :ref:`Example C++ Execution`
 * :ref:`Example SystemC Execution`
 * :ref:`Examples in the Distribution`

docs/guide/exe_sim.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Simulation Runtime Arguments:
@@ -19,11 +19,20 @@ Summary:
    .. include:: ../_build/gen/args_verilated.rst
 
 
+.. option:: +verilator+coverage+file+<filename>
+
+   When a model was Verilated using :vlopt:`--coverage`, sets the filename
+   to write coverage data into.  Defaults to :file:`coverage.dat`.
+
 .. option:: +verilator+debug
 
    Enable simulation runtime debugging.  Equivalent to
    :vlopt:`+verilator+debugi+4 <+verilator+debugi+\<value\>>`.
 
+   To be useful, the model typically must first be compiled with debug
+   capabilities by Verilating with :vlopt:`--runtime-debug` or `-CFLAGS
+   -DVL_DEBUG=1`.
+
 .. option:: +verilator+debugi+<value>
 
    Enable simulation runtime debugging at the provided level.
@@ -31,13 +40,18 @@ Summary:
 .. option:: +verilator+error+limit+<value>
 
    Set number of non-fatal errors (e.g. assertion failures) before exiting
-   simulation runtime. Also affects number of $stop calls needed before
+   simulation runtime. Also affects number of `$stop` calls needed before
-   exit. Defaults to 1.
+   exit. Does not affect `$fatal`. Defaults to 1.
 
 .. option:: +verilator+help
 
    Display help and exit.
 
+.. option:: +verilator+noassert
+
+   Disable assert checking per runtime argument. This is the same as
+   calling :code:`VerilatedContext*->assertOn(false)` in the model.
+
 .. option:: +verilator+prof+exec+file+<filename>
 
    When a model was Verilated using :vlopt:`--prof-exec`, sets the
@@ -64,15 +78,18 @@ Summary:
 
 .. option:: +verilator+prof+threads+file+<filename>
 
-   Deprecated. Alias for :vlopt:`+verilator+prof+exec+file+\<filename\>`
+   Removed in 5.020. Was an alias for
+   :vlopt:`+verilator+prof+exec+file+\<filename\>`
 
 .. option:: +verilator+prof+threads+start+<value>
 
-   Deprecated. Alias for :vlopt:`+verilator+prof+exec+start+\<value\>`
+   Removed in 5.020. Was an alias for
+   :vlopt:`+verilator+prof+exec+start+\<value\>`
 
 .. option:: +verilator+prof+threads+window+<value>
 
-   Deprecated. Alias for :vlopt:`+verilator+prof+exec+window+\<value\>`
+   Removed in 5.020. Was an alias for
+   :vlopt:`+verilator+prof+exec+window+\<value\>`
 
 .. option:: +verilator+prof+vlt+file+<filename>
 
@@ -80,6 +97,11 @@ Summary:
    profile-guided optimization data runtime filename to dump to.  Defaults
    to :file:`profile.vlt`.
 
+.. option:: +verilator+quiet
+
+   Disable printing the simulation summary report, see :ref:`Simulation
+   Summary Report`.
+
 .. option:: +verilator+rand+reset+<value>
 
    When a model was Verilated using
@@ -93,11 +115,6 @@ Summary:
    simulation runtime random seed value.  If zero or not specified picks a
    value from the system random number generator.
 
-.. option:: +verilator+noassert
-
-   Disable assert checking per runtime argument. This is the same as
-   calling :code:`VerilatedContext*->assertOn(false)` in the model.
-
 .. option:: +verilator+V
 
    Shows the verbose version, including configuration information.

docs/guide/exe_verilator_coverage.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_coverage
@@ -35,11 +35,11 @@ verilator_coverage Example Usage
     verilator_coverage --help
     verilator_coverage --version
 
-    verilator_coverage --annotate <obj>
+    verilator_coverage --annotate obj_dir coverage.dat
 
-    verilator_coverage  -write merged.dat -read <datafiles>...
+    verilator_coverage --write merged.dat coverage.dat ...
 
-    verilator_coverage  -write-info merged.info -read <datafiles>...
+    verilator_coverage --write-info merged.info coverage.dat ...
 
 
 verilator_coverage Arguments
@@ -49,86 +49,125 @@ verilator_coverage Arguments
 
 .. option:: <filename>
 
-Specifies the input coverage data file.  Multiple filenames may be provided
+   Specifies the input coverage data file.  Multiple filenames may be
-to read multiple inputs.  If no data file is specified, by default,
+   provided to read multiple inputs.  If no data file is specified, by
-"coverage.dat" will be read.
+   default, "coverage.dat" will be read.
 
 .. option:: --annotate <output_directory>
 
-Specifies the directory name to which source files with annotated coverage
+   Specifies the directory name to which source files with annotated
-data should be written.
+   coverage data should be written.
 
-Converting from the Verilator coverage data format to the info format is
+   Points are children of each line coverage- branches, expressions or
-lossy; the info will have all forms of coverage merged line coverage, and
+   toggle points.  When point counts are aggregated into a line, the
-if there are multiple coverage points on a single line they will merge.
+   minimum and maximum counts are used to determine the status of the line
-The minimum coverage across all merged points will be used to report
+   (complete, partial, failing) The count is equal to the maximum of the
-coverage of the line.
+   points.
 
-The first character of the line shows a summary of the coverage; this
+   Coverage data is annotated at the beginning of the line and is formatted
-allows use of grep to filter the report.  `%` indicates at least one point
+   as a special character followed by the number of coverage hits. The
-on the line was below the coverage limit.  `+` indicates an
+   special characters " ,%,~,+,-" indicate summary of the coverage, and
-:option:`--annotate-points` point was at or above the limit, and `-` that
+   allow use of grep to filter the report.
-the point was below the limit.
+
+   * " " (whitespace) indicates that all points on the line are above the coverage min.
+   * "%" indicates that all points on the line are below the coverage min.
+   * "~" indicates that some points on the line are above the coverage min and some are below.
+   * "+" coverage point was at or above the min. Only used with :option:`--annotate-points`.
+   * "-" coverage point was below the min.  Only used with :option:`--annotate-points`.
+
+   .. code-block::
+
+      100000  input logic a;      // Begins with whitespace, because
+                                  // number of hits (100000) is above the min.
+     +100000  point: comment=a    // Begins with +, because
+                                  // number of hits (100000) is above the min.
+     %000000  input logic b;      // Begins with %, because
+                                  // number of hits (0) is below the min.
+     -000000  point: comment=b    // Begins with -, because
+                                  // number of hits (0) is below the min.
+     ~000010  if (cyc!=0) begin   // Begins with ~, because
+                                  // branches are below and above the min.
+     +000010  point: comment=if   // The if branch is above the min.
+     -000000  point: comment=else // The else branch is below the min.
 
 .. option:: --annotate-all
 
-Specifies all files should be shown.  By default, only those source files
+   Specifies all files should be shown.  By default, only those source
-with low coverage are written to the output directory.
+   files with low coverage are written to the output directory.
+
+   This option should be used together with :option:`--annotate`.
 
 .. option:: --annotate-min <count>
 
-Specifies if the coverage point does not include the count number of
+   Specifies the threshold (<count>) below which coverage point is
-coverage hits, then the coverage point will be considered above the
+   considered sufficient. If the threshold is not exceeded, then the
-threshold, and the coverage report will put a "%" to indicate the coverage
+   annotation will begin with a "%" symbol to indicate the coverage is
-is insufficient.  Defaults to 10.
+   insufficient.
+
+   The <count> threshold defaults to 10.
+
+   This option should be used together with :option:`--annotate`.
+
 
 .. option:: --annotate-points
 
-Specifies all coverage points should be shown after each line of text.  By
+   Specifies all coverage points should be shown after each line of text.  By
-default, only source lines are shown.
+   default, only source lines are shown.
 
-with low coverage are written to the output directory.
+   .. code-block::
+
+     100000  input logic a, b, c;
+    +100000 point: comment=a  // These lines are only shown
+    +200000 point: comment=b  // with option --annotate-points
+    +300000 point: comment=c  // enabled.
+
+
+   This option should be used together with :option:`--annotate`.
+
+.. option:: --filter-type <regex>
+
+   Skips records of coverage types that matches with <regex>
+   Possible values are `toggle`, `line`, `branch`, `expr`, `user` and
+   a wildcard with `\*` or `?`. The default value is `\*`.
 
 .. option:: --help
 
-Displays a help summary, the program version, and exits.
+   Displays a help summary, the program version, and exits.
 
 .. option:: --rank
 
-Prints an experimental report listing the relative importance of each test
+   Prints an experimental report listing the relative importance of each
-in covering all of the coverage points.  The report shows "Covered" which
+   test in covering all of the coverage points.  The report shows "Covered"
-indicates the number of points the test covers; a test is considered to
+   which indicates the number of points the test covers; a test is
-cover a point if it has a bucket count of at least 1. The "rank" column has
+   considered to cover a point if it has a bucket count of at least 1. The
-a higher number t indicate the test is more critical, and rank 0 means the
+   "rank" column has a higher number t indicate the test is more critical,
-test does not need to be run to cover the points.  "RankPts" indicates the
+   and rank 0 means the test does not need to be run to cover the points.
-number of coverage points this test will contribute to overall coverage if
+   "RankPts" indicates the number of coverage points this test will
-all tests are run in the order of highest to the lowest rank.
+   contribute to overall coverage if all tests are run in the order of
+   highest to the lowest rank.
 
 .. option:: --unlink
 
-With :option:`--write`, unlink all input files after the output
+   With :option:`--write`, unlink all input files after the output has been
-has been successfully created.
+   successfully created.
 
 .. option:: --version
 
-Displays program version and exits.
+   Displays program version and exits.
 
 .. option:: --write <filename>
 
-Specifies the aggregate coverage results, summed across all the files,
+   Specifies the aggregate coverage results, summed across all the files,
-should be written to the given filename in verilator_coverage data format.
+   should be written to the given filename in verilator_coverage data
-This is useful in scripts to combine many coverage data files (likely
+   format.  This is useful in scripts to combine many coverage data files
-generated from random test runs) into one master coverage file.
+   (likely generated from random test runs) into one master coverage file.
 
 .. option:: --write-info <filename.info>
 
-Specifies the aggregate coverage results, summed across all the files,
+   Specifies the aggregate coverage results, summed across all the files,
-should be written to the given filename in :command:`lcov` .info format.
+   should be written to the given filename in :command:`lcov` .info format.
-This may be used to feed into :command:`lcov` to aggregate or generate
+   This may be used to feed into :command:`lcov` to aggregate or generate
-reports.
+   reports. This format lacks the comments for cover points that the
-
+   verilator_coverage format has. It can be used with :command:`genhtml` to
-Converting from the Verilator coverage data format to the info format is
+   generate an HTML report. :command:`genhtml --branch-coverage` will also
-lossy; the info will have all forms of coverage merged line coverage, and
+   display the branch coverage, analogous to :option:`--annotate-points`.
-if there are multiple coverage points on a single line they will merge.
-The minimum coverage across all merged points will be used to report
-coverage of the line.

docs/guide/exe_verilator_gantt.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_gantt
@@ -30,15 +30,13 @@ Gantt Chart VCD Signals
 In waveforms, there are the following signals. In GTKWave, use "decimal"
 data format to remove the leading zeros and make the traces easier to read.
 
-evals
+trace/section
-  Increments each time when eval_step was measured to be active.  This
+  Shows the name of the current top of the execution section stack.
-  allow visualization of how much time eval_step was active.
+  Set GTKWave data format to "ASCII".
 
-eval_loop
+trace/depth
-  Increments each time when the evaluation loop within eval_step was
+  Shows the depth of the execution section stack.
-  measured to be active.  For best performance, there is only a single
+  Set GTKWave data format to "Analog".
-  evaluation loop within each eval_step call; that is, the eval_loop
-  waveform looks identical to the evals waveform.
 
 measured_parallelism
   The number of mtasks active at this time, for best performance, this will
@@ -53,6 +51,10 @@ predicted_parallelism
 cpu#_thread
   For the given CPU number, the thread number measured to be executing.
 
+cpu#_waiting
+  For the given CPU number, aggregated waiting time for mtask dependencies.
+  Visualized as `X` values.
+
 mtask#_cpu
   For the given mtask id, the CPU it was measured to execute on.
 
@@ -64,6 +66,17 @@ predicted_thread#_mtask
   executing.
 
 
+verilator_gantt Example Usage
+-----------------------------
+
+..
+
+    verilator_gantt --help
+    verilator_gantt --version
+
+    verilator_gantt profile_exec.dat
+
+
 verilator_gantt Arguments
 -------------------------
 
@@ -71,16 +84,16 @@ verilator_gantt Arguments
 
 .. option:: <filename>
 
-The filename to read data from; the default is "profile_exec.dat".
+   The filename to read data from; the default is "profile_exec.dat".
 
 .. option:: --help
 
-Displays a help summary, the program version, and exits.
+   Displays a help summary, the program version, and exits.
 
 .. option:: --no-vcd
 
-Disables creating a .vcd file.
+   Disables creating a .vcd file.
 
 .. option:: --vcd <filename>
 
-Sets the output filename for vcd dump; the default is "verilator_gantt.vcd".
+   Sets the output filename for vcd dump; the default is "verilator_gantt.vcd".

docs/guide/exe_verilator_profcfunc.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_profcfunc
@@ -15,6 +15,17 @@ reported as a rounding error.
 
 For an overview of the use of verilator_profcfunc, see :ref:`Profiling`.
 
+verilator_profcfunc Example Usage
+---------------------------------
+
+..
+
+    verilator_profcfunc --help
+    verilator_profcfunc --version
+
+    verilator_profcfunc gprof.out
+
+
 verilator_profcfunc Arguments
 -----------------------------
 
@@ -22,8 +33,8 @@ verilator_profcfunc Arguments
 
 .. option:: <filename>
 
-The :command:`gprof`-generated filename to read data from. Typically "gprof.out".
+   The :command:`gprof`-generated filename to read data from. Typically "gprof.out".
 
 .. option:: --help
 
-Displays a help summary, the program version, and exits.
+   Displays a help summary, the program version, and exits.

docs/guide/executables.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *********************************

docs/guide/extensions.rst

@@ -1,14 +1,19 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-*******************
+=====================
-Language Extensions
+ Language Extensions
-*******************
+=====================
 
 The following additional constructs are the extensions Verilator supports
 on top of standard Verilog code.  Using these features outside of comments
 or "`ifdef`"'s may break other tools.
 
+.. option:: """ [string] """
+
+   A triple-quoted block specifies a string that may include newlines and
+   single quotes.  This extension was standardized in IEEE 1800-2023.
+
 .. option:: `__FILE__
 
    The :option:`\`__FILE__` define expands to the current filename as a
@@ -17,19 +22,139 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: `__LINE__
 
-   The :option:`\`__LINE__` define expands to the current filename as a
+   The :option:`\`__LINE__` define expands to the current line number like
-   string, like C++'s __LINE__.  This Verilator feature added in 2006 was
+   C++'s __LINE__.  This Verilator feature added in 2006 was incorporated
-   incorporated into IEEE 1800-2009.
+   into IEEE 1800-2009.
+
+.. option:: `coverage_block_off
+
+   Specifies the entire begin/end block should be ignored for coverage
+   analysis.  Must be inside a code block, e.g., within a begin/end pair.
+   Same as :option:`coverage_block_off` in :ref:`Verilator Control Files`.
 
 .. option:: `error [string]
 
-   This will report an error when encountered, like C++'s #error.
+   This will report an error when the preprocessor emits it, similar to
+   C++'s #error.
 
-.. option:: """ [string] """
+.. option:: `line
 
-   A triple-quoted block specifies a string that may include newlines and
+   As a special case `\`line \`__LINE__ "filename"` allows setting the
-   single quotes.  This extension is experimental and may be removed
+   filename, without changing the line number. This is used for some
-   without deprecation.
+   internal tests, so that debugging can leave the line numbers correctly
+   referring to the test file's line numbers.
+
+.. option:: `systemc_class_name
+
+   Inside one of the :option:`\`systemc_... <\`systemc_header>` text
+   blocks, replaced with the C++ class name generated for the given
+   containing SystemVerilog class or module. Currently this is replaced
+   blindly, ignoring quoting or other escapes; this behavior may change in
+   the future.  This attribute is indented only to be used internally in
+   `verilated_std.sv`.
+
+.. option:: `systemc_ctor
+
+   Take the remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into the C++ class constructor.  Must be placed as a module or
+   class item, e.g., directly inside a module/endmodule or class/endclass
+   pair. Despite the name of this macro, this also works in pure C++ code.
+
+.. option:: `systemc_dtor
+
+   Take the remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into the C++ class destructor.  Must be placed as a module or
+   class item, e.g., directly inside a module/endmodule or class/endclass
+   pair. Despite the name of this macro, this also works in pure C++ code.
+
+.. option:: `systemc_header
+
+   Take the remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into the output .h file's header.  Must be placed as a module
+   or class item, e.g., directly inside a module/endmodule or
+   class/endclass pair. Despite the name of this macro, this also works in
+   pure C++ code.
+
+.. option:: `systemc_header_post
+
+   Take the remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into the output .h file's header after the class definition.
+   Must be placed as a module or class item, e.g., directly inside a
+   module/endmodule or class/endclass pair. Despite the name of this macro,
+   this also works in pure C++ code.
+
+.. option:: `systemc_imp_header
+
+   Take the remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into the header of all files for this C++ class implementation.
+   Must be placed as a module or class item, e.g., directly inside a
+   module/endmodule or class/endclass pair. Despite the name of this macro,
+   this also works in pure C++ code.
+
+.. option:: `systemc_implementation
+
+   Take the remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into a single file of the C++ class implementation.  Must be
+   placed as a module or class item, e.g., directly inside a
+   module/endmodule or class/endclass pair. Despite the name of this macro,
+   this also works in pure C++ code.
+
+   If you will be reading or writing any Verilog variables in the C++
+   functions, the Verilog signals must be declared with a
+   :option:`/*verilator&32;public*/` metacomment.  See also the public task
+   feature; writing an accessor may result in cleaner code.
+
+.. option:: `systemc_interface
+
+   Take the remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into the C++ class interface.  Must be placed as a module or
+   class item, e.g., directly inside a module/endmodule or class/endclass
+   pair. Despite the name of this macro, this also works in pure C++ code.
+
+.. option:: `SYSTEMVERILOG
+
+   The SYSTEMVERILOG, SV_COV_START, and related standard predefined macros
+   are defined by default when :vlopt:`--language <--language>` is
+   "1800-\*".
+
+.. option:: `VERILATOR
+
+.. option:: `verilator
+
+.. option:: `verilator3
+
+   The VERILATOR, verilator and verilator3 predefined macros are defined by
+   default so you may "\`ifdef" around tool specific constructs.
+
+.. option:: `verilator_config
+
+   Take the remaining text up to the next :option:`\`verilog` mode switch
+   and treat it as Verilator Control File commands.  See :ref:`Verilator
+   Control Files`.
+
+.. option:: `VERILATOR_TIMING
+
+   The VERILATOR_TIMING define is set when :vlopt:`--timing` is used to
+   allow an "\`ifdef" of code dependent on this feature.  Note that this define
+   is not affected by the :option:`timing_off` control file option
+   nor timing metacomments.
+
+.. option:: `verilog
+
+   Switch back to processing Verilog code after a
+   :option:`\`systemc_... <\`systemc_header>` mode switch.  The Verilog
+   code returns to the last language mode specified with
+   "\`begin_keywords", or SystemVerilog if none was specified.
+
+
+   .. t_dist_docs_style restart_sort
 
 .. option:: $c([string], ...);
 
@@ -79,6 +204,16 @@ or "`ifdef`"'s may break other tools.
    prints 5 digits per the C standard. This extension was standardized into
    1800-2009.
 
+.. option:: $stacktrace
+
+   Called as a task, print a stack trace.  Called as a function, return a
+   string with a stack trace.  This relies on the C++ system trace, which
+   may give less meaningful results if the model is not compiled with debug
+   symbols.  Also, the data represents the C++ stack; the SystemVerilog
+   functions/tasks involved may be renamed and/or inlined before becoming
+   the C++ functions that may be visible in the stack trace.  This
+   extension was standardized in IEEE 1800-2023.
+
 .. option:: $timeprecision
 
    Returns the timeprecision of the model as an integer.  This extension is
@@ -89,98 +224,6 @@ or "`ifdef`"'s may break other tools.
    Returns the timeunit of the current module as an integer.  This
    extension is experimental and may be removed without deprecation.
 
-.. option:: `coverage_block_off
-
-   Specifies the entire begin/end block should be ignored for coverage
-   analysis.  Must be inside a code block, e.g., within a begin/end pair.
-   Same as :option:`coverage_block_off` in :ref:`Configuration Files`.
-
-.. option:: `systemc_header
-
-   Take the remaining text up to the next :option:`\`verilog` or
-   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
-   verbatim into the output .h file's header.  Must be placed as a module
-   item, e.g., directly inside a module/endmodule pair. Despite the name of
-   this macro, this also works in pure C++ code.
-
-.. option:: `systemc_ctor
-
-   Take the remaining text up to the next :option:`\`verilog` or
-   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
-   verbatim into the C++ class constructor.  Must be placed as a module
-   item, e.g., directly inside a module/endmodule pair. Despite the name of
-   this macro, this also works in pure C++ code.
-
-.. option:: `systemc_dtor
-
-   Take the remaining text up to the next :option:`\`verilog` or
-   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
-   verbatim into the C++ class destructor.  Must be placed as a module
-   item, e.g., directly inside a module/endmodule pair. Despite the name of
-   this macro, this also works in pure C++ code.
-
-.. option:: `systemc_interface
-
-   Take the remaining text up to the next :option:`\`verilog` or
-   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
-   verbatim into the C++ class interface.  Must be placed as a module item,
-   e.g., directly inside a module/endmodule pair. Despite the name of this
-   macro, this also works in pure C++ code.
-
-.. option:: `systemc_imp_header
-
-   Take the remaining text up to the next :option:`\`verilog` or
-   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
-   verbatim into the header of all files for this C++ class implementation.
-   Must be placed as a module item, e.g., directly inside a module/endmodule
-   pair. Despite the name of this macro, this also works in pure C++ code.
-
-.. option:: `systemc_implementation
-
-   Take the remaining text up to the next :option:`\`verilog` or
-   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
-   verbatim into a single file of the C++ class implementation.  Must be
-   placed as a module item, e.g., directly inside a module/endmodule
-   pair. Despite the name of this macro, this also works in pure C++ code.
-
-   If you will be reading or writing any Verilog variables in the C++
-   functions, the Verilog signals must be declared with a
-   :option:`/*verilator&32;public*/` metacomment.  See also the public task
-   feature; writing an accessor may result in cleaner code.
-
-.. option:: `SYSTEMVERILOG
-
-   The SYSTEMVERILOG, SV_COV_START, and related standard defines are set by
-   default when :vlopt:`--language <--language>` is "1800-\*".
-
-.. option:: `VERILATOR
-
-.. option:: `verilator
-
-.. option:: `verilator3
-
-   The VERILATOR, verilator and verilator3 defines are set by default so
-   you may "\`ifdef" around tool specific constructs.
-
-.. option:: `verilator_config
-
-   Take the remaining text up to the next :option:`\`verilog` mode switch and
-   treat it as Verilator configuration commands.  See :ref:`Configuration Files`.
-
-.. option:: `VERILATOR_TIMING
-
-   The VERILATOR_TIMING define is set when :vlopt:`--timing` is used to
-   allow an "\`ifdef" of code dependent on this feature.  Note that this define
-   is not affected by the :option:`timing_off` configuration file option
-   nor timing metacomments.
-
-.. option:: `verilog
-
-   Switch back to processing Verilog code after a
-   :option:`\`systemc_... <\`systemc_header>` mode switch.  The Verilog
-   code returns to the last language mode specified with
-   "\`begin_keywords", or SystemVerilog if none was specified.
-
 .. option:: /*verilator&32;clock_enable*/
 
    Deprecated and has no effect (ignored).
@@ -203,7 +246,10 @@ or "`ifdef`"'s may break other tools.
    the scheduling algorithm, sometimes required for correct clock behavior,
    and always improving performance.
 
-   Same as :option:`clock_enable` configuration file option.
+   Same as :option:`clock_enable` control file option.
+
+
+   .. t_dist_docs_style ignore /*verilator&32;no_clocker*/
 
 .. option:: /*verilator&32;clocker*/
 
@@ -219,7 +265,7 @@ or "`ifdef`"'s may break other tools.
    Specifies the entire begin/end block should be ignored for coverage
    analysis purposes.
 
-   Same as :option:`coverage_block_off` configuration file option.
+   Same as :option:`coverage_block_off` control file option.
 
 .. option:: /*verilator&32;coverage_off*/
 
@@ -267,7 +313,7 @@ or "`ifdef`"'s may break other tools.
    submodules will be named :code:`{submodule}__DOT__{subsignal}` as C++
    does not allow "." in signal names.
 
-   Same as :option:`inline` configuration file option.
+   Same as :option:`inline` control file option.
 
 .. option:: /*verilator&32;isolate_assignments*/
 
@@ -310,7 +356,7 @@ or "`ifdef`"'s may break other tools.
            end
          end
 
-   Same as :option:`isolate_assignments` configuration file option.
+   Same as :option:`isolate_assignments` control file option.
 
 .. option:: /*verilator&32;lint_off <msg>*/
 
@@ -349,7 +395,7 @@ or "`ifdef`"'s may break other tools.
    Specifies the module the comment appears in should not be inlined into
    any modules that use this module.
 
-   Same as :option:`no_inline` configuration file option.
+   Same as :option:`no_inline` control file option.
 
 .. option:: /*verilator&32;no_inline_task*/
 
@@ -360,7 +406,7 @@ or "`ifdef`"'s may break other tools.
    must be pure; they cannot reference any variables outside the task
    itself.
 
-   Same as :option:`no_inline` configuration file option.
+   Same as :option:`no_inline` control file option.
 
 .. option:: /*verilator&32;public*/ (on parameter)
 
@@ -372,29 +418,6 @@ or "`ifdef`"'s may break other tools.
 
          parameter [2:0] PARAM /*verilator public*/ = 2'b0;
 
-.. option:: /*verilator&32;public*/ (on typedef enum)
-
-   Used after an enum typedef declaration to indicate the emitted C code
-   should have the enum values visible. Due to C++ language restrictions,
-   this may only be used on 64-bit or narrower integral enumerations.
-
-   .. code-block:: sv
-
-         typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/;
-
-.. option:: /*verilator&32;public*/ (on variable)
-
-   Used after an input, output, register, or wire declaration to indicate
-   the signal should be declared so that C code may read or write the value
-   of the signal.  This will also declare this module public; otherwise, use
-   :code:`/*verilator&32;public_flat*/`.
-
-   Instead of using public variables, consider making a DPI or public
-   function that accesses the variable.  This is nicer as it provides an
-   obvious entry point compatible across simulators.
-
-   Same as :option:`public` configuration file option.
-
 .. option:: /*verilator&32;public*/ (on task/function)
 
    Used inside the declaration section of a function or task declaration to
@@ -417,34 +440,30 @@ or "`ifdef`"'s may break other tools.
    You may want to use DPI exports instead, as it's compatible with other
    simulators.
 
-   Same as :option:`public` configuration file option.
+   Same as :option:`public` control file option.
 
-.. option:: /*verilator&32;public_flat*/ (on variable)
+.. option:: /*verilator&32;public*/ (on typedef enum)
+
+   Used after an enum typedef declaration to indicate the emitted C code
+   should have the enum values visible. Due to C++ language restrictions,
+   this may only be used on 64-bit or narrower integral enumerations.
+
+   .. code-block:: sv
+
+         typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/;
+
+.. option:: /*verilator&32;public*/ (on variable)
 
    Used after an input, output, register, or wire declaration to indicate
    the signal should be declared so that C code may read or write the value
-   of the signal.  This will not declare this module public, which means
+   of the signal.  This will also declare this module public; otherwise, use
-   the name of the signal or path to it may change based upon the module
+   :code:`/*verilator&32;public_flat*/`.
-   inlining which takes place.
 
-   Same as :option:`public_flat` configuration file option.
+   Instead of using public variables, consider making a DPI or public
+   function that accesses the variable.  This is nicer as it provides an
+   obvious entry point compatible across simulators.
 
-.. option:: /*verilator&32;public_flat_rd*/ (on variable)
+   Same as :option:`public` control file option.
-
-   Used after an input, output, register, or wire declaration to indicate
-   the signal should be declared public_flat (see above), but read-only.
-
-   Same as :option:`public_flat_rd` configuration file option.
-
-.. option:: /*verilator&32;public_flat_rw @(<edge_list>)*/ (on variable)
-
-   Used after an input, output, register, or wire declaration to indicate
-   the signal should be declared public_flat_rd (see above), and writable,
-   where writes should be considered to have the timing specified by the
-   given sensitivity edge list. Use of this is implied when using the
-   :vlopt:`--public-flat-rw` option.
-
-   Same as :option:`public_flat_rw` configuration file option.
 
 .. option:: /*verilator&32;public_[|flat|flat_rd|flat_rw]_on [@(<edge_list>)]*/ (as scope)
 
@@ -469,9 +488,32 @@ or "`ifdef`"'s may break other tools.
          parameter width /*verilator public_flat_rw*/ = 8;
          logic data;
 
-.. option:: /*verilator&32;public_off*/
+.. option:: /*verilator&32;public_flat*/ (on variable)
 
-   Terminates the previous `/*verilator public*_on*/` directive; see above.
+   Used after an input, output, register, or wire declaration to indicate
+   the signal should be declared so that C code may read or write the value
+   of the signal.  This will not declare this module public, which means
+   the name of the signal or path to it may change based upon the module
+   inlining which takes place.
+
+   Same as :option:`public_flat` control file option.
+
+.. option:: /*verilator&32;public_flat_rd*/ (on variable)
+
+   Used after an input, output, register, or wire declaration to indicate
+   the signal should be declared public_flat (see above), but read-only.
+
+   Same as :option:`public_flat_rd` control file option.
+
+.. option:: /*verilator&32;public_flat_rw @(<edge_list>)*/ (on variable)
+
+   Used after an input, output, register, or wire declaration to indicate
+   the signal should be declared public_flat_rd (see above), and writable,
+   where writes should be considered to have the timing specified by the
+   given sensitivity edge list. Use of this is implied when using the
+   :vlopt:`--public-flat-rw` option.
+
+   Same as :option:`public_flat_rw` control file option.
 
 .. option:: /*verilator&32;public_module*/
 
@@ -481,15 +523,11 @@ or "`ifdef`"'s may break other tools.
    contains public signals or \`systemc_ directives.  Use of this is
    implied when using the :vlopt:`--public` option.
 
-   Same as :option:`public` configuration file option.
+   Same as :option:`public` control file option.
 
-.. option:: /*verilator&32;sc_clock*/
+.. option:: /*verilator&32;public_off*/
 
-   Deprecated and ignored.  Previously used after an input declaration to
+   Terminates the previous `/*verilator public*_on*/` directive; see above.
-   indicate the signal should be declared in SystemC as a sc_clock instead
-   of a bool.  This was needed in SystemC 1.1 and 1.2 only; versions 2.0
-   and later do not require clock pins to be sc_clocks, and this is no
-   longer needed and is ignored.
 
 .. option:: /*verilator&32;sc_bv*/
 
@@ -500,7 +538,15 @@ or "`ifdef`"'s may break other tools.
    In general, you should avoid using this attribute when unnecessary, as
    the performance decreases significantly with increasing usage of sc_bv.
 
-   Same as :option:`sc_bv` configuration file option.
+   Same as :option:`sc_bv` control file option.
+
+.. option:: /*verilator&32;sc_clock*/
+
+   Deprecated and ignored.  Previously used after an input declaration to
+   indicate the signal should be declared in SystemC as a sc_clock instead
+   of a bool.  This was needed in SystemC 1.1 and 1.2 only; versions 2.0
+   and later do not require clock pins to be sc_clocks, and this is no
+   longer needed and is ignored.
 
 .. option:: /*verilator&32;sformat*/
 
@@ -510,7 +556,7 @@ or "`ifdef`"'s may break other tools.
    $display-like behavior.  See the :file:`test_regress/t/t_dpi_display.v`
    file for an example.
 
-   Same as :option:`sformat` configuration file option.
+   Same as :option:`sformat` control file option.
 
 .. option:: /*verilator&32;split_var*/
 
@@ -543,7 +589,21 @@ or "`ifdef`"'s may break other tools.
    large arrays may slow down the Verilation speed, so use this only on
    variables that require it.
 
-   Same as :option:`split_var` configuration file option.
+   Packed variables that are only referenced locally (without hierarchical
+   references) via non-overlapping, constant-indexed bit or part select
+   expressions are split automatically. This covers the somewhat common
+   usage pattern:
+
+   .. code-block:: sv
+
+         logic [1:0][31:0] tmp;
+
+         assign tmp[0] = foo    + a;
+         assign tmp[1] = tmp[1] + b;
+         assign bar    = tmp[1] + c;
+
+
+   Same as :option:`split_var` control file option.
 
 .. option:: /*verilator&32;tag <text...>*/
 
@@ -558,21 +618,25 @@ or "`ifdef`"'s may break other tools.
    :option:`--no-timing`), and :code:`fork`/:code:`join*` blocks are
    converted into :code:`begin`/:code:`end` blocks.
 
-   Same as :option:`timing_off` configuration file option.
+   Same as :option:`timing_off` control file option.
 
 .. option:: /*verilator&32;timing_on*/
 
    Re-enable all timing constructs after this metacomment (only applicable
    after :option:`timing_off`).
 
-   Same as :option:`timing_on` configuration file option.
+   Same as :option:`timing_on` control file option.
 
 .. option:: /*verilator&32;trace_init_task*/
 
+   Removed.
+
+   In versions before 5.024:
+
    Attached to a DPI import to indicate that function should be called when
    initializing tracing. This attribute is indented only to be used
    internally in code that Verilator generates when :vlopt:`--lib-create`
-   or :vlopt:`--hierarchical` is used along with :vlopt:`--trace`.
+   or :vlopt:`--hierarchical` is used along with :vlopt:`--trace-vcd`.
 
 .. option:: /*verilator&32;tracing_off*/
 
@@ -586,12 +650,19 @@ or "`ifdef`"'s may break other tools.
    Re-enable waveform tracing for all future signals or instances that are
    declared.
 
-.. option:: $stacktrace
+.. option:: /*verilator&32;unroll_disable*/
 
-   Called as a task, print a stack trace.  Called as a function, return a
+   Used in a statement position to indicate the immediately following loop
-   string with a stack trace.  This relies on the C++ system trace, which
+   at the same statement level should not be unrolled by Verilator,
-   may give less meaningful results if the model is not compiled with debug
+   ignoring :vlopt:`--unroll-count`.  This is similar to clang's ``#pragma
-   symbols.  Also, the data represents the C++ stack; the SystemVerilog
+   clang loop unroll(disable)``.
-   functions/tasks involved may be renamed and/or inlined before becoming
+
-   the C++ functions that may be visible in the stack trace.  This
+   This option does not currently disable the C++ compiler's unrolling (or
-   extension is experimental and may be removed without deprecation.
+   not) of any loops that make it through to the Verilated C++ code.
+
+.. option:: /*verilator&32;unroll_full*/
+
+   Rarely needed. Used in a statement position to indicate the immediately
+   following loop at the same statement level should always be fully
+   unrolled by Verilator, ignoring :vlopt:`--unroll-count`.  This is
+   similar to clang's ``#pragma clang loop unroll(full)``.

docs/guide/faq.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ******************************
@@ -128,10 +128,13 @@ How do I generate waveforms (traces) in C++?
 
 See also the next question for tracing in SystemC mode.
 
-A. Pass the :vlopt:`--trace` option to Verilator, and in your top-level C
+A. Pass the :vlopt:`--trace-vcd` option to Verilator.  Then you may use ``$dumpfile`` and
-   code, call ``Verilated::traceEverOn(true)``.  Then you may use
+   ``$dumpvars`` to enable traces, the same as with any Verilog simulator,
-   ``$dumpfile`` and ``$dumpvars`` to enable traces, the same as with any
+   although Verilator ignores the arguments to ``$dumpvars``. See
-   Verilog simulator. See ``examples/make_tracing_c`` in the distribution.
+   ``examples/make_tracing_c`` in the distribution.
+
+   If writing the top-level C code, call ``Verilated::traceEverOn(true)``;
+   this is done for you if using :vlopt:`--binary`.
 
 B. Or, for finer-grained control, or C++ files with multiple Verilated
    modules, you may also create the trace purely from C++.  Create a
@@ -174,7 +177,7 @@ file.
 How do I generate waveforms (traces) in SystemC?
 """"""""""""""""""""""""""""""""""""""""""""""""
 
-A. Pass the :vlopt:`--trace` option to Verilator, and in your top-level
+A. Pass the :vlopt:`--trace-vcd` option to Verilator, and in your top-level
    :code:`sc_main()`, call :code:`Verilated::traceEverOn(true)`.  Then you
    may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, as
    with any Verilog simulator; see the non-SystemC example in
@@ -220,24 +223,20 @@ This is done for you if you are using the Verilator :vlopt:`--binary` or
 You can call :code:`->trace()` on multiple Verilated objects with the same
 trace file if you want all data to land in the same output file.
 
-When using SystemC 2.3, the SystemC library must have been built with the
-experimental simulation phase callback-based tracing disabled. This is
-disabled by default when building SystemC with its configure based build
-system, but when building SystemC with CMake, you must pass
-``-DENABLE_PHASE_CALLBACKS_TRACING=OFF`` to disable this feature.
-
 
 How do I generate FST waveforms (traces) in C++ or SystemC?
 """""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
 FST is a trace file format developed by GTKWave.  Verilator provides basic
 FST support.  To dump traces in FST format, add the :vlopt:`--trace-fst`
-option to Verilator and either A. use :code:`$dumpfile & $dumpvars` in
+option to Verilator and either:
-Verilog as described in the VCD example above,
+
+Use :code:`$dumpfile & $dumpvars` in Verilog as described in the VCD
+example above,
 
 Or, in C++ change the include described in the VCD example above:
 
-.. code-block:: C++
+  .. code-block:: C++
 
       #include "verilated_fst_c.h"
       VerilatedFstC* tfp = new VerilatedFstC;
@@ -245,14 +244,14 @@ Or, in C++ change the include described in the VCD example above:
 
 Or, in SystemC, change the include described in the VCD example above:
 
-.. code-block:: C++
+  .. code-block:: C++
 
       #include "verilated_fst_sc.h"
       VerilatedFstC* tfp = new VerilatedFstSc;
 
 
-Currently, supporting FST and VCD in a single simulation is impossible, but
+Currently, supporting FST and VCD in a single simulation is not supported,
-such requirement should be rare.  You can however ifdef around the trace
+but such usage should be unlikely.  You can however ifdef around the trace
 format in your C++ main loop, and select VCD or FST at compile time.
 
 
@@ -260,9 +259,11 @@ How do I view waveforms (aka dumps or traces)?
 """"""""""""""""""""""""""""""""""""""""""""""
 
 Verilator creates standard VCD (Value Change Dump) and FST files.  VCD
-files are viewable with the open-source GTKWave (recommended), or Dinotrace
+files are viewable with the open-source
-(legacy) programs, or any of the many closed-source offerings; FST is
+`GTKWave <https://gtkwave.sourceforge.net/>`_,
-supported only by GTKWave.
+`Surfer <https://surfer-project.org/>`_, Dinotrace (legacy), or any of the
+many closed-source viewer offerings; FST is supported only by GTKWave and
+Surfer.
 
 
 How do I speed up writing large waveform (trace) files?
@@ -334,7 +335,7 @@ How do I prevent my assertions from firing during reset?
 
 Call :code:`Verilated::assertOn(false)` before you first call the model,
 then turn it back on after reset.  It defaults to true.  When false, all
-assertions controlled by :vlopt:`--assert` are disabled.
+assertions are disabled.
 
 
 Why do I get "undefined reference to sc_time_stamp()?
@@ -401,7 +402,7 @@ How do I get faster build times?
 * Use a recent compiler.  Newer compilers tend to be faster.
 
 * Compile in parallel on many machines and use caching; see the web for the
-  ccache, distcc, and icecream packages. ccache will skip GCC runs between
+  ccache, sccache, distcc, or icecream packages. ccache will skip GCC runs between
   identical source builds, even across different users.  If ccache was
   installed when Verilator was built, it is used, or see OBJCACHE
   environment variable to override this. Also see the

docs/guide/files.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *****
@@ -48,12 +48,6 @@ For --cc/--sc, it creates:
      - Make include file for compiling (from --make gmake)
    * - *{prefix}*\ _classes.mk
      - Make include file with class names (from --make gmake)
-   * - *{prefix}*\ _hier.mk
-     - Make file for hierarchy blocks (from --make gmake)
-   * - *{prefix}*\ _hierMkArgs.f
-     - Arguments for hierarchical Verilation (from --make gmake)
-   * - *{prefix}*\ _hierCMakeArgs.f
-     - Arguments for hierarchical Verilation (from --make cmake)
    * - *{prefix}*\ .h
      - Model header
    * - *{prefix}*\ .cpp
@@ -71,9 +65,9 @@ For --cc/--sc, it creates:
    * - *{prefix}*\ ___024root\ *{__DepSet_hash__n}*\ .cpp
      - Infrequent cold routines (hashed to reduce build times)
    * - *{prefix}*\ ___024root__Trace\ *{__n}*\ .cpp
-     - Wave file generation code (from --trace)
+     - Wave file generation code (from --trace-\*)
    * - *{prefix}*\ ___024root__Trace__Slow\ *{__n}*\ .cpp
-     - Wave file generation code (from --trace)
+     - Wave file generation code (from --trace-\*)
    * - *{prefix}*\ __Dpi.h
      - DPI import and export declarations (from --dpi)
    * - *{prefix}*\ __Dpi.cpp
@@ -95,21 +89,35 @@ For --cc/--sc, it creates:
    * - *{prefix}{each_verilog_module}{__DepSet_hash__n}*\ .cpp
      - Additional lower C++ files (hashed to reduce build times)
 
-For --hierarchy mode, it creates:
+For --hierarchical mode, it creates:
 
 .. list-table::
 
    * - V\ *{hier_block}*\ /
-     - Directory to Verilate each hierarchy block (from --hierarchy)
+     - Directory to Verilate each hierarchical block (from --hierarchical)
    * - *{prefix}*\ __hierVer.d
-     - Make dependencies of the top module (from --hierarchy)
+     - Make dependencies of the top module (from --hierarchical)
+   * - *{prefix}*\ _hier.mk
+     - Make file for hierarchical blocks (from --make gmake)
+   * - *{prefix}*\ __hierCMakeArgs.f
+     - Arguments for hierarchical Verilation (from --make cmake)
+   * - *{prefix}*\ __hierMkArgs.f
+     - Arguments for hierarchical Verilation (from --make gmake)
+   * - *{prefix}*\ __hierParameters.v
+     - Module parameters for hierarchical blocks
    * - *{prefix}*\ __hier.dir
-     - Directory to store .dot, .vpp, .tree of top module (from --hierarchy)
+     - Directory to store .dot, .vpp, .tree of top module (from --hierarchical)
 
 In specific debug and other modes, it also creates:
 
 .. list-table::
 
+   * - *{prefix}*\ .sarif
+     - SARIF diagnostics (from --diagnostics-sarif)
+   * - *{prefix}*\ .tree.json
+     - JSON tree information (from --json-only)
+   * - *{prefix}*\ .tree.meta.json
+     - JSON tree metadata (from --json-only)
    * - *{prefix}*\ .xml
      - XML tree information (from --xml)
    * - *{prefix}*\ __cdc.txt
@@ -145,6 +153,10 @@ After running Make, the C++ compiler may produce the following:
      - Intermediate objects
    * - *{prefix}*\
      - Final executable (from --exe)
+   * - lib\ *{prefix}*\ .a
+     - Final archive (default lib mode)
+   * - libverilated.a
+     - Runtime for verilated model (default lib mode)
    * - *{prefix}*\ __ALL.a
      - Library of all Verilated objects
    * - *{prefix}*\ __ALL.cpp

docs/guide/index.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ######################

docs/guide/install-cmake.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _CMakeInstallation:

docs/guide/install.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Installation:
@@ -15,17 +15,37 @@ Package Manager Quick Install
 =============================
 
 Using a distribution's package manager is the easiest way to get
-started. (Note packages are unlikely to have the most recent version, so
+started. (Note distribution packages almost never have the most recent
-:ref:`Git Install` might be a better alternative.) To install as a
+Verilator version, so we recommend following :ref:`Git Install` below,
-package:
+instead.) To install as a package:
 
-::
+.. code-block:: shell
 
    apt-get install verilator   # On Ubuntu
 
 For other distributions, refer to `Repology Verilator Distro Packages
 <https://repology.org/project/verilator>`__.
 
+.. _pre-commit Quick Install:
+
+pre-commit Quick Install
+=============================
+
+You can use Verilator's `pre-commit <https://pre-commit.com/>`__ hook to
+lint your code before committing it.  It encapsulates the :ref:`Verilator
+Build Docker Container`, so you need docker on your system to use it.  The
+verilator image will be downloaded automatically.
+
+To use the hook, add the following entry to your :code:`.pre-commit-config.yaml`:
+
+.. code-block:: yaml
+
+   repos:
+     - repo: https://github.com/verilator/verilator
+       rev: v5.026  # or later
+       hooks:
+         - id: verilator
+
 .. _Git Install:
 
 Git Quick Install
@@ -36,7 +56,7 @@ options and details, see :ref:`Detailed Build Instructions` below.
 
 In brief, to install from git:
 
-::
+.. code-block:: shell
 
    # Prerequisites:
    #sudo apt-get install git help2man perl python3 make autoconf g++ flex bison ccache
@@ -89,7 +109,7 @@ Install Prerequisites
 
 To build or run Verilator, you need these standard packages:
 
-::
+.. code-block:: shell
 
    sudo apt-get install git help2man perl python3 make
    sudo apt-get install g++  # Alternatively, clang
@@ -98,44 +118,59 @@ To build or run Verilator, you need these standard packages:
    sudo apt-get install libfl-dev  # Ubuntu only (ignore if gives error)
    sudo apt-get install zlibc zlib1g zlib1g-dev  # Ubuntu only (ignore if gives error)
 
+For SystemC:
+
+.. code-block:: shell
+
+   sudo apt-get install libsystemc libsystemc-dev
+
+For constraints:
+
+.. code-block:: shell
+
+   sudo apt-get install z3  # Optional solver
+
+The following is optional but is recommended for nicely rendered command line
+help when running Verilator:
+
+.. code-block:: shell
+
+   sudo apt-get install perl-doc
+
 To build or run Verilator, the following are optional but should be installed
 for good performance:
 
-::
+.. code-block:: shell
 
    sudo apt-get install ccache  # If present at build, needed for run
    sudo apt-get install mold  # If present at build, needed for run
    sudo apt-get install libgoogle-perftools-dev numactl
 
-The following is optional but is recommended for nicely rendered command line
-help when running Verilator:
-
-::
-
-   sudo apt-get install perl-doc
-
 To build Verilator you will need to install these packages; these do not
 need to be present to run Verilator:
 
-::
+.. code-block:: shell
 
    sudo apt-get install git autoconf flex bison
 
-Those developing Verilator itself may also want these (see internals.rst):
+Those developing Verilator itself also need these (see internals.rst):
 
-::
+.. code-block:: shell
 
-   sudo apt-get install clang clang-format-14 cmake gdb gprof graphviz lcov
+   sudo apt-get install clang clang-format-18 cmake gdb gprof graphviz lcov
-   sudo apt-get install libclang-dev yapf3
+   sudo apt-get install python3-clang python3-distro yapf3 bear jq
-   sudo pip3 install clang sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe ruff
+   sudo pip3 install sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe gersemi mbake ruff sarif-tools
+   sudo pip3 install git+https://github.com/antmicro/astsee.git
    cpan install Pod::Perldoc
-   cpan install Parallel::Forker
 
 
 Install SystemC
 ^^^^^^^^^^^^^^^
 
-If you will be using SystemC (vs straight C++ output), download `SystemC
+SystemC code can be generated from Verilator (with :vlopt:`--sc`) if it is
+installed as a package (see above).
+
+Alternatively, from their sources, download `SystemC
 <https://www.accellera.org/downloads/standards/systemc>`__.  Follow their
 installation instructions. You will need to set the
 :option:`SYSTEMC_INCLUDE` environment variable to point to the include
@@ -147,9 +182,24 @@ Install GTKWave
 ^^^^^^^^^^^^^^^
 
 To make use of Verilator FST tracing you will want `GTKwave
-<http://gtkwave.sourceforge.net/>`__ installed, however this is not
+<https://gtkwave.sourceforge.net/>`__ installed, however this is not
 required at Verilator build time.
 
+.. code-block:: shell
+
+    sudo apt-get install gtkwave  # Optional Waveform viewer
+
+
+Install Z3
+^^^^^^^^^^
+
+In order to use constrained randomization the `Z3 Theorem Prover
+<https://github.com/z3prover/z3>`__ must be installed, however this is
+not required at Verilator build time. There are other compatible SMT solvers,
+like CVC5/CVC4, but they are not guaranteed to work. Since different solvers are
+faster for different scenarios, the solver to use at run-time can be specified
+by the environment variable :option:`VERILATOR_SOLVER`.
+
 
 .. _Obtain Sources:
 
@@ -159,14 +209,14 @@ Obtain Sources
 Get the sources from the git repository: (You need to do this only once,
 ever.)
 
-::
+.. code-block:: shell
 
    git clone https://github.com/verilator/verilator   # Only first time
    ## Note the URL above is not a page you can see with a browser; it's for git only
 
 Enter the checkout and determine what version/branch to use:
 
-::
+.. code-block:: shell
 
    cd verilator
    git pull        # Make sure we're up-to-date
@@ -181,7 +231,7 @@ Auto Configure
 
 Create the configuration script:
 
-::
+.. code-block:: shell
 
    autoconf        # Create ./configure script
 
@@ -192,8 +242,9 @@ Eventual Installation Options
 Before configuring the build, you must decide how you're going to
 eventually install Verilator onto your system. Verilator will be compiling
 the current value of the environment variables :option:`VERILATOR_ROOT`,
-:option:`SYSTEMC_INCLUDE`, and :option:`SYSTEMC_LIBDIR` as defaults into
+:option:`VERILATOR_SOLVER`, :option:`SYSTEMC_INCLUDE`, and
-the executable, so they must be correct before configuring.
+:option:`SYSTEMC_LIBDIR` as defaults into the executable, so they must be
+correct before configuring.
 
 These are the installation options:
 
@@ -206,7 +257,7 @@ directory (don't run ``make install``). This allows the easiest
 experimentation and upgrading, and allows many versions of Verilator to
 co-exist on a system.
 
-::
+.. code-block:: shell
 
    export VERILATOR_ROOT=`pwd`   # if your shell is bash
    setenv VERILATOR_ROOT `pwd`   # if your shell is csh
@@ -228,7 +279,7 @@ that may support multiple versions of every tool. Tell configure the
 eventual destination directory name.  We recommend that the destination
 location include the Verilator version name:
 
-::
+.. code-block:: shell
 
    unset VERILATOR_ROOT      # if your shell is bash
    unsetenv VERILATOR_ROOT   # if your shell is csh
@@ -237,10 +288,10 @@ location include the Verilator version name:
 
 Note after installing (see `Installation`_), you need to add the path to
 the ``bin`` directory to your ``PATH``. Or, if you use `modulecmd
-<http://modules.sourceforge.net/>`__, you'll want a module file like the
+<https://modules.sourceforge.net/>`__, you'll want a module file like the
 following:
 
-::
+.. code-block:: shell
 
    set install_root /CAD_DISK/verilator/{version-number-used-above}
    unsetenv VERILATOR_ROOT
@@ -255,7 +306,7 @@ following:
 The final option is to eventually install Verilator globally, using
 configure's default system paths:
 
-::
+.. code-block:: shell
 
    unset VERILATOR_ROOT      # if your shell is bash
    unsetenv VERILATOR_ROOT   # if your shell is csh
@@ -272,7 +323,7 @@ The command to configure the package was described in the previous step.
 Developers should configure to have more complete developer tests.
 Additional packages may be required for these tests.
 
-::
+.. code-block:: shell
 
    export VERILATOR_AUTHOR_SITE=1    # Put in your .bashrc
    ./configure --enable-longtests  ...above options...
@@ -283,7 +334,7 @@ Compile
 
 Compile Verilator:
 
-::
+.. code-block:: shell
 
    make -j `nproc`  # Or if error on `nproc`, the number of CPUs in system
 
@@ -293,7 +344,7 @@ Test
 
 Check the compilation by running self-tests:
 
-::
+.. code-block:: shell
 
    make test
 
@@ -305,7 +356,7 @@ If you used any install option other than the `1. Run-in-Place from
 VERILATOR_ROOT <#_1_run_in_place_from_verilator_root>`__ scheme, install
 the files:
 
-::
+.. code-block:: shell
 
    make install
 

docs/guide/languages.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ***************
@@ -6,7 +6,7 @@ Input Languages
 ***************
 
 This section describes the languages Verilator takes as input.  See also
-:ref:`Configuration Files`.
+:ref:`Verilator Control Files`.
 
 
 Language Standard Support
@@ -62,12 +62,23 @@ Verilator supports the 2017 "for" loop constructs and several cleanups IEEE
 made in 1800-2017.
 
 
+SystemVerilog 2023 (IEEE 1800-2023) Support
+-------------------------------------------
+
+Verilator supports some of the 2023 improvements, including triple-quoted
+string blocks that may include newlines and single quotes.
+
+Verilator implements a full IEEE 1800-2023 compliant preprocessor,
+including triple-quoted strings, and \`ifdef expressions.
+
+
 Verilog AMS Support
 -------------------
 
 Verilator implements a very small subset of Verilog AMS (Verilog Analog and
 Mixed-Signal Extensions) with the subset corresponding to those VMS
-keywords with near-equivalents in Verilog 2005 or SystemVerilog 2017.
+keywords with near-equivalents in Verilog IEEE 1364 or SystemVerilog
+IEEE 1800.
 
 AMS parsing is enabled with :vlopt:`--language VAMS <--language>` or
 :vlopt:`--language 1800+VAMS <--language>`.
@@ -79,14 +90,14 @@ wreal.
 Synthesis Directive Assertion Support
 -------------------------------------
 
-With the :vlopt:`--assert` option, Verilator reads any
+Verilator reads any :code:`//synopsys full_case` or :code:`//synopsys
+parallel_case` directives.  The same applies to any :code:`//ambit
+synthesis`, :code:`//cadence` or :code:`//pragma` directives of the same
+form.
 
-:code:`//synopsys full_case` or :code:`//synopsys parallel_case`
+When these synthesis directives are discovered, unless
-directives.  The same applies to any :code:`//ambit synthesis`,
+:vlopt:`--no-assert-case` option is used, Verilator will either formally
-:code:`//cadence` or :code:`//pragma` directives of the same form.
+prove the directive to be true, or, failing that, will insert the
-
-When these synthesis directives are discovered, Verilator will either
-formally prove the directive to be true, or, failing that, will insert the
 appropriate code to detect failing cases at simulation runtime and print an
 "Assertion failed" error message.
 
@@ -157,7 +168,7 @@ files. The :option:`/*verilator&32;timing_off*/` and
 the encompassed timing controls and forks, regardless of the chosen
 :vlopt:`--timing` or :vlopt:`--no-timing` option. This can also be achieved
 using the :option:`timing_off` and :option:`timing_off` options in Verilator
-configuration files.
+Control Files.
 
 
 .. _Language Limitations:
@@ -237,11 +248,9 @@ optimizations will be disabled around the latch.
 Structures and Unions
 ---------------------
 
-Presently Verilator only supports packed structs and packed unions.  Rand
+All structures and unions are scheduled together, which means that
-and randc tags on members are ignored.  All structures and unions are
+generating one member of a structure from blocking, and another from
-represented as a single vector, which means that generating one member of a
+non-blocking assignments is unsupported.
-structure from blocking, and another from non-blocking assignments is
-unsupported.
 
 
 .. _Unknown States:
@@ -320,26 +329,13 @@ there will be considered a two-state variable that is read and written
 instead of a four-state variable.
 
 
-Functions & Tasks
------------------
-
-All functions and tasks will be inlined (will not become functions in C.)
-The only support provided is simple statements in tasks (which may
-affect global variables).
-
-Recursive functions and tasks are not supported.  All inputs and outputs
-are automatic as if they had the Verilog 2001 "automatic" keyword
-prepended.  (If you don't know what this means, Verilator will do what you
-probably expect, what C does. The default behavior of Verilog is
-different.)
-
-
 Gate Primitives
 ---------------
 
 The 2-state gate primitives (and, buf, nand, nor, not, or, xnor, xor) are
 directly converted to behavioral equivalents.  The 3-state and MOS gate
-primitives are not supported.  Tables are not supported.
+primitives are not supported.  User-defined primitive (UDP) tables are
+supported.
 
 
 Specify blocks
@@ -383,24 +379,6 @@ Verilator does not support SEREs yet.  All assertion and coverage
 statements must be simple expressions that complete in one cycle.
 
 
-Force statement
----------------
-
-Verilator supports the procedural `force` (and corresponding `release`)
-statement. However, the behavior of the `force` statement does not entirely
-comply with IEEE 1800. According to the standard,
-when a procedural statement of the form `force a = b;` is executed, the
-simulation should behave as if, from that point forwards, a continuous
-assignment `assign a = b;` has been added to override the drivers of `a`.
-More specifically: the value of `a` should be updated whenever the value of
-`b` changes, until a `release a;` statement is executed.
-Verilator instead evaluates the current value of `b` when the `force`
-statement is executed, and forces `a` to that value, without updating it
-until a new `force` or `release` statement is encountered that applies to
-`a`. This non-standard behavior is nevertheless consistent with some other
-simulators.
-
-
 Encrypted Verilog
 -----------------
 
@@ -419,8 +397,8 @@ This section describes specific limitations for each language keyword.
    \`begin_keywords, \`begin_keywords, \`begin_keywords, \`begin_keywords,
    \`define, \`else, \`elsif, \`end_keywords, \`endif, \`error, \`ifdef,
    \`ifndef, \`include, \`line, \`systemc_ctor, \`systemc_dtor,
-   \`systemc_header, \`systemc_imp_header, \`systemc_implementation,
+   \`systemc_header, \`systemc_header_post, \`systemc_imp_header,
-   \`systemc_interface, \`undef, \`verilog
+   \`systemc_implementation, \`systemc_interface, \`undef, \`verilog
 
 |cmdslong1|
   Fully supported.
@@ -471,6 +449,21 @@ disable
   provide loop break and continue functionality before SystemVerilog added
   the break and continue keywords.
 
+force, release
+  Verilator supports the procedural `force` (and corresponding `release`)
+  statement. However, the behavior of the `force` statement does not
+  entirely comply with IEEE 1800-2023:
+
+  #. Using forced variable as a value to another force statement is
+     currently not supported. The dependent force statement is forced by an
+     initial constant value.
+
+  #. Force/release with procedural continuous assignment is not supported.
+     The assignment is treated as procedural.
+
+  #. Expressions using multiple variable references or function calls on
+     forced right-hand side are not sensitive to dependency changes.
+
 inside
   Inside expressions may not include unpacked array traversal or $ as an
   upper bound.  Case inside and case matches are also unsupported.
@@ -485,7 +478,8 @@ shortreal
   other simulators either do not support float, or convert likewise.
 
 specify specparam
-  All specify blocks and timing checks are ignored.
+  All timing checks and specify blocks (except specparam, which is
+  supported) are ignored.
 
 uwire
   Verilator does not perform warning checking on uwires; it treats the
@@ -496,7 +490,7 @@ $bits, $countbits, $countones, $finish, $isunknown, $onehot, $onehot0, $signed,
 
 $dump/$dumpports and related
   $dumpfile or $dumpports will create a VCD or FST file (based on
-  the :vlopt:`--trace` option given when the model was Verilated). This
+  the :vlopt:`--trace-vcd` option given when the model was Verilated). This
   will take effect starting at the next eval() call.  If you have multiple
   Verilated designs under the same C model, this will dump signals
   only from the design containing the $dumpvars.
@@ -543,4 +537,4 @@ $test$plusargs, $value$plusargs
         {VerilatedContext*} ->commandArgs(argc, argv);
 
   to register the command line before calling $test$plusargs or
-  $value$plusargs.
+  $value$plusargs. Or use :vlopt:`--binary` or :vlopt:`--main`.

docs/guide/overview.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ********
@@ -23,12 +23,12 @@ resulting model's C++ or SystemC code is output as .cpp and .h files. This
 is referred to as "Verilating", and the process is "to Verilate"; the
 output is a "Verilated" model.
 
-2. For simulation, a small-user written C++ wrapper file is required, the
+2. For simulation, a small user-written C++ wrapper file is required, the
 "wrapper".  This wrapper defines the C++ standard function "main()", which
 instantiates the Verilated model as a C++/SystemC object.
 
 3. The user C++ wrapper, the files created by Verilator, a "runtime
-library" provided by Verilator, and, if applicable SystemC libraries are
+library" provided by Verilator, and, if applicable, SystemC libraries are
 then compiled using a C++ compiler to create a simulation executable.
 
 4. The resulting executable will perform the actual simulation during
@@ -44,12 +44,12 @@ The best place to get started is to try the :ref:`Examples`.
 .. [#] Verilog is defined by the `Institute of Electrical and Electronics
        Engineers (IEEE) Standard for Verilog Hardware Description
        Language`, Std. 1364, released in 1995, 2001, and 2005.  The
-       Verilator documentation uses the shorthand, e.g., "IEEE 1394-2005",
+       Verilator documentation uses the shorthand, e.g., "IEEE 1364-2005",
        to refer to the, e.g., 2005 version of this standard.
 
 .. [#] SystemVerilog is defined by the `Institute of Electrical and
        Electronics Engineers (IEEE) Standard for SystemVerilog - Unified
        Hardware Design, Specification, and Verification Language`, Standard
-       1800, released in 2005, 2009, 2012, and 2017.  The Verilator
+       1800, released in 2005, 2009, 2012, 2017, and 2023.  The Verilator
-       documentation uses the shorthand e.g., "IEEE 1800-2017", to refer to
+       documentation uses the shorthand e.g., "IEEE 1800-2023", to refer to
-       the, e.g., 2017 version of this standard.
+       the, e.g., 2023 version of this standard.

docs/guide/simulating.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Simulating:
@@ -12,6 +12,62 @@ Verilated model's executable.  For the runtime arguments to a simulated
 model, see :ref:`Simulation Runtime Arguments`.
 
 
+.. _Simulation Summary Report:
+
+Simulation Summary Report
+=========================
+
+When simulation finishes, it will print a report to stdout summarizing the
+simulation. This requires the model being Verilated with :vlopt:`--main`,
+or the user's `main()` calling `VerilatedContext->statsPrintSummary()`.
+
+The report may be disabled with :vlopt:`+verilator+quiet`.
+
+For example:
+
+.. code-block::
+
+   - S i m u l a t i o n   R e p o r t: Verilator ...
+   - Verilator: End at simtime 123 ns; walltime 1234.001 s; speed 123 ns/s
+   - Verilator: cpu 22.001 s on 4 threads; alloced 123 MB
+
+The information in this report is:
+
+.. describe:: "Verilator ..."
+
+   Program version.
+
+.. describe:: "End at simtime 123 ns"
+
+   Verilog $time at which the model finished or stopped.
+
+.. describe:: "walltime 1234.001 s"
+
+   Real elapsed wall time in seconds.
+
+.. describe:: "speed 123.1 ns/s"
+
+   Simulated time (if non-zero) divided by wall time. e.g. `123 ns/s` means
+   123 simulated nanoseconds took 1 second of wall time; for a model with
+   only a 1 GHz clock that would be equivalent to 123.1 cycles per
+   second. The units are automatically selected to give a number between 1
+   and 1000.  The wall time includes initialization, initial and final
+   process blocks, so indicates a slower speed than if the model had a
+   longer runtime.
+
+.. describe:: "cpu 22 s"
+
+   CPU time used total across all CPU threads in seconds.
+
+.. describe:: "4 threads"
+
+   Number of simultaneous threads used.
+
+.. describe:: "alloced 123 MB"
+
+   Total memory used during simulation in megabytes.
+
+
 .. _Benchmarking & Optimization:
 
 Benchmarking & Optimization
@@ -20,16 +76,19 @@ Benchmarking & Optimization
 For best performance, run Verilator with the :vlopt:`-O3`
 :vlopt:`--x-assign fast <--x-assign>`
 :vlopt:`--x-initial fast <--x-initial>`
-:vlopt:`--noassert <--assert>` options.  The :vlopt:`-O3`
+:vlopt:`--no-assert` options.  The :vlopt:`-O3`
 option will require a longer time to run Verilator, and
 :vlopt:`--x-assign fast <--x-assign>`
 :vlopt:`--x-initial fast <--x-assign>`
-may increase the risk of reset bugs in trade for performance; see the above
+may increase the risk of reset bugs in trade for performance.  The
-documentation for these options.
+:vlopt:`--no-assert` will suppress checking assertions, which is faster and
+appropriate for known-good models running software, but may hide design
+errors.  See the above documentation for these options.
 
-If using Verilated multithreaded, use ``numactl`` to ensure you use
+If using Verilated multithreaded, consider overriding Verilator's default
-non-conflicting hardware resources. See :ref:`Multithreading`. Also,
+thread-to-processor assignment by using ``numactl``; see
-consider using profile-guided optimization; see :ref:`Thread PGO`.
+:ref:`Multithreading`. Also, consider using profile-guided optimization;
+see :ref:`Thread PGO`.
 
 Minor Verilog code changes can also give big wins.  You should not have any
 :option:`UNOPTFLAT` warnings from Verilator.  Fixing these warnings can
@@ -146,9 +205,6 @@ With :vlopt:`--coverage` or :vlopt:`--coverage-user`, Verilator will
 translate functional coverage points the user has inserted manually in
 SystemVerilog code through into the Verilated model.
 
-Currently, all functional coverage points are specified using SystemVerilog
-assertion syntax, which must be separately enabled with :vlopt:`--assert`.
-
 For example, the following SystemVerilog statement will add a coverage
 point under the coverage name "DefaultClock":
 
@@ -168,14 +224,6 @@ at branches).  At each such branch, a counter is incremented.  At the end
 of a test, the counters, filename, and line number corresponding to each
 counter are written into the coverage file.
 
-Verilator automatically disables coverage of branches with a $stop in
-them, as it is assumed that $stop branches contain an error check that should
-not occur.  A :option:`/*verilator&32;coverage_block_off*/` metacomment
-will perform a similar function on any code in that block or below, or
-:option:`/*verilator&32;coverage_off*/` and
-:option:`/*verilator&32;coverage_on*/` will disable and enable coverage
-respectively around a block of code.
-
 Verilator may over-count combinatorial (non-clocked) blocks when those
 blocks receive signals which have had the :option:`UNOPTFLAT` warning
 disabled; for the most accurate results, do not disable this warning when
@@ -222,6 +270,58 @@ A :option:`/*verilator&32;coverage_off*/`
 signals that do not need toggle analysis, such as RAMs and register files.
 
 
+.. _Expression Coverage:
+
+Expression Coverage
+-------------------
+
+With :vlopt:`--coverage` or :vlopt:`--coverage-expr`, Verilator will
+automatically add coverage analysis at each expression, indicating with a
+truth table how every Boolean truth-table possibility in the expression
+occurred.
+
+Multi-bit expressions are ignored, but sub-expressions with are entirely
+Boolean are analyzed.  Expression coverage does not fully explore the truth
+table of an expression, rather is looks at each term's contribution.  E.g.
+an AND operation will check coverage for TT, XF and FX.
+
+Some expressions may produce too many cover points.  Verilator limits the
+maximum number of cover points per expression to 32, but this may be
+controlled with :vlopt:`--coverage-expr-max`.
+
+Below is an example showing expression coverage produced from `verilator_coverage`
+as applied to the condition expression inside an if statement.  Each line
+shows the minimum number of terms and their values (e.g. `(t1==0 && t2==1)`) needed
+to reach a result for the overall expression (e.g. `=> 1`).  Each line also
+shows the number of times this combination was hit.  Note that individual lines
+are not mutually exclusive.
+
+.. code-block::
+
+   %000004         if ((~t1 && t2) || (~t3 && t4)) $write("");
+   -000002  point: comment=(t1==0 && t2==1) => 1 hier=top.t
+   -000002  point: comment=(t1==1 && t3==1) => 0 hier=top.t
+   -000004  point: comment=(t1==1 && t4==0) => 0 hier=top.t
+   -000002  point: comment=(t2==0 && t3==1) => 0 hier=top.t
+   -000003  point: comment=(t2==0 && t4==0) => 0 hier=top.t
+   -000002  point: comment=(t3==0 && t4==1) => 1 hier=top.t
+
+.. _Suppressing Coverage:
+
+Suppressing Coverage
+--------------------
+
+Using :option:`/*verilator&32;coverage_off*/` and
+:option:`/*verilator&32;coverage_on*/` around a block of code will disable
+and enable coverage respectively around that block. Or, use the
+:option:`coverage_block_off` control file option.
+
+Verilator automatically disables coverage of lines and branches with a
+$stop in them, as it is assumed that $stop branches contain an error check
+that should not occur.  A :option:`/*verilator&32;coverage_block_off*/`
+metacomment will perform a similar function on any code in that block or
+below.
+
 .. _Coverage Collection:
 
 Coverage Collection
@@ -230,14 +330,20 @@ Coverage Collection
 When any coverage flag is used to Verilate, Verilator will add appropriate
 coverage point insertions into the model and collect the coverage data.
 
-To get the coverage data from the model, in the user wrapper code,
+To get the coverage data from the model, write the coverage with either:
-typically at the end once a test passes, call
+
-:code:`Verilated::threadContextp()->coveragep()->write` with an argument of the filename for
+1. Using :vlopt:`--binary` or :vlopt:`--main`, and Verilator will dump
-the coverage data file to write coverage data to (typically
+   coverage when the test completes to the filename specified with
-"logs/coverage.dat").
+   :vlopt:`+verilator+coverage+file+\<filename\>`.
+
+2. In the user wrapper code, typically at the end once a test passes, call
+   :code:`Verilated::threadContextp()->coveragep()->write` with an argument
+   of the filename for the coverage data file to write coverage data to
+   (typically "logs/coverage.dat").
 
 Run each of your tests in different directories, potentially in parallel.
-Each test will create a :file:`logs/coverage.dat` file.
+Each test will create the file specified above,
+e.g. :file:`logs/coverage.dat`.
 
 After running all of the tests, execute the :command:`verilator_coverage`
 command, passing arguments pointing to the filenames of all the
@@ -273,13 +379,17 @@ profiled C++ code functions.
 
 To use profiling:
 
-#. Use Verilator's :vlopt:`--prof-cfuncs`.
+#. Make sure the Verilog code will call `$finish` at the end of simulation
+   (otherwise the C library may not correctly create the `gmon.out` file in
+   the later steps below).
+#. Run Verilator, adding the :vlopt:`--prof-cfuncs` option.
 #. Build and run the simulation model.
-#. The model will create gmon.out.
+#. The model will create `gmon.out`.
-#. Run :command:`gprof` to see where in the C++ code the time is spent.
+#. Run :command:`gprof gmon.out > gprof.log` to see where in the C++ code
-#. Run the gprof output through the :command:`verilator_profcfunc` program,
+   the time is spent.
-   and it will tell you what Verilog line numbers on which most of the time
+#. Run :command:`verilator_profcfunc gprof.log > profcfunc.log` to take the
-   is being spent.
+   gprof output and translate into output showing the Verilog line numbers
+   on which most of the time is being spent.
 
 
 .. _Execution Profiling:
@@ -505,13 +615,30 @@ documentation.
 Runtime Debugging
 =================
 
-To debug a Verilated executable, use the standard GNU debugger ``gdb`` or a
+To debug a Verilated executable, Verilate with :vlopt:`--runtime-debug`.
-similar tool. Typically you will want to have debugger symbols inserted by
+This will instruct the compiler to insert debugger, and enable various
-the compiler, assertions enabled in the C library, and assertions enabled
+library assertions. These options slow down the executable, so do this
-in the Verilated library. (These options slow down the executable, so do
+only when debugging.
-this only when debugging.) To enable this, Verilate with:
 
-    -CFLAGS -ggdb  -LDFLAGS -ggdb  -CFLAGS -DVL_DEBUG=1  -CFLAGS -D_GLIBCXX_DEBUG
+If you are using your own Makefiles, adapt appropriately to pass the
+options documented under :vlopt:`--runtime-debug` to the compiler and
+linker.
 
-The :vlopt:`-CFLAGS` and/or :vlopt:`-LDFLAGS` options pass arguments
+Once you have a debugging-enabled executable, run it using the the standard
-directly to the compiler or linker.
+GNU debugger ``gdb`` or a similar tool, and create a backtrace; e.g.:
+
+   .. code-block:: bash
+
+      gdb obj_dir/Vtop
+        run {Vtop_command_arguments}
+        {Vtop prints output, perhaps a segmentation faults}
+        bt
+
+Rarely the bug may disappear with :vlopt:`--runtime-debug`; if so, try
+instead using the sub-options that :vlopt:`--runtime-debug` documents, to
+find the maximum subset that still shows the issue.  E.g. it is likely that
+using `-CFLAGS -D_GLIBCXX_DEBUG` will not hide any bug, so may be used.
+
+Using :vlopt:`--runtime-debug` or `-CFLAGS -DVL_DEBUG=1` will only print a
+message if something goes wrong.  To enable debug print messages at
+runtime, additionally use the :vlopt:`+verilator+debug` runtime option.

docs/guide/verilating.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 **********
@@ -7,9 +7,13 @@ Verilating
 
 Verilator may be used in five major ways:
 
+* With the :vlopt:`--binary` option, Verilator will translate the design
+  into an executable, via generating C++ and compiling it.  See
+  :ref:`Binary, C++ and SystemC Generation`.
+
 * With the :vlopt:`--cc` or :vlopt:`--sc` options, Verilator will translate
-  the design into C++ or SystemC code, respectively.  See :ref:`C++ and
+  the design into C++ or SystemC code, respectively.  See :ref:`Binary, C++
-  SystemC Generation`.
+  and SystemC Generation`.
 
 * With the :vlopt:`--lint-only` option, Verilator will lint the design to
   check for warnings but will not typically create any output files.
@@ -24,13 +28,15 @@ Verilator may be used in five major ways:
   expanded.
 
 
-.. _C++ and SystemC Generation:
+.. _Binary, C++ and SystemC Generation:
 
-C++ and SystemC Generation
+Binary, C++ and SystemC Generation
-==========================
+==================================
 
 Verilator will translate a SystemVerilog design into C++ with the
-:vlopt:`--cc` option, or into SystemC with the :vlopt:`--sc` option.
+:vlopt:`--cc` option, or into SystemC with the :vlopt:`--sc` option.  It
+will translate into C++ and compile it into an executable binary with the
+:vlopt:`--binary` option.
 
 When using these options:
 
@@ -45,14 +51,53 @@ When using these options:
    The prefix is set with :vlopt:`--prefix`, or defaults to the name of the
    top module.
 
-#. If :vlopt:`--exe` is used, Verilator creates makefiles to generate a
+#. If :vlopt:`--binary` or :vlopt:`--main` is used, Verilator creates a C++
-   simulation executable, otherwise, it creates makefiles to generate an
+   top wrapper to read command line arguments, create the model, and
-   archive (.a) containing the objects.
+   execute the model.
 
-#. If :vlopt:`--build` option was used, it calls :ref:`GNU Make` or
+#. If :vlopt:`--binary` or :vlopt:`--exe` is used, Verilator creates
-   :ref:`CMake` to build the model.
+   makefiles to generate a simulation executable, otherwise, it creates
+   makefiles to generate an archive (.a) containing the objects.
 
-Once a model is built, it is then typically run, see :ref:`Simulating`.
+#. If :vlopt:`--binary` or :vlopt:`--build` is used, it calls :ref:`GNU
+   Make` or :ref:`CMake` to build the model.
+
+Once a model is built, the next step is typically for the user to run it,
+see :ref:`Simulating`.
+
+
+.. _Finding and Binding Modules:
+
+Finding and Binding Modules
+===========================
+
+Verilator provides several mechanisms to find the source code containing a
+module, primitive, interface, or program ("module" in this section) and
+bind them to an instantiation.  These capabilities are similar to the
+"Precompiling in a single-pass" use model described in IEEE 1800-2023
+33.5.1, although `config` is not yet supported.
+
+Verilator first reads all files provided on the command line and
+:vlopt:`-f` files, and parses all modules within.  Each module is assigned
+to the most recent library specified with :vlopt:`-work`, thus `-work liba
+a.v -work libb b.v` will assign modules in `a.v` to `liba` and modules in
+`b.v` to `libb`.
+
+If a module is not defined from a file on the command-line, Verilator
+attempts to find a filename constructed from the module name using
+:vlopt:`-y` and `+libext`.
+
+Binding begins with the :vlopt:`--top` module, if provided. If not provided
+Verilator attempts to figure out the top module itself, and if multiple
+tops result a :option:`MULTITOP` warning is issued which may be suppressed
+(see details in :option:`MULTITOP`).
+
+Verilator will attempt to bind lower unresolved instances first in the same
+library name as the parent's instantiation library, and if not found search
+globally across all libraries in the order modules were declared.  This
+allows otherwise conflicting duplicate module names between libraries to
+coexist uniquely within each library name.  When IEEE `config use` is
+supported, more complicated selections will be able to be specified.
 
 
 .. _Hierarchical Verilation:
@@ -83,7 +128,7 @@ There are two ways to mark a module:
 
 * Write :option:`/*verilator&32;hier_block*/` metacomment in HDL code.
 
-* Add a :option:`hier_block` line in the :ref:`Configuration Files`.
+* Add a :option:`hier_block` line in the :ref:`Verilator Control Files`.
 
 Then pass the :vlopt:`--hierarchical` option to Verilator.
 
@@ -102,8 +147,6 @@ Hierarchy blocks have some limitations, including:
 * The hierarchy block cannot be accessed using dot (.) from the upper
   module(s) or other hierarchy blocks.
 
-* Signals in the block cannot be traced.
-
 * Modport cannot be used at the hierarchical block boundary.
 
 * The simulation speed is likely not as fast as flat Verilation, in which
@@ -210,7 +253,7 @@ model, it may be beneficial to performance to adjust the
 influences the partitioning of the model by adjusting the assumed execution
 time of DPI imports.
 
-When using :vlopt:`--trace` to perform VCD tracing, the VCD trace
+When using :vlopt:`--trace-vcd` to perform VCD tracing, the VCD trace
 construction is parallelized using the same number of threads as specified
 with :vlopt:`--threads`, and is executed on the same thread pool as the model.
 
@@ -232,11 +275,14 @@ trace. FST tracing can utilize up to 2 offload threads, so there is no use
 of setting :vlopt:`--trace-threads` higher than 2 at the moment.
 
 When running a multithreaded model, the default Linux task scheduler often
-works against the model by assuming short-lived threads and thus
+works against the model by assuming short-lived threads and thus it often
-it often schedules threads using multiple hyperthreads within the same
+schedules threads using multiple hyperthreads within the same physical
-physical core. For best performance, use the :command:`numactl` program to
+core. If there is no affinity already set, on Linux only, Verilator
-(when the threading count fits) select unique physical cores on the same
+attempts to set thread-to-processor affinity in a reasonable way.
-socket. The same applies for :vlopt:`--trace-threads` as well.
+
+For best performance, use the :command:`numactl` program to (when the
+threading count fits) select unique physical cores on the same socket. The
+same applies for :vlopt:`--trace-threads` as well.
 
 As an example, if a model was Verilated with
 :vlopt:`--threads 4 <--threads>`, we consult:
@@ -279,8 +325,8 @@ and must be called only by the eval thread.
 If using :vlopt:`--sc`, the SystemC kernel is not thread-safe; therefore,
 the eval thread and main thread must be the same.
 
-If using :vlopt:`--trace`, the tracing classes must be constructed and
+If using :vlopt:`--trace-vcd` or other trace options, the tracing classes
-called from the main thread.
+must be constructed and called from the main thread.
 
 If using :vlopt:`--vpi`, since SystemVerilog VPI was not architected by
 IEEE to be multithreaded, Verilator requires all VPI calls are only made
@@ -293,9 +339,9 @@ GNU Make
 ========
 
 Verilator defaults to creating GNU Make makefiles for the model.  Verilator
-will call make automatically when the :vlopt:'--build' option is used.
+will call make automatically when the :vlopt:`--build` option is used.
 
-If calling Verilator from a makefile, the :vlopt:'-MMD' option will create
+If calling Verilator from a makefile, the :vlopt:`--MMD` option will create
 a dependency file, allowing Make to only run Verilator if input Verilog
 files change.
 
@@ -356,10 +402,11 @@ Verilate in CMake
 .. code-block:: CMake
 
      verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name]
-              [TRACE] [TRACE_FST] [SYSTEMC] [COVERAGE]
+              [COVERAGE] [SYSTEMC]
+              [TRACE_FST] [TRACE_SAIF] [TRACE_VCD] [TRACE_THREADS num]
               [INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...]
               [OPT_GLOBAL ..] [DIRECTORY dir] [THREADS num]
-              [TRACE_THREADS num] [VERILATOR_ARGS ...])
+              [VERILATOR_ARGS ...])
 
 Lowercase and ... should be replaced with arguments; the uppercase parts
 delimit the arguments and can be passed in any order or left out entirely
@@ -432,10 +479,6 @@ SystemC include directories and link to the SystemC libraries.
 
    Optional. Enable a multithreaded model; see :vlopt:`--threads`.
 
-.. describe:: TRACE_THREADS
-
-   Optional. Enable multithreaded FST trace; see :vlopt:`--trace-threads`.
-
 .. describe:: TOP_MODULE
 
    Optional. Sets the name of the top module. Defaults to the name of the
@@ -443,14 +486,27 @@ SystemC include directories and link to the SystemC libraries.
 
 .. describe:: TRACE
 
-   Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS
+   Deprecated. Same as TRACE_VCD, which should be used instead.
-   --trace".
 
 .. describe:: TRACE_FST
 
    Optional. Enables FST tracing if present, equivalent to "VERILATOR_ARGS
    --trace-fst".
 
+.. describe:: TRACE_SAIF
+
+   Optional. Enables SAIF tracing if present, equivalent to "VERILATOR_ARGS
+   --trace-saif".
+
+.. describe:: TRACE_THREADS
+
+   Optional. Enable multithreaded FST trace; see :vlopt:`--trace-threads`.
+
+.. describe:: TRACE_VCD
+
+   Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS
+   --trace-vcd".
+
 .. describe:: VERILATOR_ARGS
 
    Optional. Extra arguments to Verilator. Do not specify :vlopt:`--Mdir`
@@ -487,3 +543,78 @@ The search paths can be configured by setting some variables:
 
    Sets the installation prefix of an installed SystemC library. (Same as
    SYSTEMC_ROOT).
+
+
+.. _Verilation Summary Report:
+
+Verilation Summary Report
+=========================
+
+When Verilator generates code, unless :vlopt:`--quiet-stats` is used, it
+will print a report to stdout summarizing the build. For example:
+
+.. code-block::
+
+    - V e r i l a t i o n   R e p o r t: Verilator ....
+    - Verilator: Built from 354 MB sources in 247 modules,
+        into 74 MB in 89 C++ files needing 0.192 MB
+    - Verilator: Walltime 26.580 s (elab=2.096, cvt=18.268,
+        bld=2.100); cpu 26.548 s on 1 threads; alloced 2894.672 MB
+
+The information in this report is:
+
+.. describe:: "Verilator ..."
+
+   Program version.
+
+.. describe:: "234 MB sources"
+
+   Characters of post-preprocessed text in all input
+   Verilog and Verilator Control files in megabytes.
+
+.. describe:: "247 modules"
+
+   Number of interfaces/modules/classes/packages in design before
+   elaboration.
+
+.. describe:: "into 74 MB"
+
+   Characters of output C++ code, including comments in megabytes.
+
+.. describe:: "89 C++ files"
+
+   Number of .cpp files created.
+
+.. describe:: "needing 192MB"
+
+   Verilation-time minimum-bound estimate of memory needed to run model in
+   megabytes. (Expect to need significantly more.)
+
+.. describe:: "Walltime 26.580 s"
+
+   Real elapsed wall time for Verilation and build.
+
+.. describe:: "elab=2.096"
+
+   Wall time to read in files and complete elaboration.
+
+.. describe:: "cvt=18.268"
+
+   Wall time for Verilator to process and write output.
+
+.. describe:: "bld=2.1"
+
+   Wall time to compile gcc/clang (if using :vlopt:`--build`).
+
+.. describe:: "cpu 22.548 s"
+
+   CPU time used, total across all CPU threads.
+
+.. describe:: "4 threads"
+
+   Number of simultaneous threads used.
+
+.. describe:: "alloced 123 MB"
+
+   Total memory used during build by Verilator executable (excludes
+   :vlopt:`--build` compiler's usage) in megabytes.

docs/guide/warnings.rst

@@ -1,9 +1,9 @@
-.. Copyright 2003-2023 by Wilson Snyder.
+.. Copyright 2003-2025 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-*******************
+=====================
-Errors and Warnings
+ Errors and Warnings
-*******************
+=====================
 
 .. _Disabling Warnings:
 
@@ -12,10 +12,18 @@ Disabling Warnings
 
 Warnings may be disabled in multiple ways:
 
-#. Disable the warning in the source code.  When the warning is printed, it
+#. Disable the warning globally by invoking Verilator with the
-   will include a warning code.  Surround the offending line with a
+   :code:`-Wno-{warning-code}` option.
-   :code:`/*verilator&32;lint_off*/` and :code:`/*verilator&32;lint_on*/`
+
-   metacomment pair:
+   Global disables should be avoided, as they removes all checking across
+   the source files, and prevents other users from compiling the sources
+   without knowing the magic set of disables needed to compile those
+   sources successfully.
+
+#. Disable the warning in the design source code.  When the warning is
+   printed, it will include a warning code.  Surround the offending line
+   with a :code:`/*verilator&32;lint_off*/` and
+   :code:`/*verilator&32;lint_on*/` metacomment pair:
 
    .. code-block:: sv
 
@@ -23,20 +31,20 @@ Warnings may be disabled in multiple ways:
          if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop;
          // verilator lint_on UNSIGNED
 
-#. Disable the warning using :ref:`Configuration Files` with a
+
+   A lint_off in the design source code will propagate down to any child
+   files (files later included by the file with the lint_off), but will not
+   propagate upwards to any parent file (file that included the file with
+   the lint_off).
+
+#. Disable the warning using :ref:`Verilator Control Files` with a
    :option:`lint_off` command.  This is useful when a script suppresses
    warnings, and the Verilog source should not be changed.  This method also
    allows matching on the warning text.
 
    .. code-block:: sv
 
-         lint_off -rule UNSIGNED -file "*/example.v" -line 1
+         lint_off -rule UNSIGNED -file "*/example.v" -lines 1
-
-#. Disable the warning globally invoking Verilator with the
-   :code:`-Wno-{warning-code}` option.  This should be avoided, as it
-   removes all checking across the designs, and prevents other users from
-   compiling your code without knowing the magic set of disables needed to
-   compile your design successfully.
 
 
 Error And Warning Format
@@ -60,6 +68,10 @@ source code corresponding to the error, prefixed by the line number and a "
 | ".  Following this is typically an arrow and ~ pointing at the error on
 the source line directly above.
 
+Instead of parsing this text diagnostic output, tools that need to
+understand Verilator's warning output should read the SARIF JSON output
+created with :vlopt:`--diagnostics-sarif`.
+
 
 List Of Warnings
 ================
@@ -78,6 +90,8 @@ List Of Warnings
    Limitations`.
 
 
+   .. t_dist_docs_style restart_sort
+
 .. option:: ALWCOMBORDER
 
    .. TODO better example
@@ -97,6 +111,27 @@ List Of Warnings
    simulate correctly.
 
 
+.. option:: ALWNEVER
+
+   Warning that an `always @*` statement has no variables being read,
+   therefore the event list is empty, and as there are no events to wake
+   the process up, the always will never execute.
+
+   Faulty example:
+
+   .. include:: ../../docs/gen/ex_ALWNEVER_faulty.rst
+
+   Results in:
+
+   .. include:: ../../docs/gen/ex_ALWNEVER_msg.rst
+
+   To repair, assuming the intent was to execute the statements at e.g.
+   time zero, instead use an `always_comb` statement.
+
+   Ignoring this warning will only suppress the lint check; it will
+   simulate correctly.
+
+
 .. option:: ASCRANGE
 
    .. TODO better example
@@ -153,10 +188,32 @@ List Of Warnings
 .. option:: BADSTDPRAGMA
 
    An error that a pragma is badly formed, for pragmas defined by IEEE
-   1800-2017.  For example, an empty pragma line, or an incorrectly used
+   1800-2023.  For example, an empty pragma line, or an incorrectly used
-   'pragma protect'.  Third-party pragmas not defined by IEEE 1800-2017 are
+   'pragma protect'.  Third-party pragmas not defined by IEEE 1800-2023 are
    ignored.
 
+   This error may be disabled with a lint_off BADSTDPRAGMA metacomment.
+
+   Ignoring this warning will cause the pragma to be ignored.
+
+
+.. option:: BADVLTPRAGMA
+
+   An error that a `/*verilator ...*/` metacomment pragma is badly formed
+   or not understood.
+
+   Faulty example:
+
+   .. include:: ../../docs/gen/ex_BADVLTPRAGMA_faulty.rst
+
+   Results in:
+
+   .. include:: ../../docs/gen/ex_BADVLTPRAGMA_msg.rst
+
+   This error may be disabled with a lint_off BADVLTPRAGMA metacomment.
+
+   Ignoring this warning will cause the pragma to be ignored.
+
 
 .. option:: BLKANDNBLK
 
@@ -175,23 +232,32 @@ List Of Warnings
    public task, or when the blocking and non-blocking assignments have
    non-overlapping bits and structure members.
 
+   From Verilator 5.038, this warning is only issued when Verilator can't prove that
+   the assignments are to non-overlapping sub-parts, and the blocking
+   assignment is in combinational logic (which is the case where simulation
+   results might differ from other simulators). Review any BLKANDNBLK
+   cases carefully after this version, and sign them off as
+   described above, only if know for sure the updates are not to overlapping
+   parts of the signal.
+
    Generally, this is caused by a register driven by both combo logic and a
    flop:
 
    .. code-block:: sv
 
-         logic [1:0] foo;
+         logic [3:0] foo;
-         always @(posedge clk)  foo[0] <= ...
+         always @(posedge clk) foo[index] <= ...  // With index != 0
-         always_comb foo[1] = ...
+         always_comb foo[0] = ...
 
    Instead, use a different register for the flop:
 
    .. code-block:: sv
 
-         logic [1:0] foo;
+         logic [3:0] foo;
-         always @(posedge clk)  foo_flopped[0] <= ...
+         logic [3:1] foo_flopped;
-         always_comb foo[0] = foo_flopped[0];
+         always @(posedge clk) foo_flopped[index] <= ... // With index != 0
-         always_comb foo[1] = ...
+         always_comb foo[0] = ...
+         always_comb foo[3:1] = foo_flopped;
 
    Or, this may also avoid the error:
 
@@ -202,22 +268,35 @@ List Of Warnings
 
 .. option:: BLKLOOPINIT
 
-   .. TODO better example
+   Indicates certain constructs where non-blocking assignments to unpacked
-
+   arrays (memories) are not supported inside loops. These typically appear in
-   This indicates that the initialization of an array needs to use
+   initialization/reset code:
-   non-delayed assignments.  This is done in the interest of speed; if
-   delayed assignments were used, the simulator would have to copy large
-   arrays every cycle.  (In smaller loops, loop unrolling allows the
-   delayed assignment to work, though it's a bit slower than a non-delayed
-   assignment.)  Here's an example
 
    .. code-block:: sv
 
          always @(posedge clk)
             if (~reset_l)
                 for (i=0; i<`ARRAY_SIZE; i++)
-                    array[i] = 0;  // Non-delayed for verilator
+                    array[i] <= 0;  // Non-blocking assignment inside loop
+            else
+                array[address] <= data;
 
+   While this is supported in typical synthesizeable code (including the
+   example above), some complicated cases are not supported. Namely:
+
+   1. If the above loop is inside a suspendable process or fork statement.
+
+   2. If the variable is also the target of a '<=' non-blocking assignment
+   in a suspendable process or fork statement (in addition to a synthesizable
+   loop).
+
+   3. If the element type of the array is a compound type.
+
+   4. In versions before 5.026, any delayed assignment to an array.
+
+   It might slightly improve run-time performance if you change the
+   non-blocking assignment inside the loop into a blocking assignment
+   (that is: use '=' instead of '<='), if possible.
 
    This message is only seen on large or complicated loops because
    Verilator generally unrolls small loops.  You may want to try increasing
@@ -275,8 +354,8 @@ List Of Warnings
    Unique case statements that select on an enumerated variable, where all
    of the enumerated values are covered by case items, are considered
    complete even if the case statement does not cover illegal
-   non-enumerated values (IEEE 1800-2017 12.5.3).  To check that illegal
+   non-enumerated values (IEEE 1800-2023 12.5.3).  Verilator checks that
-   values are not hit, use :vlopt:`--assert`.
+   illegal values are not hit, unless :vlopt:`--no-assert-case` was used.
 
    Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
@@ -314,8 +393,8 @@ List Of Warnings
 
    Warns that it is better style to use casez, and "?" in place of
    "x"'s.  See
-   `http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf
+   `http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf
-   <http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf>`_
+   <http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf>`_
 
    Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
@@ -389,8 +468,8 @@ List Of Warnings
    is suppressed, Verilator, like synthesis, will convert this to a
    non-delayed assignment, which may result in logic races or other
    nasties.  See
-   `http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf
+   `http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf
-   <http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf>`_
+   <http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf>`_
 
    Ignoring this warning may make Verilator simulations differ from other
    simulators.
@@ -398,9 +477,9 @@ List Of Warnings
 
 .. option:: CONSTRAINTIGN
 
-   Warns that Verilator does not support :code:`constraint`,
+   Warns that Verilator does not support certain forms of
-   :code:`constraint_mode`, or :code:`rand_mode`, and the construct was are
+   :code:`constraint`, :code:`constraint_mode`, or :code:`rand_mode`, and
-   ignored.
+   the construct was ignored.
 
    Ignoring this warning may make Verilator randomize() simulations differ
    from other simulators.
@@ -424,6 +503,18 @@ List Of Warnings
    correctly.
 
 
+.. option:: COVERIGN
+
+   Warns that Verilator does not support certain forms of
+   :code:`covergroup`, :code:`coverpoint`, and coverage options, and the
+   construct was ignored.
+
+   Disabling the :option:`UNSUPPORTED` error also disables this warning.
+
+   Ignoring this warning may make Verilator ignore lint checking on the
+   construct, and collect coverage data differently from other simulators.
+
+
 .. option:: DECLFILENAME
 
    .. TODO better example
@@ -439,6 +530,32 @@ List Of Warnings
    correctly.
 
 
+.. option:: DEFOVERRIDE
+
+   Warns that a macro definition within the code is being overridden by a
+   command line directive:
+
+   For example, running Verilator with :code:`<+define+\<DUP\>=\<def2\>>` and
+
+   .. code-block:: sv
+      :linenos:
+      :emphasize-lines: 1
+
+         `define DUP def2 //<--- Warning
+
+   Results in:
+
+   .. code-block::
+
+         %Warning-DEFOVERRIDE: example.v1:20: Overriding define: 'DEF' with value: 'def2' to existing command line define value: 'def1'
+                      ... Location of previous definition, with value: '50'
+
+   While not explicitly stated in the IEEE 1800-2023 standard, this warning
+   tracks with the other simulators' behavior of overriding macro
+   definitions within code files with the definition passed in through
+   the command line.
+
+
 .. option:: DEFPARAM
 
    Warns that the :code:`defparam` statement was deprecated in IEEE 1364-2001,
@@ -471,7 +588,7 @@ List Of Warnings
 
    .. code-block::
 
-         %Warning-DEFPARAM: example.v:5:15: defparam is deprecated (IEEE 1800-2017 C.4.1)
+         %Warning-DEFPARAM: example.v:5:15: defparam is deprecated (IEEE 1800-2023 C.4.1)
                                           : ... Suggest use instantiation with #(.MY_PARAM(...etc...))
 
    To repair use :code:`#(.PARAMETER(...))` syntax. Repaired Example:
@@ -613,6 +730,28 @@ List Of Warnings
    missing."
 
 
+.. option:: ENUMITEMWIDTH
+
+   An error that an enum item value is being assigned from a value which
+   would be truncated (similar to :option:`WIDTHTRUNC`), or from a sized
+   literal constant with a different bit width (similar to
+   :option:`WIDTHTRUNC` or :option:`WIDTHEXPAND`).  IEEE requires this
+   error, but it may be disabled.
+
+   Faulty example:
+
+   .. code-block:: sv
+      :linenos:
+      :emphasize-lines: 2
+
+         typedef enum [3:0] {
+            WRONG_WIDTH = 33'h3  //<--- Warning
+         } enum_t;
+
+   To repair, correct the size of the item's value directly, or use a cast,
+   so the resulting width matches the enum's width.
+
+
 .. option:: ENUMVALUE
 
    An error that an enum data type value is being assigned from another data
@@ -699,7 +838,7 @@ List Of Warnings
 
    .. code-block::
 
-         %Warning-GENUNNAMED: example.v:2:9: Unnamed generate block (IEEE 1800-2017 27.6)
+         %Warning-GENUNNAMED: example.v:2:9: Unnamed generate block (IEEE 1800-2023 27.6)
 
    To fix this assign a label (often with the naming convention prefix of
    :code:`gen_` or :code:`g_`), for example:
@@ -755,7 +894,7 @@ List Of Warnings
 
    .. code-block::
 
-         %Warning-IGNOREDRETURN: example.v:5:9: Ignoring return value of non-void function (IEEE 1800-2017 13.4.1)
+         %Warning-IGNOREDRETURN: example.v:5:9: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1)
 
    The portable way to suppress this warning (in SystemVerilog) is to use a
    void cast, for example:
@@ -1021,8 +1160,6 @@ List Of Warnings
 
 .. option:: LITENDIAN
 
-   .. TODO better example
-
    The naming of this warning is in contradiction with the common
    interpretation of little endian. It was therefore renamed to
    :option:`ASCRANGE`. While :option:`LITENDIAN` remains for
@@ -1098,6 +1235,19 @@ List Of Warnings
    discarded.
 
 
+.. option:: MODMISSING
+
+   .. TODO better example
+
+   Error that a module, typically referenced by a cell, was not found.
+   This is typically fatal, but may be suppressed in some linting
+   situations with missing libraries.
+
+   Ignoring this error will cause the cell definition to be discarded.
+   Simulation results will likely be wrong, so typically used only with
+   lint-only.
+
+
 .. option:: MULTIDRIVEN
 
    Warns that the specified signal comes from multiple :code:`always`
@@ -1154,6 +1304,8 @@ List Of Warnings
    modules' signals seem identical, e.g., multiple modules with a "clk"
    input.
 
+   Ignoring this warning will make multiple tops, as described in (3) above.
+
 
 .. option:: NEEDTIMINGOPT
 
@@ -1166,7 +1318,7 @@ List Of Warnings
 
    Warns that a feature requires a newer standard of Verilog or SystemVerilog
    than the one specified by the :vlopt:`--language` option. For example, unsized
-   unbased literals (`'0`, `'1`, `'z`, `'x`) require 1800-2005 or later.
+   unbased literals (`'0`, `'1`, `'z`, `'x`) require IEEE 1800-2005 or later.
 
    To avoid this warning, use a Verilog or SystemVerilog standard that
    supports the feature. Alternatively, modify your code to use a different
@@ -1177,6 +1329,21 @@ List Of Warnings
    simulate correctly.
 
 
+.. option:: NOEFFECT
+
+   Warns that the statement will have no effect and is roughly equivalent
+   to not being present.  This is only issued when it is "non-obvious",
+   e.g. a :code:`if (0)` will not result in this warning.
+
+   Faulty example:
+
+   .. code-block:: sv
+
+         foreach (array[]) begin ... end  //<--- Warning
+
+   For a fix, remove the statement.
+
+
 .. option:: NOLATCH
 
    .. TODO better example
@@ -1189,6 +1356,17 @@ List Of Warnings
    simulate correctly.
 
 
+.. option:: NONSTD
+
+   Warns when a non-standard language feature is used that has a standard
+   equivalent, which might behave differently in corner cases. For example
+   :code:`$psprintf` system function is replaced by its standard equivalent
+   :code:`$sformatf`.
+
+   Ignoring this warning will only suppress the lint check; it will
+   simulate correctly.
+
+
 .. option:: NOTIMING
 
    Error when a timing-related construct that requires :vlopt:`--timing` has
@@ -1220,6 +1398,28 @@ List Of Warnings
    Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
+
+.. option:: PARAMNODEFAULT
+
+   An error that a parameter is being declared that has no default value,
+   and this is being done in a non-ANSI block while this is only legal in
+   ANSI-style `#(...)` declarations.  IEEE 1800-2023 6.20.1 requires this
+   error, but some simulators accept this syntax.
+
+   Faulty example:
+
+   .. include:: ../../docs/gen/ex_PARAMNODEFAULT_faulty.rst
+
+   Results in:
+
+   .. include:: ../../docs/gen/ex_PARAMNODEFAULT_msg.rst
+
+   To fix the issue, move to an ANSI-style declaration.
+
+   Suppressing this error will only suppress the IEEE-required check; it
+   will simulate correctly.
+
+
 .. option:: PINCONNECTEMPTY
 
    .. TODO better example
@@ -1235,7 +1435,7 @@ List Of Warnings
 
 .. option:: PINMISSING
 
-   .. TODO better example
+   .. TODO better example (frequent)
 
    Warns that a module has a pin that is not mentioned in an instance.  If
    a pin is not missing it should still be specified on the instance
@@ -1244,6 +1444,22 @@ List Of Warnings
    Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
+   Faulty example:
+
+   .. include:: ../../docs/gen/ex_PINMISSING_faulty.rst
+
+   Results in:
+
+   .. include:: ../../docs/gen/ex_PINMISSING_msg.rst
+
+   Repaired example:
+
+   .. code-block:: sv
+      :emphasize-lines: 2
+
+         sub sub (
+                  .port());
+
    Other tools with similar warnings: Icarus Verilog's portbind, "warning:
    Instantiating module ... with dangling input port (...)". Slang's
    unconnected-port, "port '...' has no connection".
@@ -1275,7 +1491,7 @@ List Of Warnings
          generate
             if (A==0) begin
                b b_inst1 (.x(1'b0));  //<--- error nonexistent port
-               b #(.PX(1'b0)) b_inst2 (); //<--- error nonexistent parameter
+               b #(.PX(1'b0)) b_inst2 ();  //<--- error nonexistent parameter
             end
           endgenerate
        endmodule
@@ -1292,6 +1508,15 @@ List Of Warnings
    This error may be disabled with a lint_off PINNOTFOUND metacomment.
 
 
+.. option:: PKGNODECL
+
+   Never issued since version 5.038.  Historically an error that a
+   package/class appears to have been referenced that has not yet been
+   declared.  According to IEEE 1800-2023 26.3, all packages must be
+   declared before being used. However, several standard libraries
+   including UVM violate this, and other tools do not warn.
+
+
 .. option:: PORTSHORT
 
    Warns that an output port is connected to a constant.
@@ -1315,13 +1540,63 @@ List Of Warnings
    This error may be disabled with a lint_off PORTSHORT metacomment.
 
 
-.. option:: PKGNODECL
+.. option:: PREPROCZERO
 
-   .. TODO better example
+   Warns that a preprocessor \`ifdef/\`ifndef expression (added in IEEE
+   1800-2023) evaluates a define value which has a value of :code:`0`.
+   This will evaluate in the expression as :code:`1` because the define has
+   a definition, unlike in the C preprocessor, which evaluates using the
+   define's value (of :code:`1`).
 
-   An error that a package/class appears to have been referenced that has not
+   Referring to a define with an empty value does not give this warning, as
-   yet been declared.  According to IEEE 1800-2017 26.3, all packages must
+   in C, the preprocessor will give an error on a preprocessor expression
-   be declared before being used.
+   of a define that is empty.
+
+   .. code-block:: sv
+      :linenos:
+      :emphasize-lines: 2
+
+       `define ZERO 0
+       `ifdef (ZERO || ZERO)  //<--- warning PREPROCZERO
+        `error This_will_error_which_might_be_not_the_intent
+       `endif
+
+   The portable way to suppress this warning is to use a define value other
+   than zero, when it is to be used in a preprocessor expression.
+
+   Ignoring this warning will only suppress the lint check; it will
+   simulate correctly.
+
+
+.. option:: PROCASSINIT
+
+   Warns that the specified signal is given an initial value where it is
+   declared, and is also driven in an always process.  Typically such
+   initial values should instead be set using a reset signal inside the
+   process, to match requirements of ASIC synthesis tools.  However,
+   declaration initializers are a valid FPGA design idiom and therefore,
+   FPGA users may want to disable this warning.
+
+   Faulty example:
+
+   .. include:: ../../docs/gen/ex_PROCASSINIT_faulty.rst
+
+   Results in:
+
+   .. include:: ../../docs/gen/ex_PROCASSINIT_msg.rst
+
+   One possible fix, adding a reset to the always:
+
+   .. include:: ../../docs/gen/ex_PROCASSINIT_fixed.rst
+
+   Alternatively, use an initial block for the initialization:
+
+   .. code-block:: sv
+
+      initial flop_out = 1;  // <--- Fixed
+
+   Disabled by default as this is a code-style warning; it will simulate
+   correctly.
 
 
 .. option:: PROCASSWIRE
@@ -1354,13 +1629,29 @@ List Of Warnings
    inside the protected region will be partly checked for correctness but is
    otherwise ignored.
 
-   Suppressing the warning may make Verilator differ from a simulator that
+   Ignoring the warning may make Verilator differ from a simulator that
    accepts the protected code.
 
 
+.. option:: PROTOTYPEMIS
+
+   Error that a function prototype does not match in some respects the
+   out-of-block declaration of that function. IEEE requires this error.
+
+   The typical solution is to fix the prototype to match the declaration
+   exactly, including in number of arguments, name of arguments, argument
+   data types, and return data type (for functions).
+
+   Disabling this error will cause Verilator to ignore the prototype and
+   may make the code illegal in other tools.
+
+
 .. option:: RANDC
 
-   Warns that the :code:`randc` keyword is unsupported and being converted
+   Historical, never issued since version 5.018, when :code:`randc` became
+   fully supported.
+
+   Warned that the :code:`randc` keyword was unsupported and was converted
    to :code:`rand`.
 
 
@@ -1369,6 +1660,9 @@ List Of Warnings
    Warns that a real number is being implicitly rounded to an integer, with
    possible loss of precision.
 
+   Ignoring this warning will only suppress the lint check; it will
+   simulate correctly.
+
    Faulty example:
 
    .. code-block:: sv
@@ -1398,8 +1692,12 @@ List Of Warnings
 
 .. option:: REDEFMACRO
 
-   Warns that the code has redefined the same macro with a different value,
+   Warns that the code has redefined the same macro with a different value.
-   for example:
+
+   Ignoring this warning will only suppress the lint check; it will
+   simulate correctly.
+
+   For example:
 
    .. code-block:: sv
       :linenos:
@@ -1503,6 +1801,51 @@ List Of Warnings
    modeled values, or DPI calls.
 
 
+.. option:: SIDEEFFECT
+
+   Warns that an expression has a side effect that might not properly be
+   executed by Verilator.
+
+   This often represents a bug in Verilator, as opposed to a bad code
+   construct, however the Verilog code can typically be changed to avoid
+   the warning.
+
+   Faulty example:
+
+   .. code-block:: sv
+      :linenos:
+      :emphasize-lines: 1
+
+         x = y[a++];
+
+   This example warns because Verilator does not currently handle side
+   effects inside array subscripts; the a++ may be executed multiple times.
+
+   Rewrite the code to avoid expression side effects, typically by using a
+   temporary:
+
+   .. code-block:: sv
+      :linenos:
+
+         temp = a++;
+         x = y[temp];
+
+   Ignoring this warning may make Verilator simulations differ from other
+   simulators.
+
+
+.. option:: SPECIFYIGN
+
+   Warns that Verilator does not support certain constructs in
+   :code:`specify` blocks, nor :code:`$sdf_annotate`, and the construct was
+   ignored.
+
+   Disabling the :option:`UNSUPPORTED` error also disables this warning.
+
+   Ignoring this warning may make Verilator ignore lint checking on the
+   construct, and get different results from other simulators.
+
+
 .. option:: SPLITVAR
 
    Warns that a variable with a :option:`/*verilator&32;split_var*/`
@@ -1575,6 +1918,9 @@ List Of Warnings
    Warning that a symbol matches a C++ reserved word, and using this as a
    symbol name would result in odd C++ compiler errors.  You may disable
    this warning, but Verilator will rename the symbol to avoid conflict.
+   If you are using `--vpi` and only mark things as public for VPI access
+   (and not C++ access) then it is advisable to disable this warning with
+   :code:`-Wno-SYMRSVDWORD`.
 
 
 .. option:: SYNCASYNCNET
@@ -1663,7 +2009,7 @@ List Of Warnings
 
    .. code-block::
 
-         %Warning-TIMESCALEMOD: example.v:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.3)
+         %Warning-TIMESCALEMOD: example.v:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
 
    Recommend using :vlopt:`--timescale` argument, or in front of all
    modules use:
@@ -1807,7 +2153,8 @@ List Of Warnings
 
 .. option:: UNPACKED
 
-   Warns that unpacked structs and unions are not supported.
+   Warns that unpacked structs and unions are not supported because
+   :vlopt:`--structs-packed` was used, or by up through version 5.004.
 
    Ignoring this warning will make Verilator treat the structure as packed,
    which may make Verilator simulations differ from other simulators. This
@@ -1858,14 +2205,16 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that the specified genvar is never used/consumed.
+   Warns that the specified genvar is never used/consumed. See similar
+   :option:`UNUSEDSIGNAL`.
 
 
 .. option:: UNUSEDPARAM
 
    .. TODO better example
 
-   Warns that the specified parameter is never used/consumed.
+   Warns that the specified parameter is never used/consumed. See similar
+   :option:`UNUSEDSIGNAL`.
 
 
 .. option:: UNUSEDSIGNAL
@@ -1886,12 +2235,12 @@ List Of Warnings
 
    .. code-block:: sv
 
-         wire _unused_ok = &{1'b0,
+         wire _unused_ok = 1'b0 && &{1'b0,
                              sig_not_used_a,
                              sig_not_used_yet_b,  // To be fixed
                              1'b0};
 
-   The reduction AND and constant zeros mean the net will always be zero,
+   The AND with constant zero mean the net will always be zero,
    so won't use simulation runtime.  The redundant leading and trailing
    zeros avoid syntax errors if there are no signals between them.  The
    magic name "unused" (controlled by the :vlopt:`--unused-regexp` option)
@@ -1905,7 +2254,7 @@ List Of Warnings
 .. option:: USERERROR
 
    A SystemVerilog elaboration-time assertion error was executed.
-   IEEE 1800-2017 20.11 requires this error.
+   IEEE 1800-2023 20.11 requires this error.
 
    Faulty example:
 
@@ -1921,7 +2270,7 @@ List Of Warnings
 .. option:: USERFATAL
 
    A SystemVerilog elaboration-time assertion fatal was executed.
-   IEEE 1800-2017 20.11 requires this error.
+   IEEE 1800-2023 20.11 requires this error.
 
    Faulty example:
 
@@ -1937,7 +2286,7 @@ List Of Warnings
 .. option:: USERINFO
 
    A SystemVerilog elaboration-time assertion print was executed.  This is
-   not an error or warning, and IEEE 1800-2017 20.11 requires this
+   not an error or warning, and IEEE 1800-2023 20.11 requires this
    behavior.
 
    Example:
@@ -1952,7 +2301,7 @@ List Of Warnings
 .. option:: USERWARN
 
    A SystemVerilog elaboration-time assertion warning was executed.
-   IEEE 1800-2017 20.11 requires this warning.
+   IEEE 1800-2023 20.11 requires this warning.
 
    Faulty example:
 
@@ -1983,18 +2332,24 @@ List Of Warnings
 
    .. include:: ../../docs/gen/ex_VARHIDDEN_msg.rst
 
-   To resolve this, rename the variable to an unique name.
+   To resolve this, rename the inner or outer variable to an unique name.
 
 
 .. option:: WAITCONST
 
-   .. code-block:: sv
-
-         wait(0);  // Blocks forever
-
    Warns that a `wait` statement awaits a constant condition, which means it
    either blocks forever or never blocks.
 
+   As a special case `wait(0)` with the literal constant `0` (as opposed to
+   something that elaborates to zero), does not warn, as it is presumed the
+   code is making the intent clear.
+
+   Faulty example:
+
+   .. code-block:: sv
+
+         wait(1);  // Blocks forever
+
 
 .. option:: WIDTH
 
@@ -2031,7 +2386,7 @@ List Of Warnings
 
    .. include:: ../../docs/gen/ex_WIDTHEXPAND_1_faulty.rst
 
-   Results in a WIDTHEXPAND warning:
+   Results in a :option:`WIDTHEXPAND` warning:
 
    .. include:: ../../docs/gen/ex_WIDTHEXPAND_1_msg.rst
 
@@ -2039,17 +2394,6 @@ List Of Warnings
 
    .. include:: ../../docs/gen/ex_WIDTHEXPAND_1_fixed.rst
 
-.. option:: WIDTHTRUNC
-
-   A more granular WIDTH warning, for when a value is truncated
-
-.. option:: WIDTHEXPAND
-
-   A more granular WIDTH warning, for when a value is zero expanded
-
-.. option:: WIDTHXZEXPAND
-
-   A more granular WIDTH warning, for when a value is X/Z expanded
 
 .. option:: WIDTHCONCAT
 
@@ -2076,9 +2420,67 @@ List Of Warnings
    width to the parameter usage (:code:`{PAR[31:0], PAR[31:0]}`).
 
 
+.. option:: WIDTHEXPAND
+
+   A more granular :option:`WIDTH` warning, for when a value is zero
+   expanded. See :option:`WIDTH`.
+
+.. option:: WIDTHTRUNC
+
+   A more granular :option:`WIDTH` warning, for when a value is
+   truncated. See :option:`WIDTH`.
+
+.. option:: WIDTHXZEXPAND
+
+   A more granular :option:`WIDTH` warning, for when a value is X/Z
+   expanded. See :option:`WIDTH`.
+
 .. option:: ZERODLY
 
    Warns that `#0` delays do not schedule the process to be resumed in the
    Inactive region. Such processes do get resumed in the same time slot
    somewhere in the Active region. Issued only if Verilator is run with the
    :vlopt:`--timing` option.
+
+.. option:: ZEROREPL
+
+   Warns that zero is used as the replication value in the replication
+   operator. This is specified as an error by IEEE 1800-2023 11.4.12.1.
+
+   Faulty example:
+
+   .. code-block:: sv
+      :linenos:
+      :emphasize-lines: 5
+
+         module dut
+            #(parameter int MY_PARAM = 0);
+           reg [7:0] data;
+           always @* begin
+             data = {MY_PARAM{1'b1}};  //<--- Warning
+           end
+         endmodule
+
+   Results in the following error:
+
+   .. code-block::
+
+       %Error-ZEROREPL: test.v:5:22: Replication value of 0 is only legal under a concatenation (IEEE 1800-2023 11.4.12.1)
+
+   Note that in some cases, this warning may be false, when a condition
+   upstream or downstream of the access means the zero replication will
+   never execute or be used.
+
+   Repaired example:
+
+   .. code-block:: sv
+      :linenos:
+      :emphasize-lines: 2
+
+         module dut
+            #(parameter int MY_PARAM = 1);  //<--- REPAIRED
+           reg [7:0] data;
+           always @* begin
+             data = {MY_PARAM{1'b1}};
+           end
+         endmodule