Fix error when force assignment is used with ref function args (#6244)

src/V3Force.cpp

@@ -364,9 +364,6 @@ class ForceReplaceVisitor final : public VNVisitor {
             // Replace VarRef from forced LHS with rdVscp.
             if (ForceState::ForceComponentsVarScope* const fcp
                 = m_state.tryGetForceComponents(nodep)) {
-                FileLine* const flp = nodep->fileline();
-                AstVarRef* const origp = new AstVarRef{flp, nodep->varScopep(), VAccess::READ};
-                ForceState::markNonReplaceable(origp);
                 nodep->varp(fcp->m_rdVscp->varp());
                 nodep->varScopep(fcp->m_rdVscp);
             }
@@ -398,7 +395,11 @@ class ForceReplaceVisitor final : public VNVisitor {
             break;
         }
         default:
-            nodep->v3error("Unsupported: Signals used via read-write reference cannot be forced");
+            if (!m_inLogic) return;
+            if (m_state.tryGetForceComponents(nodep) || ForceState::getValVscp(nodep)) {
+                nodep->v3error(
+                    "Unsupported: Signals used via read-write reference cannot be forced");
+            }
             break;
         }
     }

test_regress/t/t_force_readwrite.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile(verilator_flags2=["--exe", "--main", "--timing"])
+
+test.execute()
+
+test.passes()

test_regress/t/t_force_readwrite.v

@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls;
+  task take_ref(ref logic s);
+  endtask
+endclass
+
+module t;
+  logic a;
+  logic b = 1;
+  logic c;
+  Cls   cls = new;
+
+  initial begin
+    force a = b;
+    cls.take_ref(c);
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule

test_regress/t/t_force_readwrite_unsup.out

@@ -0,0 +1,8 @@
+%Error: t/t_force_readwrite_unsup.v:25:18: Unsupported: Signals used via read-write reference cannot be forced
+   25 |     cls.take_ref(a);
+      |                  ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_force_readwrite_unsup.v:26:18: Unsupported: Signals used via read-write reference cannot be forced
+   26 |     cls.take_ref(b);
+      |                  ^
+%Error: Exiting due to

test_regress/t/t_force_readwrite_unsup.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_force_readwrite_unsup.v

@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls;
+  task take_ref(ref logic s);
+  endtask
+endclass
+
+module t;
+  logic a;
+  logic b = 1;
+  Cls   cls = new;
+
+  initial begin
+    force a = b;
+    cls.take_ref(a);
+    cls.take_ref(b);
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule