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Unsupported instead of syntax error on parameter var initial values

This commit is contained in:
Wilson Snyder 2023-09-08 08:37:17 -04:00
parent 139e93d371
commit 014301587f
4 changed files with 81 additions and 10 deletions
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23
src/verilog.y
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@ -4334,13 +4334,15 @@ elaboration_system_task_guts<nodep>: // IEEE: part of elaboration_system_task
| yD_FATAL '(' expr ',' exprListE ')' { $$ = new AstElabDisplay{$1, VDisplayType::DT_FATAL, $5}; DEL($3); }
;
//UNSUPproperty_actual_arg<nodeExprp>: // ==IEEE: property_actual_arg
//UNSUP // // IEEE: property_expr
//UNSUP // // IEEE: sequence_actual_arg
//UNSUP pev_expr { $$ = $1; }
//UNSUP // // IEEE: sequence_expr
//UNSUP // // property_expr already includes sequence_expr
//UNSUP ;
property_actual_arg<nodeExprp>: // ==IEEE: property_actual_arg
// // IEEE: property_expr
// // IEEE: sequence_actual_arg
//UNSUP pev_expr { $$ = $1; }
//UNSUP remove below:
pexpr { $$ = $1; }
// // IEEE: sequence_expr
// // property_expr already includes sequence_expr
;
exprOrDataType<nodep>: // expr | data_type: combined to prevent conflicts
expr { $$ = $1; }
@ -4902,7 +4904,7 @@ fexpr<nodeExprp>: // For use as first part of statement (disam
BISONPRE_COPY(expr,{s/~l~/f/g; s/~r~/f/g; s/~f__IGNORE~/__IGNORE/g;}) // {copied}
;
//UNSUPev_expr<nodeExprp>: // IEEE: event_expression
//UNSUPpev_expr<nodeExprp>: // IEEE: event_expression
//UNSUP // // for yOR/, see event_expression
//UNSUP //
//UNSUP // // IEEE: [ edge_identifier ] expression [ yIFF expression ]
@ -5938,8 +5940,9 @@ property_port_itemFront: // IEEE: part of property_port_item/sequence_port_item
property_port_itemAssignment<nodep>: // IEEE: part of property_port_item/sequence_port_item/checker_port_direction
id variable_dimensionListE { $$ = VARDONEA($<fl>1, *$1, $2, nullptr); }
//UNSUP|id variable_dimensionListE '=' property_actual_arg
//UNSUP { VARDONE($<fl>1, $1, $2, $4); PINNUMINC(); }
| id variable_dimensionListE '=' property_actual_arg
{ $$ = VARDONEA($<fl>1, *$1, $2, $4);
BBUNSUP($3, "Unsupported: property variable default value"); }
;
property_port_itemDirE:

10
test_regress/t/t_assert_property_var_unsup.out Normal file
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@ -0,0 +1,10 @@
%Error: t/t_assert_property_var_unsup.v:17:11: syntax error, unexpected IDENTIFIER, expecting "'{"
17 | int prevcyc;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_assert_property_var_unsup.v:24:31: Unsupported: property variable default value
24 | property with_def(int nine = 9);
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Internal Error: t/t_assert_property_var_unsup.v:7:8: ../V3ParseSym.h:#: Symbols suggest ending PROPERTY 'prop' but parser thinks ending MODULE 't'
7 | module t (
| ^

20
test_regress/t/t_assert_property_var_unsup.pl Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
compile(
expect_filename => $Self->{golden_filename},
verilator_flags2 => ['--assert --error-limit 1000'],
fails => 1,
);
ok(1);
1;

38
test_regress/t/t_assert_property_var_unsup.v Normal file
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@ -0,0 +1,38 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
int cyc;
bit valid;
property prop;
int prevcyc;
(valid, prevcyc = cyc) |=> (cyc == prevcyc + 1);
endproperty
default clocking @(posedge clk); endclocking
assert property(prop);
property with_def(int nine = 9);
cyc == 9 |-> cyc == nine;
endproperty
assert property(with_def);
always @(posedge clk) begin
cyc <= cyc + 1;
valid <= cyc == 5;
if (cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule