Improve error that assert-under-assert is unsupported

This commit is contained in:
Wilson Snyder 2023-09-03 09:08:43 -04:00
parent c8c980c49d
commit de77f1ee5c
5 changed files with 74 additions and 2 deletions

View File

@ -89,7 +89,9 @@ private:
}
}
void visit(AstNodeCoverOrAssert* nodep) override {
if (m_assertp) nodep->v3error("Assert not allowed under another assert");
if (m_assertp) {
nodep->v3warn(E_UNSUPPORTED, "Unsupported: Assert not allowed under another assert");
}
m_assertp = nodep;
iterateChildren(nodep);
m_assertp = nullptr;

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@ -0,0 +1,5 @@
%Error-UNSUPPORTED: t/t_cover_assert.v:42:16: Unsupported: Assert not allowed under another assert
42 | A2: assert (b);
| ^~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

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@ -0,0 +1,20 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
lint(
verilator_flags2 => ["-Wall -Wno-DECLFILENAME --coverage"],
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

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@ -0,0 +1,46 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
bit a;
bit b;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 0) begin
a <= '0;
b <= '0;
end
else if (cyc == 10) begin
a <= '1;
b <= '1;
end
else if (cyc == 11) begin
a <= '0;
b <= '1;
end
else if (cyc == 99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always_ff @(posedge clk) begin
C1: cover property(a)
begin
// Assert under cover legal in some other simulators
A2: assert (b);
end
end
endmodule

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@ -37,7 +37,6 @@ foreach my $s (
'/*verilator sformat*/ can only be applied to last argument of ',
'Argument needed for string.',
'Array initialization has too few elements, need element ',
'Assert not allowed under another assert',
'Assigned pin is neither input nor output',
'Assignment pattern with no members',
'Attempted parameter setting of non-parameter: Param ',