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Commentary: FPGA PROCASSINIT guidance (#6067)

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Todd Strader
2025-06-06 09:59:05 -04:00
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parent 1a3fd92063
commit 9fc223d3ee
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docs/guide/warnings.rst
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@@ -1473,7 +1473,9 @@ List Of Warnings
Warns that the specified signal is given an initial value where it is
declared, and is also driven in an always process. Typically such
initial values should instead be set using a reset signal inside the
process, to match requirements of hardware synthesis tools.
process, to match requirements of ASIC synthesis tools. However,
declaration initializers are a valid FPGA design idiom and therefore,
FPGA users may want to disable this warning.
Faulty example: