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Internals: Avoid extranious base class calls in recent commit.

This commit is contained in:
Wilson Snyder 2023-12-01 19:05:21 -05:00
parent bd38c8fe3c
commit b4baa7ce02
2 changed files with 7 additions and 10 deletions
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15
src/astgen
View File

@ -993,11 +993,9 @@ def write_ast_impl(filename):
continue
emitBlock("const char* Ast{t}::brokenGen() const {{\n",
t=node.name)
for superClass in node.allSuperClasses:
if superClass.name != 'Node':
emitBlock(
" BROKEN_BASE_RTN(Ast{super}::brokenGen());\n",
super=superClass.name)
if node.superClass.name != 'Node':
emitBlock(" BROKEN_BASE_RTN(Ast{base}::brokenGen());\n",
base=node.superClass.name)
for ptr in node.ptrs:
if ptr['monad'] == 'Optional':
emitBlock(
@ -1011,10 +1009,9 @@ def write_ast_impl(filename):
emitBlock(" return Ast{t}::broken(); }}\n", t=node.name)
emitBlock("void Ast{t}::cloneRelinkGen() {{\n", t=node.name)
for superClass in node.allSuperClasses:
if superClass.name != 'Node':
emitBlock(" Ast{super}::cloneRelinkGen();\n",
super=superClass.name)
if node.superClass.name != 'Node':
emitBlock(" Ast{base}::cloneRelinkGen();\n",
base=node.superClass.name)
for ptr in node.ptrs:
emitBlock(
" if (m_{name} && m_{name}->clonep()) m_{name} = m_{name}->clonep();\n",

2
test_regress/t/t_timing_zerodly.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.