Fix DFG circular driver tracing
This commit is contained in:
Geza Lore
parent
e753480b19
commit
9c11f5e05d
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@ -192,7 +192,7 @@ class TraceDriver final : public DfgVisitor {
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}
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template <typename Vertex>
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Vertex* traceBinary(Vertex* vtxp) {
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Vertex* traceBitwiseBinary(Vertex* vtxp) {
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static_assert(std::is_base_of<DfgVertexBinary, Vertex>::value,
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"Should only call on DfgVertexBinary");
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if (DfgVertex* const rp = trace(vtxp->rhsp(), m_msb, m_lsb)) {
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@ -206,6 +206,39 @@ class TraceDriver final : public DfgVisitor {
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return nullptr;
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}
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template <typename Vertex>
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DfgVertex* traceAddSub(Vertex* vtxp) {
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static_assert(std::is_base_of<DfgVertexBinary, Vertex>::value,
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"Should only call on DfgVertexBinary");
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if (DfgVertex* const rp = trace(vtxp->rhsp(), m_msb, 0)) {
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if (DfgVertex* const lp = trace(vtxp->lhsp(), m_msb, 0)) {
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Vertex* const opp = make<Vertex>(vtxp, m_msb + 1);
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opp->rhsp(rp);
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opp->lhsp(lp);
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DfgSel* const selp = make<DfgSel>(vtxp, m_msb - m_lsb + 1);
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selp->fromp(opp);
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selp->lsb(m_lsb);
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return selp;
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}
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}
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return nullptr;
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}
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template <typename Vertex>
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Vertex* traceCmp(Vertex* vtxp) {
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static_assert(std::is_base_of<DfgVertexBinary, Vertex>::value,
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"Should only call on DfgVertexBinary");
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if (DfgVertex* const rp = trace(vtxp->rhsp(), vtxp->rhsp()->width() - 1, 0)) {
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if (DfgVertex* const lp = trace(vtxp->lhsp(), vtxp->lhsp()->width() - 1, 0)) {
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Vertex* const resp = make<Vertex>(vtxp, m_msb - m_lsb + 1);
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resp->rhsp(rp);
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resp->lhsp(lp);
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return resp;
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}
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}
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return nullptr;
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}
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// Predicate to do determine if vtxp[$bits(vtxp)-1:idx] is known to be zero
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// Somewhat rudimentary but sufficient for current purposes.
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static bool knownToBeZeroAtAndAbove(const DfgVertex* vtxp, uint32_t idx) {
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@ -356,47 +389,47 @@ class TraceDriver final : public DfgVisitor {
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void visit(DfgAnd* vtxp) override {
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if (!m_aggressive) return;
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SET_RESULT(traceBinary(vtxp));
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SET_RESULT(traceBitwiseBinary(vtxp));
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}
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void visit(DfgOr* vtxp) override {
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if (!m_aggressive) return;
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SET_RESULT(traceBinary(vtxp));
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SET_RESULT(traceBitwiseBinary(vtxp));
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}
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void visit(DfgXor* vtxp) override {
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if (!m_aggressive) return;
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SET_RESULT(traceBinary(vtxp));
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SET_RESULT(traceBitwiseBinary(vtxp));
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}
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void visit(DfgAdd* vtxp) override {
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if (!m_aggressive) return;
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SET_RESULT(traceBinary(vtxp));
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SET_RESULT(traceAddSub(vtxp));
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}
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void visit(DfgSub* vtxp) override {
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if (!m_aggressive) return;
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SET_RESULT(traceBinary(vtxp));
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SET_RESULT(traceAddSub(vtxp));
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}
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void visit(DfgEq* vtxp) override {
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if (!m_aggressive) return;
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SET_RESULT(traceBinary(vtxp));
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SET_RESULT(traceCmp(vtxp));
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}
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void visit(DfgNeq* vtxp) override {
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if (!m_aggressive) return;
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SET_RESULT(traceBinary(vtxp));
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SET_RESULT(traceCmp(vtxp));
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}
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void visit(DfgLt* vtxp) override {
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if (!m_aggressive) return;
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SET_RESULT(traceBinary(vtxp));
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SET_RESULT(traceCmp(vtxp));
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}
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void visit(DfgLte* vtxp) override {
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if (!m_aggressive) return;
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SET_RESULT(traceBinary(vtxp));
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SET_RESULT(traceCmp(vtxp));
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}
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void visit(DfgGt* vtxp) override {
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if (!m_aggressive) return;
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SET_RESULT(traceBinary(vtxp));
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SET_RESULT(traceCmp(vtxp));
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}
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void visit(DfgGte* vtxp) override {
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if (!m_aggressive) return;
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SET_RESULT(traceBinary(vtxp));
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SET_RESULT(traceCmp(vtxp));
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}
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void visit(DfgShiftR* vtxp) override {
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@ -1032,39 +1065,45 @@ class FixUpIndependentRanges final {
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lsb = msb + 1;
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}
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// If we managed to imporove something, apply the replacement
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if (nImprovements) {
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// Concatenate all the terms to create the replacement
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DfgVertex* replacementp = termps.front();
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const uint64_t vComp = vtxp->getUser<uint64_t>();
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for (size_t i = 1; i < termps.size(); ++i) {
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DfgVertex* const termp = termps[i];
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const uint32_t catWidth = replacementp->width() + termp->width();
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AstNodeDType* const dtypep = DfgVertex::dtypeForWidth(catWidth);
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DfgConcat* const catp = new DfgConcat{dfg, flp, dtypep};
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catp->rhsp(replacementp);
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catp->lhsp(termp);
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// Need to figure out which component the replacement vertex
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// belongs to. If any of the terms are of the original
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// component, it's part of that component, otherwise its not
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// cyclic (all terms are from outside the original component,
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// and feed into the original component).
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const uint64_t tComp = termp->getUser<uint64_t>();
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const uint64_t rComp = replacementp->getUser<uint64_t>();
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catp->setUser<uint64_t>(tComp == vComp || rComp == vComp ? vComp : 0);
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replacementp = catp;
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}
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// If no imporovement was possible, delete the terms we just created
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if (!nImprovements) {
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for (DfgVertex* const vtxp : termps) VL_DO_DANGLING(vtxp->unlinkDelete(dfg), vtxp);
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termps.clear();
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return 0;
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}
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// Replace the vertex
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vtxp->replaceWith(replacementp);
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// Connect the Sel nodes in the replacement
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for (DfgVertex* const termp : termps) {
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if (DfgSel* const selp = termp->cast<DfgSel>()) {
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if (!selp->fromp()) selp->fromp(vtxp);
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}
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// We managed to imporove something, apply the replacement
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// Concatenate all the terms to create the replacement
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DfgVertex* replacementp = termps.front();
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const uint64_t vComp = vtxp->getUser<uint64_t>();
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for (size_t i = 1; i < termps.size(); ++i) {
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DfgVertex* const termp = termps[i];
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const uint32_t catWidth = replacementp->width() + termp->width();
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AstNodeDType* const dtypep = DfgVertex::dtypeForWidth(catWidth);
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DfgConcat* const catp = new DfgConcat{dfg, flp, dtypep};
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catp->rhsp(replacementp);
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catp->lhsp(termp);
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// Need to figure out which component the replacement vertex
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// belongs to. If any of the terms are of the original
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// component, it's part of that component, otherwise its not
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// cyclic (all terms are from outside the original component,
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// and feed into the original component).
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const uint64_t tComp = termp->getUser<uint64_t>();
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const uint64_t rComp = replacementp->getUser<uint64_t>();
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catp->setUser<uint64_t>(tComp == vComp || rComp == vComp ? vComp : 0);
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replacementp = catp;
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}
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// Replace the vertex
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vtxp->replaceWith(replacementp);
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// Connect the Sel nodes in the replacement
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for (DfgVertex* const termp : termps) {
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if (DfgSel* const selp = termp->cast<DfgSel>()) {
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if (!selp->fromp()) selp->fromp(vtxp);
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}
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}
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// Done
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return nImprovements;
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}
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@ -42,11 +42,12 @@ with open(rdFile, 'r', encoding="utf8") as rdFh, \
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open(pdeclFile, 'w', encoding="utf8") as pdeclFh, \
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open(checkFile, 'w', encoding="utf8") as checkFh:
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for line in rdFh:
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if "// UNOPTFLAT" in line:
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nExpectedCycles += 1
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line = line.split("//")[0]
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m = re.search(r'`signal\((\w+),', line)
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if not m:
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continue
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nExpectedCycles += 1
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sig = m.group(1)
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plistFh.write(sig + ",\n")
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pdeclFh.write("output " + sig + ";\n")
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@ -26,56 +26,56 @@ module t (
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// Interesting user code to cover
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//////////////////////////////////////////////////////////////////////////
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`signal(GRAY_SEL, 3);
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`signal(GRAY_SEL, 3); // UNOPTFLAT
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assign GRAY_SEL = rand_a[2:0] ^ 3'(GRAY_SEL[2:1]);
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`signal(GRAY_SHIFT, 3);
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`signal(GRAY_SHIFT, 3); // UNOPTFLAT
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assign GRAY_SHIFT = rand_a[2:0] ^ (GRAY_SHIFT >> 1);
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`signal(GRAY_REV_SEL, 3);
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`signal(GRAY_REV_SEL, 3); // UNOPTFLAT
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assign GRAY_REV_SEL = rand_a[2:0] ^ {GRAY_REV_SEL[1:0], 1'b0};
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`signal(GRAY_REV_SHIFT, 3);
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`signal(GRAY_REV_SHIFT, 3); // UNOPTFLAT
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assign GRAY_REV_SHIFT = rand_a[2:0] ^ (GRAY_REV_SHIFT << 1);
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//////////////////////////////////////////////////////////////////////////
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// Fill coverage
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//////////////////////////////////////////////////////////////////////////
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`signal(CONCAT_RHS, 2);
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`signal(CONCAT_RHS, 2); // UNOPTFLAT
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assign CONCAT_RHS[0] = rand_a[0];
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assign CONCAT_RHS[1] = CONCAT_RHS[0];
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`signal(CONCAT_LHS, 2);
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`signal(CONCAT_LHS, 2); // UNOPTFLAT
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assign CONCAT_LHS[0] = CONCAT_LHS[1];
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assign CONCAT_LHS[1] = rand_a[1];
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`signal(CONCAT_MID, 3);
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`signal(CONCAT_MID, 3); // UNOPTFLAT
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assign CONCAT_MID[0] = |CONCAT_MID[2:1];
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assign CONCAT_MID[2:1] = {rand_a[2], ~rand_a[2]};
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`signal(SEL, 3);
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`signal(SEL, 3); // UNOPTFLAT
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assign SEL[0] = rand_a[4];
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assign SEL[1] = SEL[0];
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assign SEL[2] = SEL[1];
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`signal(EXTEND, 8);
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`signal(EXTEND, 8); // UNOPTFLAT
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assign EXTEND[0] = rand_a[3];
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assign EXTEND[3:1] = 3'(EXTEND[0]);
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assign EXTEND[4] = EXTEND[1];
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assign EXTEND[6:5] = EXTEND[2:1];
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assign EXTEND[7] = EXTEND[3];
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`signal(NOT, 3);
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`signal(NOT, 3); // UNOPTFLAT
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assign NOT = ~(rand_a[2:0] ^ 3'(NOT[2:1]));
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`signal(AND, 3);
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`signal(AND, 3); // UNOPTFLAT
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assign AND = rand_a[2:0] & 3'(AND[2:1]);
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`signal(OR, 3);
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`signal(OR, 3); // UNOPTFLAT
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assign OR = rand_a[2:0] | 3'(OR[2:1]);
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`signal(SHIFTR, 14);
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`signal(SHIFTR, 14); // UNOPTFLAT
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assign SHIFTR = {
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SHIFTR[6:5], // 13:12
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SHIFTR[7:6], // 11:10
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@ -84,10 +84,10 @@ module t (
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rand_a[3:0] // 3:0
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};
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`signal(SHIFTR_VARIABLE, 2);
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`signal(SHIFTR_VARIABLE, 2); // UNOPTFLAT
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assign SHIFTR_VARIABLE = rand_a[1:0] ^ ({1'b0, SHIFTR_VARIABLE[1]} >> rand_b[0]);
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`signal(SHIFTL, 14);
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`signal(SHIFTL, 14); // UNOPTFLAT
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assign SHIFTL = {
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SHIFTL[6:5], // 13:12
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SHIFTL[7:6], // 11:10
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@ -96,18 +96,18 @@ module t (
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rand_a[3:0] // 3:0
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};
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`signal(SHIFTL_VARIABLE, 2);
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`signal(SHIFTL_VARIABLE, 2); // UNOPTFLAT
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assign SHIFTL_VARIABLE = rand_a[1:0] ^ ({SHIFTL_VARIABLE[0], 1'b0} << rand_b[0]);
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`signal(VAR_A, 2);
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`signal(VAR_A, 2); // UNOPTFLAT
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wire logic [1:0] VAR_B;
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assign VAR_A = {rand_a[0], VAR_B[0]};
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assign VAR_B = (VAR_A >> 1) ^ 2'(VAR_B[1]);
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`signal(REPLICATE, 4);
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`signal(REPLICATE, 4); // UNOPTFLAT
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assign REPLICATE = rand_a[3:0] ^ ({2{REPLICATE[3:2]}} >> 2);
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`signal(PARTIAL, 4);
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`signal(PARTIAL, 4); // UNOPTFLAT
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assign PARTIAL[0] = rand_a[0];
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// PARTIAL[1] intentionally unconnected
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assign PARTIAL[3:2] = rand_a[3:2] ^ {PARTIAL[2], PARTIAL[0]};
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@ -115,14 +115,14 @@ module t (
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wire [2:0] array_0 [2];
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assign array_0[0] = rand_a[2:0];
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assign array_0[1] = array_0[0];
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`signal(ARRAY_0, 3);
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`signal(ARRAY_0, 3); // UNOPTFLAT
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assign ARRAY_0 = array_0[1];
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wire [2:0] array_1 [1];
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assign array_1[0][0] = rand_a[0];
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assign array_1[0][1] = array_1[0][0];
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assign array_1[0][2] = array_1[0][1];
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`signal(ARRAY_1, 3);
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`signal(ARRAY_1, 3); // UNOPTFLAT
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assign ARRAY_1 = array_1[0];
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wire [2:0] array_2a [2];
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@ -132,46 +132,66 @@ module t (
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assign array_2a[0][2] = array_2b[1][1];
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assign array_2a[1] = array_2a[0];
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assign array_2b = array_2a;
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`signal(ARRAY_2, 3);
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`signal(ARRAY_2, 3); // UNOPTFLAT
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assign ARRAY_2 = array_2a[0];
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wire [2:0] array_3 [2];
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assign array_3[0] = rand_a[2:0] ^ array_3[1] >> 1;
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assign array_3[1] = array_3[0];
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`signal(ARRAY_3, 3);
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`signal(ARRAY_3, 3); // UNOPTFLAT
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assign ARRAY_3 = array_3[0];
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`signal(ADD, 8);
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assign ADD = ((ADD << 4) + 8'(rand_a[3:0]));
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`signal(ADD_A, 8); // UNOPTFLAT
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`signal(ADD_B, 8);
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`signal(ADD_C, 8);
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assign ADD_C = rand_b[7:0] + ADD_B;
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assign ADD_B = (ADD_A << 4) + rand_a[7:0];
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assign ADD_A = {ADD_C[7], 7'd0};
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`signal(SUB, 8);
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assign SUB = ((SUB << 4) - 8'(rand_a[3:0]));
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`signal(SUB_A, 8); // UNOPTFLAT
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`signal(SUB_B, 8);
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`signal(SUB_C, 8);
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assign SUB_C = rand_b[7:0] - SUB_B;
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assign SUB_B = (SUB_A << 4) - rand_a[7:0];
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assign SUB_A = {SUB_C[7], 7'd0};
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`signal(EQ, 2);
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assign EQ = {rand_a[0], EQ >> 1 == rand_b[1:0]};
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`signal(EQ_A, 1); // UNOPTFLAT
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`signal(EQ_B, 3);
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assign EQ_A = EQ_B >> 1 == rand_b[2:0];
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assign EQ_B = {rand_a[1:0], EQ_A};
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`signal(NEQ, 2);
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assign NEQ = {rand_a[0], NEQ >> 1 != rand_b[1:0]};
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`signal(NEQ_A, 1); // UNOPTFLAT
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`signal(NEQ_B, 3);
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assign NEQ_A = NEQ_B >> 1 != rand_b[2:0];
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assign NEQ_B = {rand_a[1:0], NEQ_A};
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`signal(LT, 2);
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assign LT = {rand_a[0], LT >> 1 < rand_b[1:0]};
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`signal(LT_A, 1); // UNOPTFLAT
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`signal(LT_B, 3);
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assign LT_A = LT_B >> 1 < rand_b[2:0];
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assign LT_B = {rand_a[1:0], LT_A};
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`signal(LTE, 2);
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assign LTE = {rand_a[0], LTE >> 1 <= rand_b[1:0]};
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`signal(LTE_A, 1); // UNOPTFLAT
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`signal(LTE_B, 3);
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assign LTE_A = LTE_B >> 1 <= rand_b[2:0];
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assign LTE_B = {rand_a[1:0], LTE_A};
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`signal(GT, 2);
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assign GT = {rand_a[0], GT >> 1 > rand_b[1:0]};
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`signal(GT_A, 1); // UNOPTFLAT
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`signal(GT_B, 3);
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assign GT_A = GT_B >> 1 > rand_b[2:0];
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assign GT_B = {rand_a[1:0], GT_A};
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`signal(GTE, 2);
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assign GTE = {rand_a[0], GTE >> 1 >= rand_b[1:0]};
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`signal(GTE_A, 1); // UNOPTFLAT
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`signal(GTE_B, 3);
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assign GTE_A = GTE_B >> 1 >= rand_b[2:0];
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assign GTE_B = {rand_a[1:0], GTE_A};
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`signal(COND_THEN, 3);
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`signal(COND_THEN, 3); // UNOPTFLAT
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assign COND_THEN = {rand_a[0], rand_a[0] ? 2'(COND_THEN << 2) : rand_b[1:0]};
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`signal(COND_ELSE, 3);
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`signal(COND_ELSE, 3); // UNOPTFLAT
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assign COND_ELSE = {rand_a[0], rand_a[0] ? rand_b[1:0] : 2'(COND_ELSE << 2)};
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`signal(COND_COND, 3);
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`signal(COND_COND, 3); // UNOPTFLAT
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assign COND_COND = {rand_a[0], (COND_COND >> 2) == 3'b001 ? rand_b[3:2] : rand_b[1:0]};
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endmodule
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|
|
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Loading…
Reference in New Issue