Add error when trying to assign class object to variable of non-class types (#6237)
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@ -7329,21 +7329,26 @@ class WidthVisitor final : public VNVisitor {
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}
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return false;
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}
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void checkClassAssign(AstNode* nodep, const char* side, AstNode* rhsp,
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void checkClassAssign(const AstNode* nodep, const char* side, AstNode* rhsp,
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AstNodeDType* const lhsDTypep) {
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if (AstClassRefDType* const lhsClassRefp = VN_CAST(lhsDTypep->skipRefp(), ClassRefDType)) {
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UASSERT_OBJ(rhsp->dtypep(), rhsp, "Node has no type");
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AstNodeDType* const rhsDtypep = rhsp->dtypep()->skipRefp();
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if (AstClassRefDType* const rhsClassRefp = VN_CAST(rhsDtypep, ClassRefDType)) {
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UASSERT_OBJ(rhsp->dtypep(), rhsp, "Node has no type");
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const AstNodeDType* const lhsRawDTypep = lhsDTypep->skipRefp();
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const AstNodeDType* const rhsRawDTypep = rhsp->dtypep()->skipRefp();
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if (const AstClassRefDType* const lhsClassRefp = VN_CAST(lhsRawDTypep, ClassRefDType)) {
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if (const AstClassRefDType* const rhsClassRefp
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= VN_CAST(rhsRawDTypep, ClassRefDType)) {
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if (isBaseClassRecurse(lhsClassRefp->classp(), rhsClassRefp->classp())) return;
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} else if (rhsp->isNull()) {
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return;
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}
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nodep->v3error(side << " expects a " << lhsClassRefp->prettyTypeName() << ", got "
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<< rhsDtypep->prettyTypeName());
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<< rhsRawDTypep->prettyTypeName());
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} else if (VN_IS(rhsRawDTypep, ClassRefDType)) {
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nodep->v3error(side << " " << rhsRawDTypep->prettyDTypeNameQ()
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<< " cannot be assigned to non-class "
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<< lhsDTypep->prettyDTypeNameQ());
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}
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if (VN_IS(lhsDTypep->skipRefp(), DynArrayDType)
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&& VN_IS(rhsp->dtypep()->skipRefp(), UnpackArrayDType)) {
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if (VN_IS(lhsRawDTypep, DynArrayDType) && VN_IS(rhsRawDTypep, UnpackArrayDType)) {
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VNRelinker relinker;
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rhsp->unlinkFrBack(&relinker);
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relinker.relink(
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@ -0,0 +1,5 @@
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%Error: t/t_class_to_basic_assignment_bad.v:26:29: Assign RHS 'class{}Foo' cannot be assigned to non-class 'int'
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26 | new_node.phase_done = get();
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| ^
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Exiting due to
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,32 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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int phase_done;
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static function Foo get();
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Foo ans = new;
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return ans;
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endfunction
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static function int create ();
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return 3;
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endfunction
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function string get_name ();
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return "bar";
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endfunction
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function void add(Foo phase);
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Foo new_node;
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if (new_node.get_name() == "run") begin
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new_node.phase_done = get();
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end
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else begin
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new_node.phase_done = create();
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end
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endfunction
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endclass
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@ -7,7 +7,7 @@
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class Cls;
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int x = 1;
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function new();
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int p = process::self();
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process p = process::self();
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endfunction
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endclass
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