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Document and test `+verilator+rand+reset+2` usage (#6285 partial)

This commit is contained in:
Wilson Snyder 2025-08-16 11:47:19 -04:00
parent 340d1aff4a
commit 48a12fb0f4
50 changed files with 201 additions and 172 deletions
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23
docs/guide/exe_verilator.rst
View File

@ -1969,14 +1969,13 @@ Summary:
different seeds on different executions. This method is the slowest,
but safest for finding reset bugs.
If using `--x-assign unique`, you may want to seed your random number
generator such that each regression run gets a different randomization
sequence. The simplest is to use the
:vlopt:`+verilator+seed+\<value\>` runtime option. Alternatively, use
the system's :code:`srand48()` or for Windows :code:`srand()` function
to do this. You'll probably also want to print any seeds selected,
and code to enable rerunning with that same seed so you can reproduce
bugs.
If using `--x-assign unique`, use the
:vlopt:`+verilator+rand+reset+2 <+verilator+rand+reset+\<value\>>`
runtime option, and seed the runtime random number generator such that
each regression run gets a different randomization sequence with
:vlopt:`+verilator+seed+\<value\>`. You'll probably also want to
print any seeds selected, and code to enable rerunning with that same
seed, so you can reproduce bugs.
.. note::
@ -1999,6 +1998,14 @@ Summary:
use for each initialization. This gives the greatest flexibility and
allows for finding reset bugs. See :ref:`Unknown states`.
If using `--x-initial unique`, use the
:vlopt:`+verilator+rand+reset+2 <+verilator+rand+reset+\<value\>>`
runtime option, and seed the runtime random number generator such that
each regression run gets a different randomization sequence with
:vlopt:`+verilator+seed+\<value\>`. You'll probably also want to
print any seeds selected, and code to enable rerunning with that same
seed, so you can reproduce bugs.
With "--x-initial fast",
is best for performance, and initializes all variables to a state
Verilator determines is optimal. This may allow further code

30
test_regress/t/t_alw_split_rst.v
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@ -6,9 +6,9 @@
module t (/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
input clk;
integer cyc = 0;
@ -44,26 +44,23 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x rstn=%x\n", $time, cyc, crc, result, rstn);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
else if (cyc < 10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h77979747fd1b3a5a
`define EXPECTED_SUM 64'h77979747fd86e9fd
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
@ -75,11 +72,11 @@ endmodule
module Test
(/*AUTOARG*/
// Outputs
ff_out, fg_out, fh_out,
// Inputs
clk, clken, rstn, in
);
// Outputs
ff_out, fg_out, fh_out,
// Inputs
clk, clken, rstn, in
);
input clk;
input clken;
@ -98,6 +95,7 @@ module Test
ff_11 <= 0;
ff_12 <= 0;
ff_13 <= 0;
ff_out <= 0;
end
else begin
ff_10 <= in;
@ -120,6 +118,7 @@ module Test
fg_11 <= 0;
fg_12 <= 0;
fg_13 <= 0;
fg_out <= 0;
end
else begin
fg_10 <= in;
@ -142,6 +141,7 @@ module Test
fh_11 <= 0;
fh_12 <= 0;
fh_13 <= 0;
fh_out <= 0;
end
else begin
if (clken) begin

2
test_regress/t/t_clk_vecgen1.py
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@ -14,6 +14,6 @@ test.top_filename = "t/t_clk_vecgen1.v"
test.compile(v_flags2=['+define+T_TEST1'])
test.execute()
test.execute(all_run_flags=["+verilator+rand+reset+0"])
test.passes()

2
test_regress/t/t_clocking_inout.v
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@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
module t;
logic clk = 0, foo = 0, bar = 0;
bit clk = 0, foo = 0, bar = 0;
always #5 clk = ~clk;

8
test_regress/t/t_clocking_xref.v
View File

@ -5,8 +5,8 @@
// SPDX-License-Identifier: CC0-1.0
module mod;
logic clk = 1'b0;
logic inp = 1'b0;
bit clk = 1'b0;
bit inp = 1'b0;
clocking cb @(posedge clk);
input #3 inp;
endclocking
@ -15,8 +15,8 @@ module mod;
endmodule
module main;
logic clk = 1'b0;
logic inp = 1'b0;
bit clk = 1'b0;
bit inp = 1'b0;
always begin
#2
if (t.mod1.cb.inp != 1'b0) $stop;

81
test_regress/t/t_dpi_accessors.cpp
View File

@ -45,9 +45,10 @@ static void logRegHex(int clk, const char* desc, int bitWidth, int val, const ch
}
// Convenience function to check we got an expected result. Silent on success.
static void checkResult(bool p, const char* msg_fail) {
if (!p) vl_fatal(__FILE__, __LINE__, "dut", msg_fail);
}
#define CHECK_RESULT(p, msg_fail) \
do { \
if (!(p)) vl_fatal(__FILE__, __LINE__, "dut", (msg_fail)); \
} while (0)
// Main function instantiates the model and steps through the test.
int main() {
@ -91,9 +92,9 @@ int main() {
std::cout << std::endl;
#endif
checkResult((0 == a) && (0x00 == b) && (0x20 == mem32) && (1 == c) && (0xff == d)
&& (0x00 == e) && (0x00 == f),
"Bad initial DPI values.");
CHECK_RESULT((0 == a) && (0x00 == b) && (0x20 == mem32) && (1 == c) && (0xff == d)
&& (0x00 == e) && (0x00 == f),
"Bad initial DPI values.");
// Initialize the clock
dut->clk = 0;
@ -117,9 +118,9 @@ int main() {
#endif
// On a posedge, a should toggle, on a negedge it should stay the
// same.
checkResult(((dut->clk == 1) && (a_after == (1 - a)))
|| ((dut->clk == 0) && (a_after == a)),
"Test of scalar register reading failed.");
CHECK_RESULT(((dut->clk == 1) && (a_after == (1 - a)))
|| ((dut->clk == 0) && (a_after == a)),
"Test of scalar register reading failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -140,9 +141,9 @@ int main() {
int b_after = (int)b_read();
logRegHex(dut->clk, "read b", 8, b_after, " (after clk)");
// b should increment on a posedge and stay the same on a negedge.
checkResult(((dut->clk == 1) && (b_after == (b + 1)))
|| ((dut->clk == 0) && (b_after == b)),
"Test of vector register reading failed.");
CHECK_RESULT(((dut->clk == 1) && (b_after == (b + 1)))
|| ((dut->clk == 0) && (b_after == b)),
"Test of vector register reading failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -166,7 +167,7 @@ int main() {
// In this case, the value never changes. But we should check it is
// what we expect (0x20).
checkResult(mem32 == 0x20, "Test of array element reading failed.");
CHECK_RESULT(mem32 == 0x20, "Test of array element reading failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -195,7 +196,7 @@ int main() {
// Verilator, that means that it will only change value when "a"
// changes on the posedge of a clock. That is "c" always holds the
// inverse of the "after clock" value of "a".
checkResult(c == (1 - a), "Test of scalar wire reading failed.");
CHECK_RESULT(c == (1 - a), "Test of scalar wire reading failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -225,7 +226,7 @@ int main() {
// but in Verilator, that means that it will only change value when
// "b" changes on the posedge of a clock. That is "d" always holds
// the inverse of the "after clock" value of "b".
checkResult(d == ((~b) & 0xff), "Test of vector wire reading failed.");
CHECK_RESULT(d == ((~b) & 0xff), "Test of vector wire reading failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -252,9 +253,9 @@ int main() {
// On a posedge clock, the value of a that is written should toggle,
// on a negedge, it should not.
checkResult(((dut->clk == 1) && (a_after == (1 - a)))
|| ((dut->clk == 0) && (a_after == a)),
"Test of scalar register writing failed.");
CHECK_RESULT(((dut->clk == 1) && (a_after == (1 - a)))
|| ((dut->clk == 0) && (a_after == a)),
"Test of scalar register writing failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -281,9 +282,9 @@ int main() {
// The value of "b" written should increment on a posedge and stay the
// same on a negedge.
checkResult(((dut->clk == 1) && (b_after == (b + 1)))
|| ((dut->clk == 0) && (b_after == b)),
"Test of vector register writing failed.");
CHECK_RESULT(((dut->clk == 1) && (b_after == (b + 1)))
|| ((dut->clk == 0) && (b_after == b)),
"Test of vector register writing failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -312,7 +313,7 @@ int main() {
// happen if this part of the test coincided with the 32nd element
// being overwritten, which it does not. Check that the value after
// the clock is the same as before the clock.
checkResult(mem32_after == mem32, "Test of array element writing failed.");
CHECK_RESULT(mem32_after == mem32, "Test of array element writing failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -339,7 +340,7 @@ int main() {
logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (after clk)");
// The slice of "b" should always be the bottom 4 bits of "b"
checkResult(b_slice == (b & 0x0f), "Test of vector register slice reading failed.");
CHECK_RESULT(b_slice == (b & 0x0f), "Test of vector register slice reading failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -367,8 +368,8 @@ int main() {
// The slice of "mem32" should always be the concatenation of the top
// 2 and bottom 3 bits of "mem32"
checkResult(mem32_slice == (((mem32 & 0xc0) >> 3) | (mem32 & 0x07)),
"Test of array element slice reading failed.");
CHECK_RESULT(mem32_slice == (((mem32 & 0xc0) >> 3) | (mem32 & 0x07)),
"Test of array element slice reading failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -399,7 +400,7 @@ int main() {
logRegHex(dut->clk, "read d [6:1]", 6, d_slice, " (after clk)");
// The slice of "d" should always be the middle 6 bits of "d".
checkResult(d_slice == ((d & 0x7e) >> 1), "Test of vector wire slice reading failed.");
CHECK_RESULT(d_slice == ((d & 0x7e) >> 1), "Test of vector wire slice reading failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -431,7 +432,7 @@ int main() {
// We must test that when we wrote the slice of "b", we only wrote the
// correct bits. The slice of b is b[3:0]
int b_new = (b & 0xf0) | (b_slice & 0x0f);
checkResult(b_after == b_new, "Test of vector register slice writing failed.");
CHECK_RESULT(b_after == b_new, "Test of vector register slice writing failed.");
dut->eval();
@ -470,7 +471,7 @@ int main() {
// We must test that when we wrote the slice of "mem32", we only wrote
// the correct bits. The slice of "mem32" is {mem32[7:6], mem32[2:0]}.
int mem32_new = (mem32 & 0x38) | ((mem32_slice & 0x18) << 3) | (mem32_slice & 0x7);
checkResult(mem32_after == mem32_new, "Test of vector register slice writing failed.");
CHECK_RESULT(mem32_after == mem32_new, "Test of vector register slice writing failed.");
dut->eval();
@ -482,8 +483,8 @@ int main() {
// We have already tested that array element writing works, so we just
// check that the slice of "mem32" after the clock is the
// concatenation of the top 2 and bottom 3 bits of "mem32"
checkResult(mem32_slice == (((mem32 & 0xc0) >> 3) | (mem32 & 0x07)),
"Test of array element slice writing failed.");
CHECK_RESULT(mem32_slice == (((mem32 & 0xc0) >> 3) | (mem32 & 0x07)),
"Test of array element slice writing failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -522,10 +523,10 @@ int main() {
// and wires works. So we just need to check that l1 reads back as the
// correct combination of bits after the clock. It should be the 15
// bits: {b[3:0],mem[32][7:6],e[6:1],mem[32][2:0]}.
checkResult(l1
== ((((b & 0x0f) >> 0) << 11) | (((mem32 & 0xc0) >> 6) << 9)
| (((e & 0x7e) >> 1) << 3) | (((mem32 & 0x07) >> 0) << 0)),
"Test of complex register reading l1 failed.");
CHECK_RESULT(l1
== ((((b & 0x0f) >> 0) << 11) | (((mem32 & 0xc0) >> 6) << 9)
| (((e & 0x7e) >> 1) << 3) | (((mem32 & 0x07) >> 0) << 0)),
"Test of complex register reading l1 failed.");
}
#ifdef TEST_VERBOSE
@ -562,8 +563,8 @@ int main() {
// and wires works. So we just need to check that l1 reads back as the
// correct combination of bits after the clock. It should be the 8
// bits: {e[7:4], f[3:0]}.
checkResult(l2 == ((e & 0xf0) | (f & 0x0f)),
"Test of complex register reading l2 failed.");
CHECK_RESULT(l2 == ((e & 0xf0) | (f & 0x0f)),
"Test of complex register reading l2 failed.");
}
checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
@ -605,8 +606,8 @@ int main() {
int b_new = (b & 0xf0) | ((l1 & 0x7800) >> 11);
int mem32_new = (mem32 & 0x38) | ((l1 & 0x0600) >> 3) | (l1 & 0x0007);
int e_new = (e & 0x81) | ((l1 & 0x01f8) >> 2);
checkResult((b_new == b_after) && (mem32_new == mem32_after) && (e_new == e_after),
"Test of complex register writing l1 failed.");
CHECK_RESULT((b_new == b_after) && (mem32_new == mem32_after) && (e_new == e_after),
"Test of complex register writing l1 failed.");
dut->eval();
@ -650,8 +651,8 @@ int main() {
// bits: {e[5:2], f[5:2]}
int e_new = (e & 0xc3) | ((l2 & 0xf0) >> 2);
int f_new = (f & 0xc3) | ((l2 & 0x0f) << 2);
checkResult((e_new == e_after) && (f_new == f_after),
"Test of complex register writing l2 failed.");
CHECK_RESULT((e_new == e_after) && (f_new == f_after),
"Test of complex register writing l2 failed.");
dut->eval();

2
test_regress/t/t_dpi_shortcircuit.v
View File

@ -28,7 +28,7 @@ module t (/*AUTOARG*/);
integer i;
integer j;
bit b;
integer errors;
int errors;
task check1(integer line, bit got, bit ex);
if (got != ex) begin

2
test_regress/t/t_dpi_shortcircuit2.v
View File

@ -29,7 +29,7 @@ module t (/*AUTOARG*/);
integer j;
integer k;
bit b;
integer errors;
int errors;
task check1(integer line, bit got, bit ex);
if (got != ex) begin

2
test_regress/t/t_event_control_scope_var.v
View File

@ -11,7 +11,7 @@ module test_mod(input reg clk, input reg reset, output integer result);
endmodule
module Dut(input clk);
integer num;
int num;
integer result1;
integer result2;
reg reset1;

4
test_regress/t/t_for_count.v
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@ -51,7 +51,7 @@ module t (/*AUTOARG*/
end
// While loop
integer w;
int w;
initial begin
while (w<10) w=w+1;
if (w!=10) $stop;
@ -61,7 +61,7 @@ module t (/*AUTOARG*/
end
// Do-While loop
integer dw;
int dw;
initial begin
do dw=dw+1; while (dw<10);
if (dw!=10) $stop;

2
test_regress/t/t_func_check.v
View File

@ -35,7 +35,7 @@ endmodule
module chk (input clk, input rst_l, input expr);
integer errors; initial errors = 0;
int errors;
task printerr;
input [8*64:1] msg;

8
test_regress/t/t_interface_array.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
interface foo_intf;
logic a;
bit a;
modport source (
output a
@ -29,9 +29,9 @@ module t (/*AUTOARG*/
localparam N = 5;
logic [N-1:0] a_in;
logic [N-1:0] a_out;
logic [N-1:0] ack_out;
bit [N-1:0] a_in;
bit [N-1:0] a_out;
bit [N-1:0] ack_out;
foo_intf foos [N-1:0] ();

12
test_regress/t/t_mem_multi_io.v
View File

@ -21,6 +21,7 @@ module t (/*AUTOARG*/
initial begin
for (int i = 0; i < 8; i++) begin
arr[i] = 0;
arri[i] = 0;
end
end
@ -29,10 +30,12 @@ module t (/*AUTOARG*/
if (cyc == 5 && arri[1] != 8) begin
$stop;
end
for (int i = 0; i < 7; ++i) begin
arr[i+1] <= arr[i];
if (cyc >= 2) begin
for (int i = 0; i < 7; ++i) begin
arr[i+1] <= arr[i];
end
arr[0] <= arr[0] + 1;
end
arr[0] <= arr[0] + 1;
end
endmodule : t
@ -47,7 +50,8 @@ module has_array (
always @(posedge clk) begin
cyc <= cyc + 1;
if (arri[0] == 10 && cyc == 10) begin
if (cyc == 10) begin
if (arri[0] != 8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end

4
test_regress/t/t_mem_slot.v
View File

@ -13,9 +13,9 @@ module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal);
input BitToChange;
input BitVal;
input [1:0] SlotToReturn;
output reg [1:0] OutputVal;
output bit [1:0] OutputVal;
reg [1:0] Array[2:0];
bit [1:0] Array[2:0];
always @(posedge Clk)
begin

1
test_regress/t/t_mod_interface_array0.v
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@ -49,6 +49,7 @@ module t
intf_sink sink(a_out, tl_intf);
initial a_in = '0;
initial ack_out = '0;
always @(posedge clk) begin
a_in <= a_in + { {N-1 {1'b0}}, 1'b1 };
ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 };

1
test_regress/t/t_mod_interface_array1.v
View File

@ -51,6 +51,7 @@ module t
intf_sink sink(a_out, tl_intf);
initial a_in = '0;
initial ack_out = '0;
always @(posedge clk) begin
a_in <= a_in + { {N-1 {1'b0}}, 1'b1 };
ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 };

1
test_regress/t/t_mod_interface_array2.v
View File

@ -50,6 +50,7 @@ module t
intf_sink sink(a_out, tl_intf);
initial a_in = '0;
initial ack_out = '0;
always @(posedge clk) begin
a_in <= a_in + { {N-1 {1'b0}}, 1'b1 };
ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 };

2
test_regress/t/t_nba_mixed_update_clocked.v
View File

@ -22,7 +22,7 @@ module t (/*AUTOARG*/
reg y0 = 1'b0;
reg y1 = 1'b0;
// 'z[0]' should equal '{8{x[0]}', 'z[1]' should equal '{8{x[1]}}'
reg [1:0][7:0] z;
reg [1:0][7:0] z = '{default: 0};
// 'pair.a' should equal 'x[0]', 'pair.b' should equal 'x[1]'
struct {
logic a;

14
test_regress/t/t_nba_mixed_update_comb.v
View File

@ -8,16 +8,16 @@
`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0)
module t (/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
input clk;
reg [31:0] cyc = 0;
reg [31:0] sameAsCycButCantBeOptimized_0;
reg [31:0] sameAsCycButCantBeOptimized_1;
reg [31:0] sameAsCycButCantBeOptimized_2;
reg [31:0] sameAsCycButCantBeOptimized_0 = '0;
reg [31:0] sameAsCycButCantBeOptimized_1 = '0;
reg [31:0] sameAsCycButCantBeOptimized_2 = '0;
// 'x' has both blocking and non-blocking update, with the blocking
// update in **combinational** logic
@ -27,7 +27,7 @@ module t (/*AUTOARG*/
reg y1 = 1'b0;
// 'z[0]' should equal '{8{x[0]}', 'z[1]' should equal '{8{x[1]}}'
// verilator lint_off BLKANDNBLK
reg [1:0][7:0] z;
bit [1:0][7:0] z;
// verilator lint_on BLKANDNBLK
// 'pair.a' should equal 'x[0]', 'pair.b' should equal 'x[1]'
// verilator lint_off BLKANDNBLK

1
test_regress/t/t_nba_shared_flag_reuse.v
View File

@ -52,6 +52,7 @@ module t;
always @(posedge clk) begin
if (reset) begin
r_valid <= 0;
addr[0] <= '0;
end
else begin
if (r_valid) begin

4
test_regress/t/t_opt_const.v
View File

@ -255,6 +255,10 @@ endmodule
// Of course the correct result is ^d[38:0] = ^d
module bug3470(input wire clk, input wire [31:0] in, output wire out);
logic [38:0] d;
initial d = 0;
initial tmp = 0;
initial expected = 0;
always_ff @(posedge clk)
d <= {d[6:0], in};

0
test_regress/t/t_const_no_opt.py → test_regress/t/t_opt_const_no_opt.py
View File

10
test_regress/t/t_order_dpi_export_2.v
View File

@ -8,12 +8,12 @@
module testbench(
/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
input clk; // Top level input clock
logic other_clk; // Dependent clock set via DPI
bit other_clk; // Dependent clock set via DPI
export "DPI-C" function set_other_clk;
function void set_other_clk(bit val);
@ -30,7 +30,7 @@ module testbench(
int n = 0;
always @(posedge other_clk) begin
$display("t=%t n=%d", $time, n);
$display("[%0t] n=%0d", $time, n);
if ($time != (4*n+1) * 500) $stop;
if (n == 20) begin
$write("*-* All Finished *-*\n");

12
test_regress/t/t_order_dpi_export_3.v
View File

@ -8,13 +8,13 @@
module testbench(
/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
input clk; // Top level input clock
logic other_clk; // Dependent clock set via DPI
logic third_clk; // Additional dependent clock set via DPI
bit other_clk; // Dependent clock set via DPI
bit third_clk; // Additional dependent clock set via DPI
export "DPI-C" function set_other_clk;
function void set_other_clk(bit val);
@ -43,7 +43,7 @@ module testbench(
int n = 0;
always @(posedge third_clk) begin
$display("t=%d n=%d", $time, n);
$display("[%0t] n=%0d", $time, n);
if ($time != (8*n+1) * 500) $stop;
if (n == 20) begin
$write("*-* All Finished *-*\n");

12
test_regress/t/t_order_dpi_export_4.v
View File

@ -8,13 +8,13 @@
module testbench(
/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
input clk; // Top level input clock
logic other_clk; // Dependent clock set via DPI
logic third_clk; // Additional dependent clock set via DPI
bit other_clk; // Dependent clock set via DPI
bit third_clk; // Additional dependent clock set via DPI
export "DPI-C" function set_other_clk;
function void set_other_clk(bit val);
@ -45,7 +45,7 @@ module testbench(
wire final_clk = $c1("1") & third_clk;
always @(posedge final_clk) begin
$display("t=%d n=%d", $time, n);
$display("[%0t] n=%0d", $time, n);
if ($time != (8*n+1) * 500) $stop;
if (n == 20) begin
$write("*-* All Finished *-*\n");

10
test_regress/t/t_order_dpi_export_6.v
View File

@ -8,12 +8,12 @@
module testbench(
/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
input clk; // Top level input clock
logic other_clk; // Dependent clock set via DPI
bit other_clk; // Dependent clock set via DPI
export "DPI-C" function set_other_clk;
function void set_other_clk(bit val);
@ -36,7 +36,7 @@ module testbench(
// above is committed, as setting clocks via the set_other_clk uses
// blocking assignment.
if (even_other !== current_even_other) $stop;
$display("t=%t n=%d", $time, n);
$display("[%0t] n=%0d", $time, n);
if ($time != (2*n+1) * 500) $stop;
if (n == 20) begin
$write("*-* All Finished *-*\n");

22
test_regress/t/t_past.v
View File

@ -71,18 +71,20 @@ module Test (/*AUTOARG*/
dly1 <= dly0;
dly2 <= dly1;
dly3 <= dly2;
// $past(expression, ticks, expression, clocking)
// In clock expression
if (dly0 != $past(in)) $stop;
if (dly0 != $past(in,)) $stop;
if (dly1 != $past(in, 2)) $stop;
if (dly1 != $past(in, 2, )) $stop;
if (dly1 != $past(in, 2, , )) $stop;
// $sampled(expression) -> expression
if (in != $sampled(in)) $stop;
if ($time > 40) begin
// $past(expression, ticks, expression, clocking)
// In clock expression
if (dly0 != $past(in)) $stop;
if (dly0 != $past(in,)) $stop;
if (dly1 != $past(in, 2)) $stop;
if (dly1 != $past(in, 2, )) $stop;
if (dly1 != $past(in, 2, , )) $stop;
// $sampled(expression) -> expression
if (in != $sampled(in)) $stop;
end
end
assert property (@(posedge clk) dly0 == $past(in));
assert property (@(posedge clk) $time < 40 || dly0 == $past(in));
endmodule

12
test_regress/t/t_past_funcs.v
View File

@ -48,9 +48,9 @@ module Test (/*AUTOARG*/
input clk;
input [31:0] in;
reg [31:0] dly0 = 0;
reg [31:0] dly1 = 0;
reg [31:0] dly2 = 0;
bit [31:0] dly0 = 0;
bit [31:0] dly1 = 0;
bit [31:0] dly2 = 0;
// If called in an assertion, sequence, or property, the appropriate clocking event.
// Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit.
@ -107,9 +107,9 @@ module Test2 (/*AUTOARG*/
input clk;
input [31:0] in;
reg [31:0] dly0 = 0;
reg [31:0] dly1 = 0;
reg [31:0] dly2 = 0;
bit [31:0] dly0 = 0;
bit [31:0] dly1 = 0;
bit [31:0] dly2 = 0;
always @(posedge clk) begin
dly0 <= in;

2
test_regress/t/t_property_named.v
View File

@ -43,7 +43,7 @@ module t (/*AUTOARG*/
assert property(check(0, 1))
else begin
// Assertion should pass
$display("Assert failed, but shouldn't");
$display("[%0t] Assert failed, but shouldn't", $time);
$stop;
end
assert property(check(1, 1))

2
test_regress/t/t_property_untyped.v
View File

@ -25,7 +25,7 @@ module t (/*AUTOARG*/
assert property(check(0, 5'b11111))
else begin
// Assertion should pass
$display("Assert failed, but shouldn't");
$display("[%0t] Assert failed, but shouldn't", $time);
$stop;
end

10
test_regress/t/t_protect_ids.v
View File

@ -10,9 +10,9 @@ interface secret_intf();
endinterface
module t (/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
input clk;
secret_sub secret_inst (.*);
@ -30,7 +30,7 @@ module secret_sub
integer secret_field_r;
} secret_st;
integer secret_cyc;
int secret_cyc;
real secret_cyc_r;
integer secret_o;
real secret_r;
@ -63,7 +63,7 @@ module secret_other
(
input clk);
integer secret_cyc;
int secret_cyc;
always @ (posedge clk) begin
secret_cyc <= secret_cyc + 1;

10
test_regress/t/t_queue.v
View File

@ -10,18 +10,18 @@
`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
input clk;
integer cyc = 0;
integer i;
typedef integer q_t[$];
typedef int q_t[$];
function void set_val(ref integer lhs, input integer rhs);
function void set_val(ref int lhs, input int rhs);
lhs = rhs;
endfunction

2
test_regress/t/t_savable.v
View File

@ -35,7 +35,7 @@ module sub (/*AUTOARG*/
reg [127:0] save128;
reg [47:0] save48;
reg [1:0] save2;
reg [255:0] cycdone; // Make sure each cycle executes exactly once
bit [255:0] cycdone; // Make sure each cycle executes exactly once
reg [31:0] vec[2:1][2:1];
reg [2:1][2:1][31:0] pvec;
real r;

2
test_regress/t/t_threads_counter.v
View File

@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc;
int cyc;
always @ (posedge clk) begin
cyc <= cyc + 1;

2
test_regress/t/t_threads_crazy.v
View File

@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc;
int cyc;
always @ (posedge clk) begin
cyc <= cyc + 1;

6
test_regress/t/t_timing_always.v
View File

@ -11,11 +11,11 @@
`endif
module t;
logic clk = 0;
bit clk = 0;
always #3 clk = ~clk;
logic flag_a;
logic flag_b;
bit flag_a;
bit flag_b;
always @(posedge clk)
begin
`WRITE_VERBOSE(("[%0t] b <= 0\n", $time));

4
test_regress/t/t_timing_fork_comb.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
module t;
logic clk = 0;
bit clk;
assign #5 clk = ~clk;
@ -28,7 +28,7 @@ module t;
c = a + b;
end
logic[5:0] v;
bit [5:0] v;
always @a begin
v[0] = a[0];
fork

2
test_regress/t/t_timing_nested_assignment_on_lhs.py
View File

@ -14,6 +14,6 @@ test.top_filename = "t/t_net_delay.v"
test.compile(timing_loop=True, verilator_flags2=["--timing"])
test.execute()
test.execute(all_run_flags=["+verilator+rand+reset+0"])
test.passes()

6
test_regress/t/t_timing_sched_if.v
View File

@ -5,14 +5,14 @@
// SPDX-License-Identifier: CC0-1.0
module t;
logic clk1 = 0;
bit clk1 = 0;
assign #3 clk1 = ~clk1;
logic clk2 = 0;
bit clk2 = 0;
assign #11 clk2 = ~clk2;
logic flag = 0;
bit flag = 0;
int a1 = 0;
int b1 = 0;
int c1 = 0;

4
test_regress/t/t_timing_sched_nba.v
View File

@ -5,11 +5,11 @@
// SPDX-License-Identifier: CC0-1.0
module t;
logic clk1 = 0;
bit clk1 = 0;
assign #3 clk1 = ~clk1;
logic clk2 = 0;
bit clk2 = 0;
assign #11 clk2 = ~clk2;
int a1 = 0;

2
test_regress/t/t_tri_dangle.py
View File

@ -13,6 +13,6 @@ test.scenarios('simulator')
test.compile()
test.execute()
test.execute(all_run_flags=['+verilator+rand+reset+0'])
test.passes()

1
test_regress/t/t_tri_dangle.v
View File

@ -30,5 +30,6 @@ module sub (/*AUTOARG*/
inout AVDD;
inout AVSS;
tri NON_IO;
// +verilator+rand+reset+0 so z will read as zero
initial if (NON_IO !== 'z) $stop;
endmodule

8
test_regress/t/t_unpacked_slice_range.v
View File

@ -35,10 +35,10 @@ module t2 #(parameter ORIGIN = 0) (input wire clk, input int c);
localparam FULL_HI = ORIGIN + WIDTH - 1;
localparam PART_LO = FULL_LO + OFFSET;
localparam PART_HI = FULL_HI;
logic unpack_sig0 [FULL_LO:FULL_HI];
logic unpack_sig1 [PART_LO:PART_HI];
logic unpack_sig2 [FULL_HI:FULL_LO];
logic unpack_sig3 [PART_HI:PART_LO];
bit unpack_sig0 [FULL_LO:FULL_HI];
bit unpack_sig1 [PART_LO:PART_HI];
bit unpack_sig2 [FULL_HI:FULL_LO];
bit unpack_sig3 [PART_HI:PART_LO];
initial $display("%m ORIGIN:%d [%d:%d] [%d:%d]", ORIGIN, FULL_LO, FULL_HI, PART_LO, PART_HI);
always @(posedge clk) begin

2
test_regress/t/t_unpacked_struct_eq.py
View File

@ -11,7 +11,7 @@ import vltest_bootstrap
test.scenarios('simulator')
test.compile()
test.compile(verilator_flags2=['--binary'])
test.execute()

9
test_regress/t/t_unpacked_struct_eq.v
View File

@ -18,14 +18,14 @@
module t;
typedef struct{
logic [31:0] subarr[4];
bit [31:0] subarr[4];
} arr_str_t;
typedef struct {
string txt;
struct {
logic m0;
logic [3:0] m1;
logic [7:0] arr[2][3];
bit m0;
bit [3:0] m1;
bit [7:0] arr[2][3];
arr_str_t str[5];
} sub;
} struct_t;
@ -56,6 +56,7 @@ module t;
assign s3.sub.arr[1][2] = 8'h06;
initial begin
#1;
if(s3 == s1) $stop;
if(s1 == s2 && s3 != s1) begin
$write("*-* All Finished *-*\n");

2
test_regress/t/t_verilated_all.v
View File

@ -16,7 +16,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc;
int cyc;
integer rand_result;
integer seed = 123;

5
test_regress/t/t_vpi_escape.cpp
View File

@ -403,8 +403,11 @@ int main(int argc, char** argv) {
tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
#endif
topp->eval();
topp->a = 0;
topp->clk = 0;
topp->b__02ec = 0;
topp->eval();
main_time += 10;
while (vl_time_stamp64() < sim_time && !contextp->gotFinish()) {

4
test_regress/t/t_vpi_var.cpp
View File

@ -1031,8 +1031,10 @@ int main(int argc, char** argv) {
tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
#endif
topp->eval();
topp->clk = 0;
topp->a = 0;
topp->eval();
main_time += 10;
while (vl_time_stamp64() < sim_time && !contextp->gotFinish()) {

2
test_regress/t/t_vpi_var.v
View File

@ -40,7 +40,7 @@ extern "C" int mon_check();
// verilator lint_on ASCRANGE
reg [31:0] count /*verilator public_flat */;
reg [31:0] half_count /*verilator public_flat_rd */;
reg [31:0] half_count /*verilator public_flat_rd */ = 0;
reg [31:0] delayed /*verilator public_flat_rw */;
reg [31:0] delayed_mem [16] /*verilator public_flat_rw */;

2
test_regress/t/t_vpi_var2.v
View File

@ -53,7 +53,7 @@ extern "C" int mon_check();
/*verilator public_flat_on*/
reg [31:0] count;
reg [31:0] half_count;
reg [31:0] half_count = 0;
/*verilator public_off*/
/*verilator public_flat_rw_on*/
reg [31:0] delayed;