Add check for missing 'parameter' on implicit types

src/verilog.y

@@ -1485,6 +1485,7 @@ paramPortDeclOrArg<nodep>:      // IEEE: param_assignment + parameter_port_decla
                 paramPortDeclOrArgSub                   { $$ = $1; }
         |       vlTag                                   { $$ = nullptr; }
         ;
+
 paramPortDeclOrArgSub<nodep>:
                 parameter_port_declarationFrontE param_assignment       { $$ = $2; }
         |       parameter_port_declarationTypeFrontE type_assignment    { $$ = $2; }
@@ -1945,7 +1946,12 @@ parameter_port_declarationFrontE: // IEEE: local_ or parameter_port_declaration
                         { /*VARRESET-in-varParam*/
                           // Keep previous type to handle subsequent declarations.
                           // This rule is also used when the previous parameter is a type parameter
-                        }
+                          if ($1) $1->v3error("parameter port declarations require 'parameter'"
+                                              " keyword before implicit data types"
+                                              " (IEEE 1800-2023 6.20.1/A.2.1.1)\n"
+                                              + $1->warnMore()
+                                              + "... Suggest add 'parameter' before here");
+                       }
         |       data_type                               { /*VARRESET-in-varParam*/ VARDTYPE($1); }
         ;
 

test_regress/t/t_param_implicit_bad.out

@@ -0,0 +1,14 @@
+%Error: t/t_param_implicit_bad.v:9:15: parameter port declarations require 'parameter' keyword before implicit data types (IEEE 1800-2023 6.20.1/A.2.1.1)
+                                     : ... Suggest add 'parameter' before here
+    9 | module sub1 #([7:0] PAR1 = 1);   
+      |               ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_param_implicit_bad.v:12:42: parameter port declarations require 'parameter' keyword before implicit data types (IEEE 1800-2023 6.20.1/A.2.1.1)
+                                      : ... Suggest add 'parameter' before here
+   12 | module sub2 #(parameter real PAR1 = 1.0, signed PAR2 = 2);
+      |                                          ^~~~~~
+%Error: t/t_param_implicit_bad.v:15:43: parameter port declarations require 'parameter' keyword before implicit data types (IEEE 1800-2023 6.20.1/A.2.1.1)
+                                      : ... Suggest add 'parameter' before here
+   15 | module sub3 #(localparam real PAR1 = 1.0, signed PAR2 = 2);
+      |                                           ^~~~~~
+%Error: Exiting due to

test_regress/t/t_param_implicit_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_param_implicit_bad.v

@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// IEEE parameter_port_declaration has data_type but not data_type_or_implicit
+
+module sub1 #([7:0] PAR1 = 1);  // <--- Error: requires 'parameter'
+endmodule
+
+module sub2 #(parameter real PAR1 = 1.0, signed PAR2 = 2);
+endmodule
+
+module sub3 #(localparam real PAR1 = 1.0, signed PAR2 = 2);
+endmodule
+
+module t;
+  sub1 sub1();
+  sub2 sub2();
+  sub3 sub3();
+  initial $stop;
+endmodule