Fix fork crash with no init, test for (#4471)
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@ -218,10 +218,12 @@ private:
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beginp->stmtsp()->addNext(instAsgnp);
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beginp->stmtsp()->addNext(forkp);
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forkp->initsp()->foreach([forkp](AstAssign* asgnp) {
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asgnp->unlinkFrBack();
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forkp->addHereThisAsNext(asgnp);
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});
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if (forkp->initsp()) {
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forkp->initsp()->foreach([forkp](AstAssign* asgnp) {
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asgnp->unlinkFrBack();
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forkp->addHereThisAsNext(asgnp);
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});
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}
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UASSERT_OBJ(!forkp->initsp(), forkp, "Leftover nodes in block_item_declaration");
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m_modp->addStmtsp(m_instance.m_classp);
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@ -0,0 +1,26 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2023 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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verilator_flags2 => ["--exe --main --timing"],
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make_main => 0,
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# bug#4471 - remove this
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verilator_make_gmake => 0,
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);
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#bug#4471 - add this
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#execute(
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# check_finished => 1,
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# );
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ok(1);
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1;
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@ -0,0 +1,15 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t();
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initial fork
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reg i;
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i = 1'b1;
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if (i != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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join
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endmodule
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