Remove support for parameterized UDPs (#4518)
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@ -1346,16 +1346,15 @@ module_declaration: // ==IEEE: module_declaration
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GRAMMARP->m_modp = nullptr;
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SYMP->popScope($1);
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GRAMMARP->endLabel($<fl>7, $1, $7); }
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| udpFront parameter_port_listE portsStarE ';'
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| udpFront portsStarE ';'
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/*cont*/ module_itemListE yENDPRIMITIVE endLabelE
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{ $1->modTrace(false); // Stash for implicit wires, etc
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if ($2) $1->addStmtsp($2);
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if ($3) $1->addStmtsp($3);
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if ($5) $1->addStmtsp($5);
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if ($4) $1->addStmtsp($4);
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GRAMMARP->m_tracingParse = true;
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GRAMMARP->m_modp = nullptr;
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SYMP->popScope($1);
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GRAMMARP->endLabel($<fl>7, $1, $7); }
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GRAMMARP->endLabel($<fl>6, $1, $6); }
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//
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| yEXTERN modFront parameter_port_listE portsStarE ';'
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{ BBUNSUP($<fl>1, "Unsupported: extern module"); }
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@ -0,0 +1,7 @@
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%Error: t/t_udp_param_bad.v:12:15: syntax error, unexpected '#', expecting ';'
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12 | primitive udp #(
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| ^
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%Error: t/t_udp_param_bad.v:14:1: syntax error, unexpected ')', expecting ';'
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14 | ) (o, a);
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| ^
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%Error: Exiting due to
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@ -0,0 +1,19 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(linter => 1);
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lint(
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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@ -0,0 +1,22 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Anthony Donlon.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire a, b;
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udp i_udp (a, b);
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endmodule
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primitive udp #(
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parameter A = 1
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) (o, a);
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output o;
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input a;
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table
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//o a
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0 : 1;
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1 : 0;
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endtable
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endprimitive
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