SC variables can only be assigned whole, so do not split up concatenation assignments in V3FuncOpt. Fixes #6329
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@ -228,6 +228,8 @@ class FuncOptVisitor final : public VNVisitor {
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UASSERT_OBJ(lhsp->width() == rhsp->width(), nodep, "Inconsistent assignment");
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// Only consider pure assignments. Nodes inserted below are safe.
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if (!nodep->user1() && (!lhsp->isPure() || !rhsp->isPure())) return false;
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// Do not split assignments to SC variables, they cannot be assigned in parts
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if (lhsp->exists([](AstVarRef* refp) { return refp->varp()->isSc(); })) return false;
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// Check for a Sel on the LHS if present, and skip over it
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uint32_t lsb = 0;
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if (AstSel* const selp = VN_CAST(lhsp, Sel)) {
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@ -11,7 +11,8 @@ import vltest_bootstrap
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test.scenarios('vlt')
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test.compile(verilator_flags2=["--stats"])
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test.compile(
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verilator_flags2=["--stats", "--build", "--gate-stmts", "10000", "--expand-limit", "128"])
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test.file_grep(test.stats, r'Optimizations, FuncOpt concat trees balanced\s+(\d+)', 1)
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test.file_grep(test.stats, r'Optimizations, FuncOpt concat splits\s+(\d+)', 62)
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@ -0,0 +1,23 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.top_filename = "t/t_balance_cats.v"
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test.compile(verilator_flags2=[
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"--stats", "--build", "--gate-stmts", "10000", "--expand-limit", "128", "--sc"
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])
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test.file_grep(test.stats, r'Optimizations, FuncOpt concat trees balanced\s+(\d+)', 1)
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test.file_grep(test.stats, r'Optimizations, FuncOpt concat splits\s+(\d+)', 0)
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test.passes()
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