Fix assignment of null into struct member (#4952).
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@ -23,11 +23,12 @@ Verilator 5.023 devel
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* Support public packed struct / union (#860) (#4878). [Kefa Chen]
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* Change installation to be relocatable (#4927). [Geza Lore]
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* Fix __Vlip undefined error in --freloop (#4824). [Justin Yao Du]
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* Fix invalid cast on string structure creation (#4921). [esynr3z]
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* Fix invalid cast on string structure creation (#4921).
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* Fix try-lock spuriously fails (#4931) (#4938). [Kamil Rakoczy]
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* Fix V3Unknown unpacked struct x-assign (#4934). [Yan Xu]
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* Fix DFG removing forceable signals (#4942). [Geza Lore]
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* Fix null characters in shortened identifiers (#4946). [Abdul Hameed]
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* Fix assignment of null into struct member (#4952).
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Verilator 5.022 2024-02-24
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@ -82,7 +82,8 @@ class CastVisitor final : public VNVisitor {
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}
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void ensureCast(AstNodeExpr* nodep) {
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if (castSize(nodep->backp()) != castSize(nodep) || !nodep->user1()) {
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insertCast(nodep, castSize(nodep->backp()));
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const AstConst* const constp = VN_CAST(nodep, Const);
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if (!(constp && constp->num().isNull())) insertCast(nodep, castSize(nodep->backp()));
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}
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}
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void ensureLower32Cast(AstCCast* nodep) {
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@ -201,7 +202,7 @@ class CastVisitor final : public VNVisitor {
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// Constants are of unknown size if smaller than 33 bits, because
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// we're too lazy to wrap every constant in the universe in
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// ((IData)#).
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nodep->user1(nodep->isQuad() || nodep->isWide());
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nodep->user1(nodep->isQuad() || nodep->isWide() || nodep->num().isNull());
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}
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// Null dereference protection
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@ -0,0 +1,20 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2020 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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);
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ok(1);
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1;
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@ -0,0 +1,39 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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endclass : Cls
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typedef struct {
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Cls obj;
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int number;
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} str_t;
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module t (/*AUTOARG*/);
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function automatic str_t func_null();
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return '{null, 42};
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endfunction
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function automatic str_t func_obj();
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Cls c;
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c = new;
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return '{c, 43};
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endfunction
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initial begin
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str_t result;
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result = func_null();
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if (result.obj != null) $stop;
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if (result.number != 42) $stop;
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result = func_obj();
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if (result.obj == null) $stop;
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if (result.number != 43) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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