Internals: Do not astgen useless Dfg vertex subtypes
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@ -50,38 +50,11 @@ DfgArraySel* makeVertex<DfgArraySel, AstArraySel>(const AstArraySel* nodep, DfgG
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// Some earlier passes create malformed ArraySels, just bail on those...
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// See t_bitsel_wire_array_bad
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if (VN_IS(nodep->fromp(), Const)) return nullptr;
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AstUnpackArrayDType* const fromDtypep
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= VN_CAST(nodep->fromp()->dtypep()->skipRefp(), UnpackArrayDType);
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if (!fromDtypep) return nullptr;
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if (!VN_IS(nodep->fromp()->dtypep()->skipRefp(), UnpackArrayDType)) return nullptr;
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return new DfgArraySel{dfg, nodep->fileline(), DfgVertex::dtypeFor(nodep)};
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}
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//======================================================================
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// Currently unhandled nodes
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// LCOV_EXCL_START
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// AstCCast changes width, but should not exists where DFG optimization is currently invoked
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template <>
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DfgCCast* makeVertex<DfgCCast, AstCCast>(const AstCCast*, DfgGraph&) {
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return nullptr;
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}
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// Unhandled in DfgToAst, but also operates on strings which we don't optimize anyway
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template <>
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DfgAtoN* makeVertex<DfgAtoN, AstAtoN>(const AstAtoN*, DfgGraph&) {
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return nullptr;
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}
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// Unhandled in DfgToAst, but also operates on strings which we don't optimize anyway
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template <>
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DfgCompareNN* makeVertex<DfgCompareNN, AstCompareNN>(const AstCompareNN*, DfgGraph&) {
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return nullptr;
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}
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// Unhandled in DfgToAst, but also operates on unpacked arrays which we don't optimize anyway
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template <>
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DfgSliceSel* makeVertex<DfgSliceSel, AstSliceSel>(const AstSliceSel*, DfgGraph&) {
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return nullptr;
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}
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// LCOV_EXCL_STOP
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} // namespace
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} //namespace
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// Visitor that can convert combinational Ast logic constructs/assignments to Dfg
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template <bool T_Scoped>
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@ -52,15 +52,6 @@ T_Node* makeNode(const T_Vertex* vtxp, Ops... ops) {
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//======================================================================
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// Vertices needing special conversion
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template <>
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AstCountOnes* makeNode<AstCountOnes, DfgCountOnes, AstNodeExpr*>( //
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const DfgCountOnes* vtxp, AstNodeExpr* op1) {
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AstCountOnes* const nodep = new AstCountOnes{vtxp->fileline(), op1};
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// Set dtype same as V3Width
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nodep->dtypeSetLogicSized(32, VSigning::UNSIGNED);
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return nodep;
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}
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template <>
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AstExtend* makeNode<AstExtend, DfgExtend, AstNodeExpr*>( //
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const DfgExtend* vtxp, AstNodeExpr* op1) {
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@ -91,38 +82,6 @@ AstShiftRS* makeNode<AstShiftRS, DfgShiftRS, AstNodeExpr*, AstNodeExpr*>( //
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return new AstShiftRS{vtxp->fileline(), op1, op2, static_cast<int>(vtxp->width())};
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}
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//======================================================================
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// Currently unhandled nodes - see corresponding AstToDfg functions
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// LCOV_EXCL_START
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template <>
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AstCCast* makeNode<AstCCast, DfgCCast, AstNodeExpr*>(const DfgCCast* vtxp, AstNodeExpr*) {
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vtxp->v3fatalSrc("not implemented");
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VL_UNREACHABLE;
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return nullptr; // LCOV_EXCL_LINE
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}
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template <>
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AstAtoN* makeNode<AstAtoN, DfgAtoN, AstNodeExpr*>(const DfgAtoN* vtxp, AstNodeExpr*) {
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vtxp->v3fatalSrc("not implemented");
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VL_UNREACHABLE;
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return nullptr; // LCOV_EXCL_LINE
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}
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template <>
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AstCompareNN*
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makeNode<AstCompareNN, DfgCompareNN, AstNodeExpr*, AstNodeExpr*>(const DfgCompareNN* vtxp,
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AstNodeExpr*, AstNodeExpr*) {
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vtxp->v3fatalSrc("not implemented");
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VL_UNREACHABLE;
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return nullptr; // LCOV_EXCL_LINE
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}
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template <>
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AstSliceSel* makeNode<AstSliceSel, DfgSliceSel, AstNodeExpr*, AstNodeExpr*, AstNodeExpr*>(
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const DfgSliceSel* vtxp, AstNodeExpr*, AstNodeExpr*, AstNodeExpr*) {
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vtxp->v3fatalSrc("not implemented");
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VL_UNREACHABLE;
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return nullptr; // LCOV_EXCL_LINE
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}
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// LCOV_EXCL_STOP
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} // namespace
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template <bool T_Scoped>
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@ -79,15 +79,11 @@ using BitwiseToReduction = typename BitwiseToReductionImpl<T_Reduction>::type;
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namespace {
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template<typename Vertex> void foldOp(V3Number& out, const V3Number& src);
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template <> void foldOp<DfgCLog2> (V3Number& out, const V3Number& src) { out.opCLog2(src); }
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template <> void foldOp<DfgCountOnes> (V3Number& out, const V3Number& src) { out.opCountOnes(src); }
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template <> void foldOp<DfgExtend> (V3Number& out, const V3Number& src) { out.opAssign(src); }
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template <> void foldOp<DfgExtendS> (V3Number& out, const V3Number& src) { out.opExtendS(src, src.width()); }
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template <> void foldOp<DfgLogNot> (V3Number& out, const V3Number& src) { out.opLogNot(src); }
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template <> void foldOp<DfgNegate> (V3Number& out, const V3Number& src) { out.opNegate(src); }
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template <> void foldOp<DfgNot> (V3Number& out, const V3Number& src) { out.opNot(src); }
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template <> void foldOp<DfgOneHot> (V3Number& out, const V3Number& src) { out.opOneHot(src); }
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template <> void foldOp<DfgOneHot0> (V3Number& out, const V3Number& src) { out.opOneHot0(src); }
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template <> void foldOp<DfgRedAnd> (V3Number& out, const V3Number& src) { out.opRedAnd(src); }
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template <> void foldOp<DfgRedOr> (V3Number& out, const V3Number& src) { out.opRedOr(src); }
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template <> void foldOp<DfgRedXor> (V3Number& out, const V3Number& src) { out.opRedXor(src); }
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@ -665,14 +661,6 @@ class V3DfgPeephole final : public DfgVisitor {
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// DfgVertexUnary
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//=========================================================================
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void visit(DfgCLog2* vtxp) override {
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if (foldUnary(vtxp)) return;
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}
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void visit(DfgCountOnes* vtxp) override {
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if (foldUnary(vtxp)) return;
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}
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void visit(DfgExtend* vtxp) override {
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UASSERT_OBJ(vtxp->width() > vtxp->srcp()->width(), vtxp, "Invalid zero extend");
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@ -768,14 +756,6 @@ class V3DfgPeephole final : public DfgVisitor {
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}
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}
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void visit(DfgOneHot* vtxp) override {
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if (foldUnary(vtxp)) return;
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}
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void visit(DfgOneHot0* vtxp) override {
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if (foldUnary(vtxp)) return;
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}
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void visit(DfgRedOr* vtxp) override {
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if (optimizeReduction(vtxp)) return;
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}
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114
src/astgen
114
src/astgen
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@ -1356,6 +1356,116 @@ DfgVertices["Vertex"].addSubClass(DfgVertices["VertexTernary"])
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DfgVertices["VertexVariadic"] = Node("VertexVariadic", DfgVertices["Vertex"])
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DfgVertices["Vertex"].addSubClass(DfgVertices["VertexVariadic"])
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# AstNodeExpr that are not representable in Dfg
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DfgIgnored = (
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# Floating point operations
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"AcosD",
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"AcoshD",
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"AddD",
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"AsinD",
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"AsinhD",
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"Atan2D",
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"AtanD",
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"AtanhD",
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"BitsToRealD",
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"CeilD",
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"CosD",
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"CoshD",
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"DivD",
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"EqD",
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"ExpD",
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"FloorD",
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"GtD",
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"GteD",
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"HypotD",
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"ISToRD",
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"IToRD",
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"Log10D",
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"LogD",
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"LtD",
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"LteD",
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"MulD",
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"NegateD",
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"NeqD",
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"PowD",
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"RealToBits",
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"RToIRoundS",
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"RToIS",
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"SinD",
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"SinhD",
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"SqrtD",
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"SubD",
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"TanD",
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"TanhD",
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# String operations
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"AtoN",
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"CompareNN",
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"ConcatN",
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"CvtPackString",
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"EqN",
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"GetcN",
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"GetcRefN",
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"GteN",
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"GtN",
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"LenN",
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"LteN",
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"LtN",
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"NeqN",
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"NToI",
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"PutcN",
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"ReplicateN",
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"SubstrN",
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"ToLowerN",
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"ToUpperN",
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# Effectful
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"PostAdd",
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"PostSub",
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"PreAdd",
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"PreSub",
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# Only used after DFG
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"ShiftLOvr",
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"ShiftROvr",
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"ShiftRSOvr",
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"WordSel",
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# File operations
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"FEof",
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"FGetC",
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"FGetS",
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"FUngetC",
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# Dynamic array operations
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"AssocSel",
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"IsUnbounded",
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"WildcardSel",
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# Type comparison
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"EqT",
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"NeqT",
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# Distributions
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"DistChiSquare",
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"DistErlang",
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"DistExponential",
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"DistNormal",
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"DistPoisson",
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"DistT",
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"DistUniform",
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# Specials
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"CastDynamic",
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"CastWrap",
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"CAwait",
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"CCast",
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"CLog2",
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"CountOnes",
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"IsUnknown",
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"NullCheck",
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"OneHot",
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"OneHot0",
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"ResizeLValue",
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"Signed",
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"SliceSel",
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"TimeImport",
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"Unsigned",
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"URandomRange",
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)
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# Read DfgVertex definitions
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for filename in Args.dfgdef:
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read_types(os.path.join(Args.I, filename), DfgVertices, "Dfg")
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@ -1370,6 +1480,10 @@ for node in AstNodeList:
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if node.name in DfgVertices:
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continue
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# Ignore expressions types that DFG cannot handle
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if node.name in DfgIgnored:
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continue
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if node.isSubClassOf(AstNodes["NodeUniop"]):
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base = DfgVertices["VertexUnary"]
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elif node.isSubClassOf(AstNodes["NodeBiop"]):
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@ -1,16 +0,0 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.compile()
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test.passes()
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@ -1,12 +0,0 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module v(input logic t);
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endmodule
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module top(input logic [2:0] c);
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v v1((int'(c) + int'($countones(c))) > 2);
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endmodule
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@ -43,14 +43,9 @@ module t (
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array[2][7:4] = rand_a[7:4];
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end
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`signal(FOLD_UNARY_CLog2, $clog2(const_a));
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`signal(FOLD_UNARY_CountOnes, $countones(const_a));
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`signal(FOLD_UNARY_IsUnknown, $isunknown(const_a));
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`signal(FOLD_UNARY_LogNot, !const_a[0]);
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`signal(FOLD_UNARY_Negate, -const_a);
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`signal(FOLD_UNARY_Not, ~const_a);
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`signal(FOLD_UNARY_OneHot, $onehot(const_a));
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`signal(FOLD_UNARY_OneHot0, $onehot0(const_a));
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`signal(FOLD_UNARY_RedAnd, &const_a);
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`signal(FOLD_UNARY_RedOr, |const_a);
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`signal(FOLD_UNARY_RedXor, ^const_a);
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@ -1,19 +0,0 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.compile(verilator_flags2=["--stats"])
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test.file_grep(test.stats,
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r'Optimizations, DFG pre inline AstToDfg, non-representable \(impure\)\s+(\d+)', 1)
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test.passes()
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@ -1,16 +0,0 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input wire clk,
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output wire [31:0] o0
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);
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int file;
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assign o0 = $fgetc(file); // Impure
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endmodule
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