mirror of
https://github.com/verilator/verilator.git
synced 2026-10-02 16:13:34 +02:00
Internals: Use LogOr/LogAnd on inside operator expansion (#4951)
This will help introducing constrained randomization, as SMT solvers treat booleans and 1-bit vectors as incompatible types.
This commit is contained in:
+1
-1
@@ -319,7 +319,7 @@ AstNodeExpr* AstInsideRange::newAndFromInside(AstNodeExpr* exprp, AstNodeExpr* l
|
||||
AstNodeExpr* const bp = new AstLte{fileline(), exprp->cloneTreePure(true), rhsp};
|
||||
ap->fileline()->modifyWarnOff(V3ErrorCode::UNSIGNED, true);
|
||||
bp->fileline()->modifyWarnOff(V3ErrorCode::CMPCONST, true);
|
||||
return new AstAnd{fileline(), ap, bp};
|
||||
return new AstLogAnd{fileline(), ap, bp};
|
||||
}
|
||||
|
||||
AstConst* AstConst::parseParamLiteral(FileLine* fl, const string& literal) {
|
||||
|
||||
+1
-1
@@ -2572,7 +2572,7 @@ class WidthVisitor final : public VNVisitor {
|
||||
itemp->unlinkFrBack());
|
||||
}
|
||||
if (newp) {
|
||||
newp = new AstOr{nodep->fileline(), newp, inewp};
|
||||
newp = new AstLogOr{nodep->fileline(), newp, inewp};
|
||||
} else {
|
||||
newp = inewp;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user