Fix dynamic cast purity (#6267)
Signed-off-by: Igor Zaworski <izaworski@internships.antmicro.com>
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@ -2465,7 +2465,7 @@ public:
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bool sizeMattersLhs() const override { return false; }
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bool sizeMattersRhs() const override { return false; }
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int instrCount() const override { return widthInstrs() * 20; }
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bool isPure() override { return true; }
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bool isPure() override { return false; }
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};
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class AstCompareNN final : public AstNodeBiop {
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// Verilog str.compare() and str.icompare()
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,33 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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typedef class Derived;
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class Base;
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function Derived cast();
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if ($cast(cast,this)) begin end
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endfunction
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endclass
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class Derived extends Base;
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string x;
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function new(string xval);
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x = xval;
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endfunction
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function string get();
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return x;
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endfunction
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endclass
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module t;
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initial begin
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Derived d = new("Hello");
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Base b = d;
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Derived c = b.cast();
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if (d.get() != c.get()) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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