Fix race in t_interface_virtual_sched_ico

test_regress/t/t_interface_virtual_sched_ico.cpp

@@ -23,13 +23,23 @@ int main(int argc, char** argv) {
     srand48(5);
 
     const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX};
-    topp->inc = 1;
     topp->clk = false;
+    topp->inc1 = 1;
+    topp->eval();
+    topp->inc2 = 1;
     topp->eval();
 
+    bool flop = true;
     while (!contextp->gotFinish() && contextp->time() < 100000) {
         contextp->timeInc(5);
-        if (topp->clk) topp->inc += 1;
+        if (topp->clk) {
+            if (flop) {
+                topp->inc1 += 1;
+            } else {
+                topp->inc2 += 1;
+            }
+            flop = !flop;
+        }
         topp->clk = !topp->clk;
         topp->eval();
     }

test_regress/t/t_interface_virtual_sched_ico.out

@@ -1,25 +1,43 @@
 [0] intf1.inc==0
 [0] vif2.inc==0
 [0] intf1.inc==1
-[0] vif2.inc==1
+[0] vif2.inc==0
+[0] intf1.inc==1
+[0] vif2.inc==0
 [0] intf1.inc==1
 [0] vif2.inc==1
 [5] intf1.inc==1
 [5] vif2.inc==1
 [10] intf1.inc==2
-[10] vif2.inc==2
+[10] vif2.inc==1
 [15] intf1.inc==2
-[15] vif2.inc==2
-[20] intf1.inc==3
-[20] vif2.inc==3
-[25] intf1.inc==3
-[25] vif2.inc==3
-[30] intf1.inc==4
-[30] vif2.inc==4
-[35] intf1.inc==4
-[35] vif2.inc==4
-[40] intf1.inc==5
-[40] vif2.inc==5
-[45] intf1.inc==5
-[45] vif2.inc==5
+[15] vif2.inc==1
+[20] intf1.inc==2
+[20] vif2.inc==2
+[25] intf1.inc==2
+[25] vif2.inc==2
+[30] intf1.inc==3
+[30] vif2.inc==2
+[35] intf1.inc==3
+[35] vif2.inc==2
+[40] intf1.inc==3
+[40] vif2.inc==3
+[45] intf1.inc==3
+[45] vif2.inc==3
+[50] intf1.inc==4
+[50] vif2.inc==3
+[55] intf1.inc==4
+[55] vif2.inc==3
+[60] intf1.inc==4
+[60] vif2.inc==4
+[65] intf1.inc==4
+[65] vif2.inc==4
+[70] intf1.inc==5
+[70] vif2.inc==4
+[75] intf1.inc==5
+[75] vif2.inc==4
+[80] intf1.inc==5
+[80] vif2.inc==5
+[85] intf1.inc==5
+[85] vif2.inc==5
 *-* All Finished *-*

test_regress/t/t_interface_virtual_sched_ico.v

@@ -10,11 +10,13 @@ endinterface
 
 module top (
     clk,
-    inc
+    inc1,
+    inc2
 );
 
   input clk;
-  input [31:0] inc;
+  input [31:0] inc1;
+  input [31:0] inc2;
   int cyc = 0;
 
   If intf1();
@@ -22,12 +24,12 @@ module top (
   virtual If vif1 = intf1;
   virtual If vif2 = intf2;
 
-  assign vif1.inc  = inc;
-  assign intf2.inc = inc;
+  assign vif1.inc  = inc1;
+  assign intf2.inc = inc2;
 
   always @(posedge clk) begin
     cyc <= cyc + 1;
-    if (cyc >= 4) begin
+    if (cyc >= 8) begin
       $write("*-* All Finished *-*\n");
       $finish;
     end