parent
72b4a74245
commit
a948be184c
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@ -88,6 +88,7 @@ Josh Redford
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Julian Daube
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Julie Schwartz
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Julien Margetts
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Justin Thiel
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Kaleb Barrett
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Kamil Rakoczy
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Kanad Kanhere
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@ -0,0 +1,5 @@
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*-* All Finished *-*
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top.t.intf: symbolsPerBeat 16, symbolsPerBeatDivBy2 8, mismatch 0
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top.t.theCore.core_intf: symbolsPerBeat 64, symbolsPerBeatDivBy2 8, mismatch 1
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%Error: t/t_interface_localparam_unsup.v:23: Verilog $stop
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Aborting...
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@ -0,0 +1,23 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2023 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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fails => $Self->{vlt_all},
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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@ -0,0 +1,51 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Justin Thiel.
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// SPDX-License-Identifier: CC0-1.0
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interface SimpleIntf
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#(
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parameter int symbolsPerBeat = 16
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)
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();
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// This value is calculated incorrectly for other instances of
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// this interface when it is accessed via the HDL for any other
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// instance of this interface
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localparam int symbolsPerBeatDivBy2 = symbolsPerBeat/2;
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localparam bit mismatch = (symbolsPerBeat != (2*symbolsPerBeatDivBy2) );
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initial begin
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$write("%m: symbolsPerBeat %0d, symbolsPerBeatDivBy2 %0d, mismatch %0d\n",
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symbolsPerBeat, symbolsPerBeatDivBy2, mismatch);
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if (mismatch) $stop;
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end
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endinterface
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module Core(
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SimpleIntf intf
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);
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// NOTE: When this line is commented out the test will pass
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localparam intf_symbolsPerBeatDivBy2 = intf.symbolsPerBeatDivBy2;
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localparam int core_intf_symbolsPerBeat = 64;
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SimpleIntf #(.symbolsPerBeat(core_intf_symbolsPerBeat)) core_intf ();
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endmodule
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module t();
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SimpleIntf intf();
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Core theCore (.intf);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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