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Support generic interfaces (#6272)

This commit is contained in:
Igor Zaworski 2025-08-22 12:44:35 +02:00 committed by GitHub
parent b19215770b
commit b95a974ff1
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GPG Key ID: B5690EEEBB952194
94 changed files with 1813 additions and 68 deletions
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1
src/V3Ast.cpp
View File

@ -73,6 +73,7 @@ bool VFwdType::isNodeCompatible(const AstNode* nodep) const {
case VFwdType::UNION: return VN_IS(defp, UnionDType); break;
case VFwdType::INTERFACE_CLASS: // FALLTHRU // TODO: Over permissive for now
case VFwdType::CLASS: return VN_IS(defp, ClassRefDType) || VN_IS(defp, Class); break;
case VFwdType::GENERIC_INTERFACE: return VN_IS(defp, IfaceRefDType); break;
default: v3fatalSrc("Bad case");
}
VL_UNREACHABLE;

4
src/V3Ast.h
View File

@ -288,11 +288,11 @@ public:
class VFwdType final {
public:
enum en : uint8_t { NONE, ENUM, STRUCT, UNION, CLASS, INTERFACE_CLASS };
enum en : uint8_t { NONE, ENUM, STRUCT, UNION, CLASS, INTERFACE_CLASS, GENERIC_INTERFACE };
enum en m_e;
const char* ascii() const {
static const char* const names[]
= {"none", "enum", "struct", "union", "class", "interface class"};
= {"none", "enum", "struct", "union", "class", "interface class", "generic interface"};
return names[m_e];
}
VFwdType()

36
src/V3AstNodeDType.h
View File

@ -845,6 +845,40 @@ public:
const TableMap& tableMap() const { return m_tableMap; }
};
class AstIfaceGenericDType final : public AstNodeDType {
// Generic interface that will be replaced with AstIfaceRefDType
FileLine* m_modportFileline; // Where modport token was
string m_modportName; // "" = no modport
public:
explicit AstIfaceGenericDType(FileLine* fl)
: ASTGEN_SUPER_IfaceGenericDType(fl) {
dtypep(this);
}
AstIfaceGenericDType(FileLine* fl, FileLine* modportFl, const string& modport)
: ASTGEN_SUPER_IfaceGenericDType(fl)
, m_modportFileline{modportFl}
, m_modportName{modport} {
dtypep(this);
}
ASTGEN_MEMBERS_AstIfaceGenericDType;
void dumpSmall(std::ostream& str) const override;
bool hasDType() const override VL_MT_SAFE { return true; }
bool maybePointedTo() const override VL_MT_SAFE { return true; }
bool undead() const override { return true; }
AstNodeDType* subDTypep() const override VL_MT_STABLE { return nullptr; }
AstNodeDType* virtRefDTypep() const override { return nullptr; }
void virtRefDTypep(AstNodeDType* nodep) override {}
bool similarDTypeNode(const AstNodeDType* samep) const override { return this == samep; }
AstBasicDType* basicp() const override VL_MT_STABLE { return nullptr; }
int widthAlignBytes() const override { return 1; }
int widthTotalBytes() const override { return 1; }
string modportName() const { return m_modportName; }
bool isModport() { return !m_modportName.empty(); }
bool isCompound() const override { return true; }
FileLine* modportFileline() const { return m_modportFileline; }
string name() const override { return m_modportName; }
};
class AstIfaceRefDType final : public AstNodeDType {
// Reference to an interface, either for a port, or inside parent cell
// @astgen op1 := paramsp : List[AstPin]
@ -898,11 +932,13 @@ public:
if (flag) v3Global.setHasVirtIfaces();
}
FileLine* modportFileline() const { return m_modportFileline; }
void modportFileline(FileLine* const modportFileline) { m_modportFileline = modportFileline; }
string cellName() const { return m_cellName; }
void cellName(const string& name) { m_cellName = name; }
string ifaceName() const { return m_ifaceName; }
string ifaceNameQ() const { return "'" + prettyName(ifaceName()) + "'"; }
void ifaceName(const string& name) { m_ifaceName = name; }
void modportName(const string& modportName) { m_modportName = modportName; }
string modportName() const { return m_modportName; }
AstIface* ifaceViaCellp() const; // Use cellp or ifacep
AstIface* ifacep() const { return m_ifacep; }

4
src/V3AstNodeOther.h
View File

@ -2545,6 +2545,8 @@ class AstModule final : public AstNodeModule {
// A module declaration
const bool m_isChecker; // Module represents a checker
const bool m_isProgram; // Module represents a program
bool m_hasGenericIface = false; // Module contains a generic interface
public:
class Checker {}; // for constructor type-overload selection
class Program {}; // for constructor type-overload selection
@ -2567,6 +2569,8 @@ public:
bool timescaleMatters() const override { return true; }
bool isChecker() const { return m_isChecker; }
bool isProgram() const { return m_isProgram; }
bool hasGenericIface() const { return m_hasGenericIface; }
void hasGenericIface(bool hasGenericIface) { m_hasGenericIface = hasGenericIface; }
void dump(std::ostream& str) const override;
void dumpJson(std::ostream& str) const override;
};

6
src/V3AstNodes.cpp
View File

@ -2105,10 +2105,12 @@ void AstModule::dump(std::ostream& str) const {
this->AstNodeModule::dump(str);
if (isChecker()) str << " [CHECKER]";
if (isProgram()) str << " [PROGRAM]";
if (hasGenericIface()) str << " [HASGENERICIFACE]";
}
void AstModule::dumpJson(std::ostream& str) const {
dumpJsonBoolFunc(str, isChecker);
dumpJsonBoolFunc(str, isProgram);
dumpJsonBoolFunc(str, hasGenericIface);
dumpJsonGen(str);
}
void AstPin::dump(std::ostream& str) const {
@ -2557,6 +2559,10 @@ void AstVoidDType::dumpSmall(std::ostream& str) const {
this->AstNodeDType::dumpSmall(str);
str << "void";
}
void AstIfaceGenericDType::dumpSmall(std::ostream& str) const {
this->AstNodeDType::dumpSmall(str);
str << "generic_interface";
}
void AstStreamDType::dumpSmall(std::ostream& str) const {
this->AstNodeDType::dumpSmall(str);
str << "stream";

142
src/V3LinkDot.cpp
View File

@ -2415,6 +2415,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
int m_indent = 0; // Indentation (tree depth) for debug
bool m_inSens = false; // True if in senitem
bool m_inWith = false; // True if in with
bool m_genericIfaceModule = false; // True if in module containing generic interface
std::map<std::string, AstNode*> m_ifClassImpNames; // Names imported from interface class
std::set<AstClass*> m_extendsParam; // Classes that have a parameterized super class
// (except the default instances)
@ -2434,6 +2435,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
bool m_super; // Starts with super reference
bool m_unresolvedCell; // Unresolved cell, needs help from V3Param
bool m_unresolvedClass; // Unresolved class reference, needs help from V3Param
bool m_unresolvedGenericIface; // Unresolved generic interface, needs help from V3Param
bool m_genBlk; // Contains gen block reference
AstNode* m_unlinkedScopep; // Unresolved scope, needs corresponding VarXRef
AstDisable* m_disablep; // Disable statement under which the reference is
@ -2450,6 +2452,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
m_dotText = "";
m_unresolvedCell = false;
m_unresolvedClass = false;
m_unresolvedGenericIface = false;
m_genBlk = false;
m_unlinkedScopep = nullptr;
m_disablep = nullptr;
@ -2467,6 +2470,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
if (m_super) sstr << " [super]";
if (m_unresolvedCell) sstr << " [unrCell]";
if (m_unresolvedClass) sstr << " [unrClass]";
if (m_unresolvedGenericIface) sstr << " [unrGIface]";
if (m_genBlk) sstr << " [genBlk]";
sstr << " txt=" << m_dotText;
return sstr.str();
@ -2745,6 +2749,9 @@ class LinkDotResolveVisitor final : public VNVisitor {
dtypep = adtypep->childDTypep()->skipRefp();
} else if (const AstQueueDType* const adtypep = VN_CAST(dtypep, QueueDType)) {
dtypep = adtypep->childDTypep()->skipRefp();
} else if (const AstUnpackArrayDType* const adtypep
= VN_CAST(dtypep, UnpackArrayDType)) {
dtypep = adtypep->childDTypep()->skipRefp();
} else {
break;
}
@ -2776,6 +2783,81 @@ class LinkDotResolveVisitor final : public VNVisitor {
}
return nullptr;
}
static const AstVar* getNextVarp(const AstNode* stmtsp) {
while (stmtsp) {
if (const AstVar* const varp = VN_CAST(stmtsp, Var)) return varp;
stmtsp = stmtsp->nextp();
}
return nullptr;
}
// Introduce implicit parameters for modules with generic interafeces
void addImplicitParametersOfGenericIface(AstCell* const nodep, const AstModule* const modp) {
// Get Param number
int paramNum = 1;
for (AstPin* paramp = nodep->paramsp(); paramp; paramp = VN_CAST(paramp->nextp(), Pin)) {
++paramNum;
}
// Add each implicit parameter type
const AstVar* modIfaceVarp = getNextVarp(modp->stmtsp());
for (const AstPin* pinp = nodep->pinsp(); pinp && modIfaceVarp;
pinp = VN_CAST(pinp->nextp(), Pin),
modIfaceVarp = getNextVarp(modIfaceVarp->nextp())) {
if (modIfaceVarp->varType() != VVarType::IFACEREF
|| !VN_IS(modIfaceVarp->childDTypep(), IfaceGenericDType)) {
continue;
}
AstNode* exprp = pinp->exprp();
if (!exprp) {
modIfaceVarp->v3error("Interface port "
<< modIfaceVarp->prettyNameQ()
<< " is not connected to interface/modport pin expression");
continue;
}
while (const AstNodePreSel* const preSelp = VN_CAST(exprp, NodePreSel)) {
exprp = preSelp->fromp();
}
if (const AstVarRef* const varRefp = VN_CAST(exprp, VarRef)) {
const AstVar* const varp = varRefp->varp();
if (const AstIfaceRefDType* const refp
= VN_CAST(getElemDTypep(varp->childDTypep()), IfaceRefDType)) {
AstIface* const ifacep = VN_AS(refp->cellp()->modp(), Iface);
AstIfaceRefDType* newIfaceRefp;
if (refp->modportp()) {
newIfaceRefp = new AstIfaceRefDType{
refp->fileline(), refp->modportFileline(), m_modp->name(),
ifacep->name(), refp->modportName()};
} else {
newIfaceRefp = new AstIfaceRefDType{refp->fileline(), m_modp->name(),
ifacep->name()};
}
newIfaceRefp->ifacep(ifacep);
if (refp->cellp()->paramsp()) {
newIfaceRefp->addParamsp(refp->cellp()->paramsp()->cloneTree(true));
}
UASSERT_OBJ(pinp->name().find("__pinNumber") == 0
|| pinp->name() == modIfaceVarp->name(),
pinp, "Not found interface with such name");
AstPin* const newPinp
= new AstPin{pinp->fileline(), paramNum,
"__VGIfaceParam" + modIfaceVarp->name(), newIfaceRefp};
newPinp->param(true);
visit(newPinp);
nodep->addParamsp(newPinp);
} else {
varRefp->v3error("Generic interfaces can only connect to an interface and "
<< varp->prettyNameQ() << " is "
<< (varp->childDTypep()
? "of type " + varp->childDTypep()->prettyDTypeNameQ()
: "not an interface"));
}
} else {
exprp->v3error("Expected an interface but " << exprp->prettyNameQ()
<< " is not an interface");
}
++paramNum;
}
}
#define LINKDOT_VISIT_START() \
VL_RESTORER(m_indent); \
@ -2798,6 +2880,10 @@ class LinkDotResolveVisitor final : public VNVisitor {
if (nodep->dead() || !m_statep->existsNodeSym(nodep)) return;
LINKDOT_VISIT_START();
UINFO(8, indent() << "visit " << nodep);
VL_RESTORER(m_genericIfaceModule);
if (const AstModule* const modp = VN_CAST(nodep, Module)) {
m_genericIfaceModule = modp->hasGenericIface();
}
checkNoDot(nodep);
m_ds.init(m_curSymp);
m_ds.m_dotSymp = m_curSymp = m_modSymp
@ -2854,6 +2940,12 @@ class LinkDotResolveVisitor final : public VNVisitor {
// UINFOTREE(1, nodep, "", "linkcell");
// UINFOTREE(1, nodep->modp(), "", "linkcemd");
iterateChildren(nodep);
if (m_statep->forPrimary())
if (const AstModule* const modp = VN_CAST(nodep->modp(), Module)) {
if (modp->hasGenericIface())
addImplicitParametersOfGenericIface(nodep, modp);
}
}
}
// Parent module inherits child's publicity
@ -2954,6 +3046,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
UINFO(8, indent() << m_ds.ascii());
const DotStates lastStates = m_ds;
const bool start = (m_ds.m_dotPos == DP_NONE); // Save, as m_dotp will be changed
const DotPosition initialDotPos = m_ds.m_dotPos;
VL_RESTORER(m_randSymp);
{
if (start) { // Starting dot sequence
@ -3053,9 +3146,14 @@ class LinkDotResolveVisitor final : public VNVisitor {
UINFO(8, indent() << "iter.ldone " << m_ds.ascii() << " " << nodep);
} else {
m_ds.m_dotPos = DP_FIRST;
m_ds.m_unresolvedGenericIface = false;
UINFO(8, indent() << "iter.lhs " << m_ds.ascii() << " " << nodep);
iterateAndNextNull(nodep->lhsp());
UINFO(8, indent() << "iter.ldone " << m_ds.ascii() << " " << nodep);
if (m_ds.m_unresolvedGenericIface) {
m_ds.m_dotPos = initialDotPos;
return;
}
// UINFOTREE(9, nodep, "", "dot-lho");
}
if (m_statep->forPrimary() && isParamedClassRef(nodep->lhsp())) {
@ -3383,7 +3481,11 @@ class LinkDotResolveVisitor final : public VNVisitor {
} else if (AstVar* const varp = foundToVarp(foundp, nodep, VAccess::READ)) {
AstIfaceRefDType* const ifacerefp
= LinkDotState::ifaceRefFromArray(varp->subDTypep());
if (ifacerefp && varp->isIfaceRef()) {
if (varp->isIfaceRef() && m_genericIfaceModule
&& VN_IS(varp->childDTypep(), IfaceGenericDType)) {
ok = true;
m_ds.m_unresolvedGenericIface = true;
} else if (ifacerefp && varp->isIfaceRef()) {
UASSERT_OBJ(ifacerefp->ifaceViaCellp(), ifacerefp, "Unlinked interface");
// Really this is a scope reference into an interface
UINFO(9, indent() << "varref-ifaceref " << m_ds.m_dotText << " " << nodep);
@ -3787,8 +3889,44 @@ class LinkDotResolveVisitor final : public VNVisitor {
}
dotSymp = m_statep->findDotted(nodep->fileline(), dotSymp, nodep->dotted(), baddot,
okSymp, true); // Maybe nullptr
bool modport = false;
if (const AstVar* varp = VN_CAST(dotSymp->nodep(), Var)) {
if (const AstIfaceRefDType* const ifaceRefp
= VN_CAST(varp->childDTypep(), IfaceRefDType)) {
if (ifaceRefp->modportp()) {
dotSymp = m_statep->getNodeSym(ifaceRefp->modportp());
modport = true;
} else {
dotSymp = m_statep->getNodeSym(ifaceRefp->ifacep());
}
}
}
if (!m_statep->forScopeCreation()) {
VSymEnt* foundp = m_statep->findSymPrefixed(dotSymp, nodep->name(), baddot, true);
VSymEnt* foundp = nullptr;
if (modport) {
// This is a copy of findSymPrefixed with few modifications.
// This searches without a fallback like findSymPrefixed but if lookup fails it
// will check one fallback (fallback of modport shall be interface) and take
// only L and G PARAMs since they should be visible from a modport always.
string prefix = dotSymp->symPrefix();
while (!foundp) {
foundp = dotSymp->findIdFlat(prefix + nodep->name());
if (foundp) break;
UASSERT_OBJ(dotSymp->fallbackp(), nodep, "Modports shall have fallback");
foundp = dotSymp->fallbackp()->findIdFlat(prefix + nodep->name());
if (const AstVar* const varp
= foundToVarp(foundp, nodep, nodep->access())) {
if (!varp->isParam()) foundp = nullptr;
}
if (prefix.empty()) break;
string nextPrefix = LinkDotState::removeLastInlineScope(prefix);
if (prefix == nextPrefix) break;
prefix = std::move(nextPrefix);
}
baddot = nodep->name();
} else {
foundp = m_statep->findSymPrefixed(dotSymp, nodep->name(), baddot, true);
}
if (m_inSens && foundp) {
if (AstClocking* const clockingp = VN_CAST(foundp->nodep(), Clocking)) {
foundp = getCreateClockingEventSymEnt(clockingp);

7
src/V3LinkParse.cpp
View File

@ -64,6 +64,7 @@ class LinkParseVisitor final : public VNVisitor {
bool m_insideLoop = false; // True if the node is inside a loop
bool m_lifetimeAllowed = false; // True to allow lifetime settings
VDouble0 m_statModules; // Number of modules seen
bool m_moduleWithGenericIface = false; // If current module contains generic interface
// METHODS
void cleanFileline(AstNode* nodep) {
@ -345,6 +346,7 @@ class LinkParseVisitor final : public VNVisitor {
VL_DO_DANGLING(nodep->deleteTree(), nodep);
return;
}
m_moduleWithGenericIface |= VN_IS(nodep->childDTypep(), IfaceGenericDType);
// Maybe this variable has a signal attribute
V3Control::applyVarAttr(m_modp, m_ftaskp, nodep);
@ -634,6 +636,7 @@ class LinkParseVisitor final : public VNVisitor {
VL_RESTORER(m_implTypedef);
VL_RESTORER(m_lifetime);
VL_RESTORER(m_lifetimeAllowed);
VL_RESTORER(m_moduleWithGenericIface);
{
// Module: Create sim table for entire module and iterate
cleanFileline(nodep);
@ -648,6 +651,7 @@ class LinkParseVisitor final : public VNVisitor {
m_valueModp = nodep;
m_lifetime = nodep->lifetime();
m_lifetimeAllowed = VN_IS(nodep, Class);
m_moduleWithGenericIface = false;
if (m_lifetime.isNone()) {
m_lifetime = VN_IS(nodep, Class) ? VLifetime::AUTOMATIC : VLifetime::STATIC;
}
@ -657,6 +661,9 @@ class LinkParseVisitor final : public VNVisitor {
"Verilator top-level internals");
}
iterateChildren(nodep);
if (AstModule* const modp = VN_CAST(nodep, Module)) {
modp->hasGenericIface(m_moduleWithGenericIface);
}
}
m_valueModp = nodep;
}

45
src/V3Param.cpp
View File

@ -818,6 +818,7 @@ class ParamProcessor final {
bool& any_overridesr, IfaceRefRefs& ifaceRefRefs) {
for (AstPin* pinp = pinsp; pinp; pinp = VN_AS(pinp->nextp(), Pin)) {
const AstVar* const modvarp = pinp->modVarp();
if (modvarp && VN_IS(modvarp->subDTypep(), IfaceGenericDType)) continue;
if (modvarp->isIfaceRef()) {
AstIfaceRefDType* portIrefp = VN_CAST(modvarp->subDTypep(), IfaceRefDType);
if (!portIrefp && arraySubDTypep(modvarp->subDTypep())) {
@ -888,6 +889,46 @@ class ParamProcessor final {
}
}
// Set interfaces types inside generic modules
// to the corresponding values of implicit parameters
void genericInterfaceVarSetup(const AstPin* const paramsp, const AstPin* const pinsp) {
std::unordered_map<string, const AstPin*> paramspMap;
for (const AstPin* pinp = paramsp; pinp; pinp = VN_AS(pinp->nextp(), Pin)) {
if (VString::startsWith(pinp->name(), "__VGIfaceParam")) {
paramspMap.insert({pinp->name().substr(std::strlen("__VGIfaceParam")), pinp});
}
}
if (paramspMap.empty()) return;
for (const AstNode* nodep = pinsp; nodep; nodep = nodep->nextp()) {
if (const AstPin* const pinp = VN_CAST(nodep, Pin)) {
if (AstVar* const varp = pinp->modVarp()) {
if (AstIfaceGenericDType* const ifaceGDTypep
= VN_CAST(varp->childDTypep(), IfaceGenericDType)) {
const auto iter = paramspMap.find(varp->name());
if (iter == paramspMap.end()) continue;
ifaceGDTypep->unlinkFrBack();
const AstPin* const paramp = iter->second;
paramspMap.erase(iter);
const AstIfaceRefDType* const ifacerefp
= VN_AS(paramp->exprp(), IfaceRefDType);
AstIfaceRefDType* const newIfacerefp = new AstIfaceRefDType{
ifaceGDTypep->fileline(), ifaceGDTypep->modportFileline(),
ifaceGDTypep->name(), ifacerefp->ifaceName(),
ifaceGDTypep->modportName()};
newIfacerefp->ifacep(ifacerefp->ifacep());
varp->childDTypep(newIfacerefp);
VL_DO_DANGLING(m_deleter.pushDeletep(ifaceGDTypep), ifaceGDTypep);
if (paramspMap.empty()) return;
}
}
}
}
UASSERT(paramspMap.empty(), "Not every generic interface implicit param is used");
}
bool nodeDeparamCommon(AstNode* nodep, AstNodeModule*& srcModpr, AstPin* paramsp,
AstPin* pinsp, bool any_overrides) {
// Make sure constification worked
@ -946,7 +987,7 @@ class ParamProcessor final {
nodep->v3error(
"Class parameter type without default value is never given value"
<< " (IEEE 1800-2023 6.20.1): " << dtypep->prettyNameQ());
VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
VL_DO_DANGLING(m_deleter.pushDeletep(nodep->unlinkFrBack()), nodep);
}
}
if (AstVar* const varp = VN_CAST(stmtp, Var)) {
@ -957,6 +998,8 @@ class ParamProcessor final {
}
}
genericInterfaceVarSetup(paramsp, pinsp);
// Delete the parameters from the cell; they're not relevant any longer.
if (paramsp) paramsp->unlinkFrBackWithNext()->deleteTree();
return any_overrides;

25
src/verilog.y
View File

@ -295,6 +295,27 @@ public:
forkp->addInitsp(varp);
}
}
void createGenericIface(AstNode* const nodep, AstNodeRange* const rangep,
AstNode* sigAttrListp, FileLine* const modportFileline = nullptr,
const string& modportstrp = "") {
m_varDecl = VVarType::GPARAM;
m_varIO = VDirection::NONE;
setDType(new AstParseTypeDType{nodep->fileline(), VFwdType::GENERIC_INTERFACE});
m_varDeclTyped = true;
const std::string uniqueName = "__VGIfaceParam" + nodep->name();
AstNode::addNext(nodep,
createVariable(nodep->fileline(), uniqueName, rangep, sigAttrListp));
m_varDecl = VVarType::IFACEREF;
AstIfaceGenericDType* const refdtypep
= new AstIfaceGenericDType{nodep->fileline(), modportFileline, modportstrp};
setDType(refdtypep);
m_varDeclTyped = true;
m_varIO = VDirection::INPUT;
AstNode::addNext(nodep,
createVariable(nodep->fileline(), nodep->name(), rangep, sigAttrListp));
m_varDecl = VVarType::VAR;
}
};
const VBasicDTypeKwd LOGIC = VBasicDTypeKwd::LOGIC; // Shorthand "LOGIC"
@ -1561,9 +1582,9 @@ port<nodep>: // ==IEEE: port
VARDTYPE(dtp); VARIOANSI();
addNextNull($$, VARDONEP($$, $6, $7)); }
| portDirNetE yINTERFACE portSig rangeListE sigAttrListE
{ $$ = nullptr; BBUNSUP($<fl>2, "Unsupported: generic interfaces"); }
{ $$ = $3; GRAMMARP->createGenericIface($3, $4, $5); }
| portDirNetE yINTERFACE '.' idAny/*modport*/ portSig rangeListE sigAttrListE
{ $$ = nullptr; BBUNSUP($<fl>2, "Unsupported: generic interfaces"); }
{ $$ = $5; GRAMMARP->createGenericIface($5, $6, $7, $<fl>4, *$4); }
//
| portDirNetE yINTERCONNECT signingE rangeListE portSig variable_dimensionListE sigAttrListE
{ $$ = $5;

7
test_regress/t/t_class_param_noinit_bad.out
View File

@ -7,5 +7,8 @@
: ... note: In instance 't'
13 | Cls #(1) c;
| ^~~
%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt
%Error: Command Failed
%Error: t/t_class_param_noinit_bad.v:8:32: Parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'T'
: ... note: In instance 't'
8 | class Cls #(int A, int B, type T);
| ^
%Error: Exiting due to

4
test_regress/t/t_constraint_json_only.out
View File

@ -1,6 +1,6 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED",
"modulesp": [
{"type":"MODULE","name":"t","addr":"(F)","loc":"d,67:8,67:9","isChecker":false,"isProgram":false,"origName":"t","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"t","addr":"(F)","loc":"d,67:8,67:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"t","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"p","addr":"(G)","loc":"d,69:11,69:12","dtypep":"(H)","origName":"p","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"VAR","dtypeName":"Packet","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"INITIAL","name":"","addr":"(I)","loc":"d,71:4,71:11","isSuspendable":false,"needProcess":false,
@ -77,7 +77,7 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(SB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(SB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(TB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(SB)","varsp": [],"blocksp": [],"inlinesp": []}
]}

6
test_regress/t/t_dump_json.out
View File

@ -1,6 +1,6 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"(F)","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED",
"modulesp": [
{"type":"MODULE","name":"t","addr":"(G)","loc":"e,7:8,7:9","isChecker":false,"isProgram":false,"origName":"t","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"t","addr":"(G)","loc":"e,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"t","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"PORT","name":"clk","addr":"(H)","loc":"e,9:4,9:7","exprp": []},
{"type":"VAR","name":"clk","addr":"(I)","loc":"e,11:10,11:13","dtypep":"UNLINKED","origName":"clk","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
@ -431,7 +431,7 @@
]}
]}
]},
{"type":"MODULE","name":"Test","addr":"(RB)","loc":"e,66:8,66:12","isChecker":false,"isProgram":false,"origName":"Test","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"Test","addr":"(RB)","loc":"e,66:8,66:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"Test","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"PORT","name":"out","addr":"(AH)","loc":"e,68:4,68:7","exprp": []},
{"type":"PORT","name":"clk","addr":"(BH)","loc":"e,70:4,70:7","exprp": []},
@ -1082,7 +1082,7 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(VQ)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(VQ)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(WQ)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(VQ)","varsp": [],"blocksp": [],"inlinesp": []}
]}

18
test_regress/t/t_interface_generic.py Executable file
View File

@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

33
test_regress/t/t_interface_generic.v Normal file
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@ -0,0 +1,33 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface a, interface b);
initial begin
#1;
if (a.v != 7) $stop;
if (b.k != 9) $stop;
end
endmodule
module t;
inf inf_inst();
inf2 inf_inst2();
GenericModule genericModule (inf_inst, inf_inst2);
initial begin
inf_inst.v = 7;
inf_inst2.k = 9;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic2.py Executable file
View File

@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

35
test_regress/t/t_interface_generic2.v Normal file
View File

@ -0,0 +1,35 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
endinterface
interface inf2;
int k;
endinterface
module GenericModule (logic[31:0] l1, interface a, logic[31:0] l2, interface b);
initial begin
#1;
if (l1 != 87) $stop;
if (a.v != 7) $stop;
if (l2 != 73) $stop;
if (b.k != 9) $stop;
end
endmodule
module t;
inf inf_inst();
inf2 inf_inst2();
GenericModule genericModule (87, inf_inst, 73, inf_inst2);
initial begin
inf_inst.v = 7;
inf_inst2.k = 9;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_array.py Executable file
View File

@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

26
test_regress/t/t_interface_generic_array.v Normal file
View File

@ -0,0 +1,26 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
endinterface
module GenericModule (interface a);
initial begin
#1;
if (a.v != 7) $stop;
end
endmodule
module t;
inf inf_inst[3]();
GenericModule genericModule (inf_inst[2]);
initial begin
inf_inst[2].v = 7;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

13
test_regress/t/t_interface_generic_bad.out Executable file
View File

@ -0,0 +1,13 @@
%Warning-PINMISSING: t/t_interface_generic_bad.v:26:17: Instance has missing pin: 'b'
26 | GenericModule genericModule (inf_inst);
| ^~~~~~~~~~~~~
t/t_interface_generic_bad.v:15:46: ... Location of port declaration
15 | module GenericModule (interface a, interface b);
| ^
... For warning description see https://verilator.org/warn/PINMISSING?v=latest
... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
%Error: t/t_interface_generic_bad.v:15:46: Interface port 'b' is not connected to interface/modport pin expression
15 | module GenericModule (interface a, interface b);
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

16
test_regress/t/t_interface_generic_bad.py Executable file
View File

@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename)
test.passes()

33
test_regress/t/t_interface_generic_bad.v Normal file
View File

@ -0,0 +1,33 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface a, interface b);
initial begin
#1;
if (a.v != 7) $stop;
if (b.k != 9) $stop;
end
endmodule
module t;
inf inf_inst();
inf2 inf_inst2();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;
inf_inst2.k = 9;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

24
test_regress/t/t_interface_generic_bad2.out Executable file
View File

@ -0,0 +1,24 @@
%Error: t/t_interface_generic_bad2.v:15:9: Can't find definition of scope/variable: 'b'
15 | if (b.k != 9) $stop;
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_interface_generic_bad2.v:20:3: Cannot find file containing interface: 'inf'
20 | inf inf_inst();
| ^~~
%Error: t/t_interface_generic_bad2.v:21:32: Found definition of 'inf_inst' as a CELL but expected a variable
21 | GenericModule genericModule (inf_inst);
| ^~~~~~~~
%Error: t/t_interface_generic_bad2.v:21:32: Expected an interface but 'inf_inst' is not an interface
21 | GenericModule genericModule (inf_inst);
| ^~~~~~~~
%Error: t/t_interface_generic_bad2.v:23:5: Dotted reference to instance that refers to missing module/interface: 'inf'
23 | inf_inst.v = 7;
| ^~~~~~~~
%Error: t/t_interface_generic_bad2.v:23:14: Can't find definition of 'v' in dotted variable/method: 'inf_inst.v'
23 | inf_inst.v = 7;
| ^
%Error: t/t_interface_generic_bad2.v:24:5: Can't find definition of scope/variable: 'inf_inst2'
: ... Suggested alternative: 'inf_inst'
24 | inf_inst2.k = 9;
| ^~~~~~~~~
%Error: Exiting due to

16
test_regress/t/t_interface_generic_bad2.py Executable file
View File

@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename)
test.passes()

28
test_regress/t/t_interface_generic_bad2.v Normal file
View File

@ -0,0 +1,28 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
class inf;
int v;
endclass
module GenericModule (interface a);
initial begin
#1;
if (a.v != 7) $stop;
if (b.k != 9) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;
inf_inst2.k = 9;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

9
test_regress/t/t_interface_generic_bad3.out Normal file
View File

@ -0,0 +1,9 @@
%Error: t/t_interface_generic_bad3.v:15:9: Can't find definition of scope/variable: 'b'
15 | if (b.k != 9) $stop;
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error-PINNOTFOUND: t/t_interface_generic_bad3.v:21:42: Pin not found: '__pinNumber2'
21 | GenericModule genericModule (inf_inst, inf_inst);
| ^~~~~~~~
... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest
%Error: Exiting due to

16
test_regress/t/t_interface_generic_bad3.py Executable file
View File

@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename)
test.passes()

27
test_regress/t/t_interface_generic_bad3.v Normal file
View File

@ -0,0 +1,27 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
endinterface
module GenericModule (interface a);
initial begin
#1;
if (a.v != 7) $stop;
if (b.k != 9) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst, inf_inst);
initial begin
inf_inst.v = 7;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

5
test_regress/t/t_interface_generic_bad4.out Normal file
View File

@ -0,0 +1,5 @@
%Error: t/t_interface_generic_bad4.v:26:32: Generic interfaces can only connect to an interface and 'inf_inst' is of type 'int'
26 | GenericModule genericModule (inf_inst, inf_inst2);
| ^~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

16
test_regress/t/t_interface_generic_bad4.py Executable file
View File

@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename)
test.passes()

33
test_regress/t/t_interface_generic_bad4.v Normal file
View File

@ -0,0 +1,33 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface a, interface b);
initial begin
#1;
if (a.v != 7) $stop;
if (b.k != 9) $stop;
end
endmodule
module t;
int inf_inst;
inf2 inf_inst2();
GenericModule genericModule (inf_inst, inf_inst2);
initial begin
inf_inst.v = 7;
inf_inst2.k = 9;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_function.py Executable file
View File

@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

33
test_regress/t/t_interface_generic_function.v Normal file
View File

@ -0,0 +1,33 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
function int get();
return v;
endfunction
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface a);
initial begin
#1;
if (a.get() != 4) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 4;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

7
test_regress/t/t_interface_generic_function_bad.out Executable file
View File

@ -0,0 +1,7 @@
%Error: t/t_interface_generic_function_bad.v:14:11: Can't find definition of 'get' in dotted task/function: 'a.get'
: ... note: In instance 't.genericModule'
14 | if (a.get() != 4) $stop;
| ^~~
... Known scopes under 'get': <no instances found>
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

16
test_regress/t/t_interface_generic_function_bad.py Executable file
View File

@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename)
test.passes()

26
test_regress/t/t_interface_generic_function_bad.v Normal file
View File

@ -0,0 +1,26 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
endinterface
module GenericModule (interface a);
initial begin
#1;
if (a.get() != 4) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 4;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_iface_param.py Executable file
View File

@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

27
test_regress/t/t_interface_generic_iface_param.v Normal file
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@ -0,0 +1,27 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf #(PARAM);
logic[PARAM-1:0] v;
endinterface
module GenericModule (interface a);
initial begin
#1;
if (a.v != 7) $stop;
if (a.PARAM != 13) $stop;
end
endmodule
module t;
inf #(.PARAM(13)) inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_mod_param.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

26
test_regress/t/t_interface_generic_mod_param.v Normal file
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@ -0,0 +1,26 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
endinterface
module GenericModule#(type T, type Y = int) (interface a);
initial begin
#1;
if (a.v != 7) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule #(string) genericModule (inf_inst);
initial begin
inf_inst.v = 7;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_modport.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

29
test_regress/t/t_interface_generic_modport.v Normal file
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@ -0,0 +1,29 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
modport mp (
input v
);
endinterface
module GenericModule (interface.mp a);
initial begin
#1;
if (a.v != 7) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_modport2.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(timing_loop=True, verilator_flags2=['--timing'])
test.execute()
test.passes()

29
test_regress/t/t_interface_generic_modport2.v Normal file
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@ -0,0 +1,29 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
modport mp (
output v
);
endinterface
module GenericModule (interface.mp a);
initial begin
a.v = 7;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
#1;
if (inf_inst.v != 7) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

5
test_regress/t/t_interface_generic_modport_bad.out Executable file
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@ -0,0 +1,5 @@
%Error: t/t_interface_generic_modport_bad.v:11:33: Modport not found under interface 'inf': 'mp'
11 | module GenericModule (interface.mp a);
| ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

16
test_regress/t/t_interface_generic_modport_bad.py Executable file
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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename)
test.passes()

26
test_regress/t/t_interface_generic_modport_bad.v Normal file
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@ -0,0 +1,26 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
endinterface
module GenericModule (interface.mp a);
initial begin
#1;
if (a.v != 7) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

6
test_regress/t/t_interface_generic_modport_bad2.out Executable file
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@ -0,0 +1,6 @@
%Error: t/t_interface_generic_modport_bad2.v:17:7: Attempt to drive input-only modport: 'v'
: ... note: In instance 't.genericModule'
17 | a.v = 10;
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

16
test_regress/t/t_interface_generic_modport_bad2.py Executable file
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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename)
test.passes()

29
test_regress/t/t_interface_generic_modport_bad2.v Normal file
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@ -0,0 +1,29 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
modport mp (
input v
);
endinterface
module GenericModule (interface.mp a);
initial begin
#1;
a.v = 10;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

7
test_regress/t/t_interface_generic_modport_bad3.out Executable file
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@ -0,0 +1,7 @@
%Error: t/t_interface_generic_modport_bad3.v:18:11: Can't find definition of 'v' in dotted signal: 'a.v'
: ... note: In instance 't.genericModule'
18 | if (a.v != 7) $stop;
| ^
... Known scopes under 'v': <no instances found>
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

16
test_regress/t/t_interface_generic_modport_bad3.py Executable file
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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename)
test.passes()

30
test_regress/t/t_interface_generic_modport_bad3.v Normal file
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@ -0,0 +1,30 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
int o;
modport mp (
input o
);
endinterface
module GenericModule (interface.mp a);
initial begin
#1;
if (a.v != 7) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_modport_function.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

36
test_regress/t/t_interface_generic_modport_function.v Normal file
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@ -0,0 +1,36 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
function int get();
return v;
endfunction
modport mp(
import get
);
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface.mp a);
initial begin
#1;
if (a.get() != 4) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 4;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_modport_function2.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(timing_loop=True, verilator_flags2=['--timing'])
test.execute()
test.passes()

36
test_regress/t/t_interface_generic_modport_function2.v Normal file
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@ -0,0 +1,36 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
function int get();
return v;
endfunction
modport mp(
output v
);
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface.mp a);
initial begin
a.v = 5;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
#1;
if(inf_inst.get() != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

7
test_regress/t/t_interface_generic_modport_function_bad.out Executable file
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@ -0,0 +1,7 @@
%Error: t/t_interface_generic_modport_function_bad.v:24:11: Can't find definition of 'get' in dotted task/function: 'a.get'
: ... note: In instance 't.genericModule'
24 | if (a.get() != 4) $stop;
| ^~~
... Known scopes under 'get': <no instances found>
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

16
test_regress/t/t_interface_generic_modport_function_bad.py Executable file
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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(fails=True, expect_filename=test.golden_filename)
test.passes()

36
test_regress/t/t_interface_generic_modport_function_bad.v Normal file
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@ -0,0 +1,36 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
function int get();
return v;
endfunction
modport mp(
input v
);
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface.mp a);
initial begin
#1;
if (a.get() != 4) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 4;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_modport_param.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

32
test_regress/t/t_interface_generic_modport_param.v Normal file
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@ -0,0 +1,32 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
localparam lparam = 12;
int v;
modport mp (
input v
);
endinterface
module GenericModule (interface.mp a);
initial begin
#1;
if (a.lparam != 12) $stop;
if (a.v != 7) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_modport_task.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(timing_loop=True, verilator_flags2=['--timing'])
test.execute()
test.passes()

33
test_regress/t/t_interface_generic_modport_task.v Normal file
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@ -0,0 +1,33 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
task setup();
v = 3;
endtask
modport mp(
input v,
import setup
);
endinterface
module GenericModule (interface.mp a);
initial begin
a.setup();
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
#1;
if (inf_inst.v != 3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_modport_task2.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

32
test_regress/t/t_interface_generic_modport_task2.v Normal file
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@ -0,0 +1,32 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
task setup();
v = 3;
endtask
modport mp(
input v
);
endinterface
module GenericModule (interface.mp a);
initial begin
#1;
if (a.v != 3) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.setup();
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

7
test_regress/t/t_interface_generic_modport_task_bad.out Executable file
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@ -0,0 +1,7 @@
%Error: t/t_interface_generic_modport_task_bad.v:23:7: Can't find definition of 'setup' in dotted task/function: 'a.setup'
: ... note: In instance 't.genericModule'
23 | a.setup();
| ^~~~~
... Known scopes under 'setup': <no instances found>
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

16
test_regress/t/t_interface_generic_modport_task_bad.py Executable file
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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename)
test.passes()

36
test_regress/t/t_interface_generic_modport_task_bad.v Normal file
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@ -0,0 +1,36 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
task setup();
v = 3;
endtask
modport mp(
input v
);
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface.mp a);
initial begin
a.setup();
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
#1;
if (inf_inst.v != 3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_normal.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

30
test_regress/t/t_interface_generic_normal.v Normal file
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@ -0,0 +1,30 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
endinterface
module GenericModule (interface a, inf b, interface c);
initial begin
#1;
if (a.v != 7) $stop;
if (b.v != 8) $stop;
if (c.v != 9) $stop;
end
endmodule
module t;
inf inf_inst[3]();
GenericModule genericModule (inf_inst[0], inf_inst[1], inf_inst[2]);
initial begin
inf_inst[0].v = 7;
inf_inst[1].v = 8;
inf_inst[2].v = 9;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_positional.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

26
test_regress/t/t_interface_generic_positional.v Normal file
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@ -0,0 +1,26 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
endinterface
module GenericModule (interface a, interface b);
initial begin
#1;
if (a.v != 7) $stop;
end
endmodule
module t;
inf inf_inst[3]();
GenericModule genericModule (.a(inf_inst[1]), .b(inf_inst[2]));
initial begin
inf_inst[1].v = 7;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_submod_param.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(timing_loop=True, verilator_flags2=['--timing'])
test.execute()
test.passes()

39
test_regress/t/t_interface_generic_submod_param.v Normal file
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@ -0,0 +1,39 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
module sub #(parameter P);
endmodule
package pkg;
parameter A = 3;
endpackage
class B;
int x;
endclass
module Gm (interface a);
B b;
sub#(.P(pkg::A + $bits(b.x))) s();
initial begin
a.v = s.P;
end
endmodule
interface inf;
int v;
endinterface
module t;
inf i();
Gm g(.a(i));
initial begin
#1;
if (i.v != 35) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_task.py Executable file
View File

@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(timing_loop=True, verilator_flags2=['--timing'])
test.execute()
test.passes()

33
test_regress/t/t_interface_generic_task.v Normal file
View File

@ -0,0 +1,33 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
task setup();
v = 3;
endtask
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface a);
initial begin
a.setup();
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
#1;
if (inf_inst.v != 3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_interface_generic_task2.py Executable file
View File

@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--timing'])
test.execute()
test.passes()

33
test_regress/t/t_interface_generic_task2.v Normal file
View File

@ -0,0 +1,33 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
task setup();
v = 3;
endtask
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface a);
initial begin
#1;
if (a.v != 3) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.setup();
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

7
test_regress/t/t_interface_generic_task_bad.out Executable file
View File

@ -0,0 +1,7 @@
%Error: t/t_interface_generic_task_bad.v:17:7: Can't find definition of 'setup' in dotted task/function: 'a.setup'
: ... note: In instance 't.genericModule'
17 | a.setup();
| ^~~~~
... Known scopes under 'setup': <no instances found>
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

16
test_regress/t/t_interface_generic_task_bad.py Executable file
View File

@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename)
test.passes()

30
test_regress/t/t_interface_generic_task_bad.v Normal file
View File

@ -0,0 +1,30 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface a);
initial begin
a.setup();
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
#1;
if (inf_inst.v != 3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

8
test_regress/t/t_interface_param2.out
View File

@ -1,8 +0,0 @@
%Error-UNSUPPORTED: t/t_interface_param2.v:38:12: Unsupported: generic interfaces
38 | module mem(interface a);
| ^~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_interface_param2.v:49:12: Unsupported: generic interfaces
49 | module cpu(interface b);
| ^~~~~~~~~
%Error: Exiting due to

8
test_regress/t/t_interface_param2.py
View File

@ -11,12 +11,8 @@ import vltest_bootstrap
test.scenarios('simulator')
test.compile(
# Verilator unsupported, bug1104
fails=test.vlt_all,
expect_filename=test.golden_filename)
test.compile()
if not test.vlt_all:
test.execute()
test.execute()
test.passes()

3
test_regress/t/t_interface_param2.v
View File

@ -31,7 +31,7 @@ interface simple_bus #(AWIDTH = 8, DWIDTH = 8)
output data);
initial begin
if (DWIDTH != 16) $stop;
if (DWIDTH != 8 && DWIDTH != 16) $stop;
end
endinterface: simple_bus
@ -40,7 +40,6 @@ module mem(interface a);
always @(posedge a.clk)
a.gnt <= a.req & avail;
initial begin
if ($bits(a.data) != 16) $stop;
$write("*-* All Finished *-*\n");
$finish;
end

8
test_regress/t/t_json_only_begin_hier.out
View File

@ -1,6 +1,6 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED",
"modulesp": [
{"type":"MODULE","name":"test","addr":"(E)","loc":"d,22:8,22:12","isChecker":false,"isProgram":false,"origName":"test","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"test","addr":"(E)","loc":"d,22:8,22:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"test","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"N","addr":"(F)","loc":"d,24:12,24:13","dtypep":"(G)","origName":"N","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":true,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"GENVAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"BEGIN","name":"FOR_GENERATE","addr":"(H)","loc":"d,25:14,25:17","generate":true,"genfor":false,"implied":true,"needProcess":false,"unnamed":false,"genforp": [],"stmtsp": []},
@ -23,7 +23,7 @@
{"type":"CELL","name":"submod_3","addr":"(S)","loc":"d,31:21,31:29","origName":"submod_3","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}
]}
]},
{"type":"MODULE","name":"submod","addr":"(K)","loc":"d,10:8,10:14","isChecker":false,"isProgram":false,"origName":"submod","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"submod","addr":"(K)","loc":"d,10:8,10:14","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"submod","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"BEGIN","name":"submod_gen","addr":"(T)","loc":"d,12:19,12:29","generate":true,"genfor":false,"implied":false,"needProcess":false,"unnamed":false,"genforp": [],
"stmtsp": [
@ -36,7 +36,7 @@
]},
{"type":"CELL","name":"submod_l0","addr":"(AB)","loc":"d,19:13,19:22","origName":"submod_l0","recursive":false,"modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}
]},
{"type":"MODULE","name":"submod2","addr":"(Y)","loc":"d,7:8,7:15","isChecker":false,"isProgram":false,"origName":"submod2","level":4,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],"stmtsp": []}
{"type":"MODULE","name":"submod2","addr":"(Y)","loc":"d,7:8,7:15","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"submod2","level":4,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],"stmtsp": []}
],"filesp": [],
"miscsp": [
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED",
@ -46,7 +46,7 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(BB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(BB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(CB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(BB)","varsp": [],"blocksp": [],"inlinesp": []}
]}

4
test_regress/t/t_json_only_debugcheck.out
View File

@ -1,6 +1,6 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"UNLINKED","evalp":"(F)","evalNbap":"(G)","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(H)",
"modulesp": [
{"type":"MODULE","name":"$root","addr":"(I)","loc":"d,11:8,11:9","isChecker":false,"isProgram":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"$root","addr":"(I)","loc":"d,11:8,11:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"clk","addr":"(J)","loc":"d,15:10,15:13","dtypep":"(K)","origName":"clk","isSc":false,"isPrimaryIO":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":true,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"clker","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"t.e","addr":"(L)","loc":"d,24:9,24:10","dtypep":"(M)","origName":"e","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"VAR","dtypeName":"my_t","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
@ -2987,7 +2987,7 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(URB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(URB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"TOP","addr":"(VRB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(URB)","varsp": [],"blocksp": [],"inlinesp": []}
]}

8
test_regress/t/t_json_only_first.out
View File

@ -1,6 +1,6 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED",
"modulesp": [
{"type":"MODULE","name":"t","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"origName":"t","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"t","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"t","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"q","addr":"(F)","loc":"d,15:22,15:23","dtypep":"(G)","origName":"q","isSc":false,"isPrimaryIO":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"clk","addr":"(H)","loc":"d,13:10,13:13","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
@ -37,7 +37,7 @@
]}
],"paramsp": [],"rangep": [],"intfRefsp": []}
]},
{"type":"MODULE","name":"mod2","addr":"(X)","loc":"d,46:8,46:12","isChecker":false,"isProgram":false,"origName":"mod2","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"mod2","addr":"(X)","loc":"d,46:8,46:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mod2","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"clk","addr":"(FB)","loc":"d,48:10,48:13","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"d","addr":"(Z)","loc":"d,49:16,49:17","dtypep":"(G)","origName":"d","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
@ -50,7 +50,7 @@
{"type":"VARREF","name":"q","addr":"(JB)","loc":"d,53:13,53:14","dtypep":"(G)","access":"WR","varp":"(CB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"MODULE","name":"mod1__W4","addr":"(M)","loc":"d,31:8,31:12","isChecker":false,"isProgram":false,"origName":"mod1","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"mod1__W4","addr":"(M)","loc":"d,31:8,31:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mod1","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"WIDTH","addr":"(KB)","loc":"d,32:15,32:20","dtypep":"(LB)","origName":"WIDTH","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"GPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":true,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],
"valuep": [
@ -93,7 +93,7 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(WB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(WB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(XB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(WB)","varsp": [],"blocksp": [],"inlinesp": []}
]}

4
test_regress/t/t_json_only_flat.out
View File

@ -1,6 +1,6 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)",
"modulesp": [
{"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"q","addr":"(G)","loc":"d,15:22,15:23","dtypep":"(H)","origName":"q","isSc":false,"isPrimaryIO":true,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"clk","addr":"(I)","loc":"d,13:10,13:13","dtypep":"(J)","origName":"clk","isSc":false,"isPrimaryIO":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"clker","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
@ -146,7 +146,7 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(BD)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(BD)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(CD)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(BD)","varsp": [],"blocksp": [],"inlinesp": []}
]}

4
test_regress/t/t_json_only_flat_no_inline_mod.out
View File

@ -1,6 +1,6 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)",
"modulesp": [
{"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","isChecker":false,"isProgram":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
@ -39,7 +39,7 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(U)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(U)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(V)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(U)","varsp": [],"blocksp": [],"inlinesp": []}
]}

4
test_regress/t/t_json_only_flat_pub_mod.out
View File

@ -1,6 +1,6 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)",
"modulesp": [
{"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","isChecker":false,"isProgram":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
@ -39,7 +39,7 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(U)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(U)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(V)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(U)","varsp": [],"blocksp": [],"inlinesp": []}
]}

4
test_regress/t/t_json_only_flat_vlvbound.out
View File

@ -1,6 +1,6 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)",
"modulesp": [
{"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:21","isChecker":false,"isProgram":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:21","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"i_a","addr":"(G)","loc":"d,9:25,9:28","dtypep":"(H)","origName":"i_a","isSc":false,"isPrimaryIO":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"i_b","addr":"(I)","loc":"d,10:25,10:28","dtypep":"(H)","origName":"i_b","isSc":false,"isPrimaryIO":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
@ -307,7 +307,7 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(OF)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(OF)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(PF)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(OF)","varsp": [],"blocksp": [],"inlinesp": []}
]}

4
test_regress/t/t_json_only_output.out
View File

@ -1,6 +1,6 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED",
"modulesp": [
{"type":"MODULE","name":"m","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"origName":"m","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"m","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"m","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:10,8:13","dtypep":"(G)","origName":"clk","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
]}
@ -12,7 +12,7 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(H)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(H)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(I)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(H)","varsp": [],"blocksp": [],"inlinesp": []}
]}

4
test_regress/t/t_json_only_tag.out
View File

@ -1,6 +1,6 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED",
"modulesp": [
{"type":"MODULE","name":"m","addr":"(E)","loc":"d,12:8,12:9","isChecker":false,"isProgram":false,"origName":"m","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"m","addr":"(E)","loc":"d,12:8,12:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"m","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"clk_ip","addr":"(F)","loc":"d,14:11,14:17","dtypep":"(G)","origName":"clk_ip","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"rst_ip","addr":"(H)","loc":"d,15:11,15:17","dtypep":"(G)","origName":"rst_ip","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
@ -91,7 +91,7 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(AC)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(AC)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(BC)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(AC)","varsp": [],"blocksp": [],"inlinesp": []}
]}

32
test_regress/t/t_var_port_json_only.out
View File

@ -1,66 +1,66 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED",
"modulesp": [
{"type":"MODULE","name":"mh2","addr":"(E)","loc":"d,18:8,18:11","isChecker":false,"isProgram":false,"origName":"mh2","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"mh2","addr":"(E)","loc":"d,18:8,18:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh2","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"x_inout_wire_integer","addr":"(F)","loc":"d,18:27,18:47","dtypep":"(G)","origName":"x_inout_wire_integer","isSc":false,"isPrimaryIO":false,"direction":"INOUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
]},
{"type":"MODULE","name":"mh5","addr":"(H)","loc":"d,24:8,24:11","isChecker":false,"isProgram":false,"origName":"mh5","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
{"type":"MODULE","name":"mh5","addr":"(H)","loc":"d,24:8,24:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh5","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"x_input_wire_logic","addr":"(I)","loc":"d,24:19,24:37","dtypep":"(J)","origName":"x_input_wire_logic","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
]},
{"type":"MODULE","name":"mh6","addr":"(K)","loc":"d,26:8,26:11","isChecker":false,"isProgram":false,"origName":"mh6","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
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