Fix signed cast (#6912) (#6068)

This commit is contained in:
Todd Strader
2025-06-06 21:13:31 -04:00
committed by GitHub
parent 54e637c72b
commit a044697990
3 changed files with 46 additions and 3 deletions
+5 -3
View File
@@ -2128,9 +2128,11 @@ class WidthVisitor final : public VNVisitor {
if (debug() >= 9) nodep->dumpTree("- CastPre: ");
// if (debug()) nodep->backp()->dumpTree("- CastPreUpUp: ");
if (AstSigned* const fromp = VN_CAST(nodep->fromp(), Signed)) {
AstNode* const lhsp = fromp->lhsp()->unlinkFrBack();
fromp->replaceWith(lhsp);
VL_DO_DANGLING(fromp->deleteTree(), fromp);
if (VN_IS(fromp->lhsp(), NodeStream)) {
AstNode* const lhsp = fromp->lhsp()->unlinkFrBack();
fromp->replaceWith(lhsp);
VL_DO_DANGLING(fromp->deleteTree(), fromp);
}
}
userIterateAndNext(nodep->fromp(), WidthVP{SELF, PRELIM}.p());
if (debug() >= 9) nodep->dumpTree("- CastDit: ");
+18
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@@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios("simulator")
test.compile()
test.execute()
test.passes()
+23
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@@ -0,0 +1,23 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
logic [7:0] smaller;
logic [15:0] bigger;
typedef logic [15:0] bigger_t;
initial begin
smaller = 8'hfa;
bigger = bigger_t'(signed'(smaller));
$display("%x", bigger); // NOCOMMIT
if (bigger != 16'hfffa) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule