Commentary (#6246)

2025-07-31 18:09:43 -04:00 · 2025-07-31 18:09:43 -04:00 · 5faaa7ec58
parent d8f1e1113a
commit 5faaa7ec58
1 changed files with 0 additions and 2 deletions
--- a/docs/guide/verilating.rst
+++ b/docs/guide/verilating.rst
@ -147,8 +147,6 @@ Hierarchy blocks have some limitations, including:
 * The hierarchy block cannot be accessed using dot (.) from the upper
  module(s) or other hierarchy blocks.

-* Signals in the block cannot be traced.
-
 * Modport cannot be used at the hierarchical block boundary.

 * The simulation speed is likely not as fast as flat Verilation, in which