Fix referencing module variables above classes (#6304)
Signed-off-by: Artur Bieniek <abieniek@internships.antmicro.com>
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@ -68,9 +68,18 @@ class ScopeVisitor final : public VNVisitor {
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UASSERT_OBJ(it2 != m_packageScopes.end(), nodep, "Can't locate package scope");
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scopep = it2->second;
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}
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const auto it3 = m_varScopes.find(std::make_pair(nodep->varp(), scopep));
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UASSERT_OBJ(it3 != m_varScopes.end(), nodep, "Can't locate varref scope");
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AstVarScope* const varscp = it3->second;
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// Search up the scope hierarchy for the variable
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AstVarScope* varscp = nullptr;
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AstScope* searchScopep = scopep;
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while (searchScopep) {
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const auto it3 = m_varScopes.find(std::make_pair(nodep->varp(), searchScopep));
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if (it3 != m_varScopes.end()) {
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varscp = it3->second;
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break;
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}
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searchScopep = searchScopep->aboveScopep();
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}
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UASSERT_OBJ(varscp, nodep, "Can't locate varref scope");
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nodep->varScopep(varscp);
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}
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}
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,34 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module m();
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class c;
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static function void fstatic();
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`checkh(v, 42);
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v++;
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endfunction
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function void fnonstatic();
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`checkh(v, 43);
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v++;
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endfunction
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endclass
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c classinst;
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int v;
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initial begin
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v=42;
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`checkh(v, 42);
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c::fstatic();
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classinst = new();
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classinst.fnonstatic();
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`checkh(v, 44);
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$finish;
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end
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endmodule
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