Support `$fread` with missing start (#6125).
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Wilson Snyder
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@ -29,6 +29,7 @@ Verilator 5.039 devel
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* Support randomization of scope variables with 'std::randomize()' (#5438) (#6185). [Yilou Wang]
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* Support disabling a fork in additional contexts (#5432 partial) (#6174) (#6183). [Ryszard Rozak, Antmicro Ltd.]
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* Support bit queue streaming (#5830) (#6103). [Paul Swirhun]
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* Support `$fread` with missing start (#6125). [Iztok Jeras]
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* Support unpacked array `with` methods (#6134).
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* Support Verilog real ports as SystemC double ports (#6136) (#6158). [George Polack]
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* Support `$countones` in constraints (#6144 partial) (#6235). [Ryszard Rozak, Antmicro Ltd.]
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@ -4500,6 +4500,7 @@ system_f_call_or_t<nodeExprp>: // IEEE: part of system_tf_call (can be task
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| yD_FREAD '(' expr ',' expr ')' { $$ = new AstFRead{$1, $3, $5, nullptr, nullptr}; }
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| yD_FREAD '(' expr ',' expr ',' expr ')' { $$ = new AstFRead{$1, $3, $5, $7, nullptr}; }
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| yD_FREAD '(' expr ',' expr ',' expr ',' expr ')' { $$ = new AstFRead{$1, $3, $5, $7, $9}; }
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| yD_FREAD '(' expr ',' expr ',' ',' expr ')' { $$ = new AstFRead{$1, $3, $5, nullptr, $8}; }
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| yD_FREWIND '(' expr ')' { $$ = new AstFRewind{$1, $3}; }
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| yD_FLOOR '(' expr ')' { $$ = new AstFloorD{$1, $3}; }
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| yD_FSCANF '(' expr ',' str commaVRDListE ')' { $$ = new AstFScanF{$1, *$5, $3, $6}; }
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@ -1,7 +1,7 @@
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Dump:
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r_i: 00010203
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r_upb: 0e 0d 0c 0b 0a 09 08 07 06 05 04
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r_dnb: 19 18 17 16 15 14 13 12 11 10 0f
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r_dnb: 0f 10 11 12 13 14 15 16 17 18 19
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r_ups: 2e2f 2c2d 2a2b 2829 2627 2425 2223 2021 1e1f 1c1d 1a1b
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r_dns: 3031 3233 3435 3637 3839 3a3b 3c3d 3e3f 0041 0243 0445
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r_upi: 6e6f7071 6a6b6c6d 66676869 62636465 5e5f6061 5a5b5c5d 56575859 52535455 4e4f5051 4a4b4c4d 46474849
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@ -13,9 +13,9 @@ Dump:
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Dump:
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r_i: ffffffff
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r_upb: 05 04 03 02 01 00 ff ff ff ff ff
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r_dnb: ff ff ff ff ff ff ff ff ff ff ff
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r_ups: 3fff 3fff 3fff 3fff 0809 0607 3fff 3fff 3fff 3fff 3fff
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r_upb: 05 04 03 02 01 00 ff 0e ff ff 0c
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r_dnb: 0d ff ff 0f ff 06 07 08 09 0a 0b
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r_ups: 3fff 3fff 3fff 3fff 1213 1011 3fff 3fff 3fff 3fff 3fff
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r_dns: 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff
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r_upi: 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff
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r_dni: 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff
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@ -4,87 +4,99 @@
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define STRINGIFY(x) `"x`"
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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//======================================================================
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module t;
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integer file;
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integer r_i;
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byte r_upb[20:10];
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byte r_dnb[20:10];
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reg [13:0] r_ups[20:10];
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reg [13:0] r_dns[10:20];
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reg [30:0] r_upi[20:10];
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reg [30:0] r_dni[10:20];
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reg [61:0] r_upq[20:10];
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reg [61:0] r_dnq[10:20];
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reg [71:0] r_upw[20:10];
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reg [71:0] r_dnw[10:20];
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integer file;
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integer r_i;
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byte r_upb[20:10];
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byte r_dnb[10:20];
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reg [13:0] r_ups[20:10];
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reg [13:0] r_dns[10:20];
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reg [30:0] r_upi[20:10];
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reg [30:0] r_dni[10:20];
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reg [61:0] r_upq[20:10];
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reg [61:0] r_dnq[10:20];
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reg [71:0] r_upw[20:10];
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reg [71:0] r_dnw[10:20];
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task clear;
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// Initialize memories to zero,
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// avoid differences between 2-state and 4-state.
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r_i = ~0;
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foreach (r_upb[i]) r_upb[i] = ~0;
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foreach (r_dnb[i]) r_dnb[i] = ~0;
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foreach (r_ups[i]) r_ups[i] = ~0;
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foreach (r_dns[i]) r_dns[i] = ~0;
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foreach (r_upi[i]) r_upi[i] = ~0;
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foreach (r_dni[i]) r_dni[i] = ~0;
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foreach (r_upq[i]) r_upq[i] = ~0;
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foreach (r_dnq[i]) r_dnq[i] = ~0;
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foreach (r_upw[i]) r_upw[i] = ~0;
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foreach (r_dnw[i]) r_dnw[i] = ~0;
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task clear;
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// Initialize memories to zero,
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// avoid differences between 2-state and 4-state.
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r_i = ~0;
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foreach (r_upb[i]) r_upb[i] = ~0;
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foreach (r_dnb[i]) r_dnb[i] = ~0;
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foreach (r_ups[i]) r_ups[i] = ~0;
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foreach (r_dns[i]) r_dns[i] = ~0;
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foreach (r_upi[i]) r_upi[i] = ~0;
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foreach (r_dni[i]) r_dni[i] = ~0;
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foreach (r_upq[i]) r_upq[i] = ~0;
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foreach (r_dnq[i]) r_dnq[i] = ~0;
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foreach (r_upw[i]) r_upw[i] = ~0;
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foreach (r_dnw[i]) r_dnw[i] = ~0;
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// Open file
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$fclose(file);
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file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_fread.mem"}, "r");
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if ($feof(file)) $stop;
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endtask
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// Open file
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$fclose(file);
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file = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_sys_fread.mem"}, "r");
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if ($feof(file)) $stop;
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endtask
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task dump;
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$write("Dump:");
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$write("\n r_i:"); $write(" %x",r_i);
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$write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]);
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$write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]);
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$write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]);
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$write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]);
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$write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]);
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$write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]);
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$write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]);
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$write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]);
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$write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]);
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$write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]);
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$write("\n\n");
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endtask
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task dump;
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// verilog_format: off
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$write("Dump:");
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$write("\n r_i:"); $write(" %x",r_i);
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$write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]);
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$write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]);
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$write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]);
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$write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]);
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$write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]);
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$write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]);
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$write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]);
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$write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]);
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$write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]);
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$write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]);
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$write("\n\n");
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// verilog_format: on
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endtask
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integer code;
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integer code;
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initial begin
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clear;
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code = $fread(r_i, file); `checkd(code, 4);
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code = $fread(r_upb, file); `checkd(code, 11);
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code = $fread(r_dnb, file); `checkd(code, 11);
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code = $fread(r_ups, file); `checkd(code, 22);
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code = $fread(r_dns, file); `checkd(code, 22);
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code = $fread(r_upi, file); `checkd(code, 44);
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code = $fread(r_dni, file); `checkd(code, 44);
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code = $fread(r_upq, file); `checkd(code, 88);
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code = $fread(r_dnq, file); `checkd(code, 88);
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code = $fread(r_upw, file); `checkd(code, 99);
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code = $fread(r_dnw, file); `checkd(code, 99);
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dump;
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initial begin
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// verilog_format: off
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clear;
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code = $fread(r_i, file); `checkd(code, 4);
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code = $fread(r_upb, file); `checkd(code, 11);
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code = $fread(r_dnb, file); `checkd(code, 11);
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code = $fread(r_ups, file); `checkd(code, 22);
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code = $fread(r_dns, file); `checkd(code, 22);
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code = $fread(r_upi, file); `checkd(code, 44);
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code = $fread(r_dni, file); `checkd(code, 44);
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code = $fread(r_upq, file); `checkd(code, 88);
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code = $fread(r_dnq, file); `checkd(code, 88);
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code = $fread(r_upw, file); `checkd(code, 99);
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code = $fread(r_dnw, file); `checkd(code, 99);
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dump;
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clear;
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code = $fread(r_upb, file, 15); `checkd(code, 6);
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// Bug where fread in if() broke.
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if ($fread(r_ups, file, 15, 2) != 4) $stop;
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dump;
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clear;
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code = $fread(r_upb, file, 15); `checkd(code, 6);
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code = $fread(r_dnb, file, 15); `checkd(code, 6);
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code = $fread(r_upb, file, , 1); `checkd(code, 1);
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code = $fread(r_dnb, file, , 1); `checkd(code, 1);
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code = $fread(r_upb, file, 13, 1); `checkd(code, 1);
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code = $fread(r_dnb, file, 13, 1); `checkd(code, 1);
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// verilog_format: on
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$write("*-* All Finished *-*\n");
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$finish;
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end
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// Bug where fread in if() broke.
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if ($fread(r_ups, file, 15, 2) != 4) $stop;
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dump;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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