Fix sign extension of signed compared with unsigned case items (#5968).
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@ -13,6 +13,8 @@ Verilator 5.037 devel
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**Other:**
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* Fix sign extension of signed compared with unsigned case items (#5968).
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Verilator 5.036 2025-04-27
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==========================
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@ -5076,7 +5076,7 @@ class WidthVisitor final : public VNVisitor {
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}
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// Apply width
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iterateCheck(nodep, "Case expression", nodep->exprp(), CONTEXT_DET, FINAL, subDTypep,
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EXTEND_LHS);
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EXTEND_EXP);
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for (AstCaseItem* itemp = nodep->itemsp(); itemp;
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itemp = VN_AS(itemp->nextp(), CaseItem)) {
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for (AstNode *nextcp, *condp = itemp->condsp(); condp; condp = nextcp) {
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@ -48,7 +48,13 @@ module t (/*AUTOARG*/);
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wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111;
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initial `checkh(cond_b, 6'b111111);
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bit cmp;
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initial begin
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`ifndef VERILATOR
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#1;
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`endif
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// verilator lint_on WIDTH
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`checkh(bug729_yuu, 1'b0);
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`checkh(bug729_ysu, 1'b0);
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@ -81,13 +87,37 @@ module t (/*AUTOARG*/);
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bug349_s = 4'sb1111 - 5'b00001;
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`checkh(bug349_s,33'he);
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cmp = 3'sb111 == 4'b111;
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`checkh(cmp, 1);
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cmp = 3'sb111 == 4'sb111;
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`checkh(cmp, 0);
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cmp = 3'sb111 != 4'b111;
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`checkh(cmp, 0);
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cmp = 3'sb111 != 4'sb111;
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`checkh(cmp, 1);
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cmp = 3'sb111 === 4'b111;
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`checkh(cmp, 1);
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cmp = 3'sb111 === 4'sb111;
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`checkh(cmp, 0);
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case (2'sb11)
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4'b1111: ;
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4'b1111: $stop;
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default: ;
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endcase
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case (sb11)
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4'b1111: $stop;
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default: ;
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endcase
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case (2'sb11)
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4'sb1111: ;
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default: $stop;
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endcase
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case (sb11)
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4'b1111: ;
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4'sb1111: ;
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default: $stop;
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endcase
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@ -96,7 +126,7 @@ module t (/*AUTOARG*/);
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end
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endmodule
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module sub (input [3:0] a,
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output [3:0] z);
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module sub(input [3:0] a,
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output [3:0] z);
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assign z = a;
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endmodule
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