Fix parameter passing to ports (#4723)
Signed-off-by: Ryszard Rozak <rrozak@antmicro.com>
This commit is contained in:
Ryszard Rozak
GitHub
parent
7167d4bdc0
commit
ebfc2a4942
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@ -283,7 +283,7 @@ class InlineRelinkVisitor final : public VNVisitor {
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// user2p is either a const or a var.
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FileLine* const flp = nodep->fileline();
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AstConst* const exprconstp = VN_CAST(nodep->user2p(), Const);
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const AstVarRef* const exprvarrefp = VN_CAST(nodep->user2p(), VarRef);
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AstVarRef* exprvarrefp = VN_CAST(nodep->user2p(), VarRef);
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UINFO(8, "connectto: " << nodep->user2p() << endl);
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UASSERT_OBJ(exprconstp || exprvarrefp, nodep,
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"Unknown interconnect type; pinReconnectSimple should have cleared up");
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@ -296,30 +296,32 @@ class InlineRelinkVisitor final : public VNVisitor {
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// remove the change detection on the output variable.
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UINFO(9, "public pin assign: " << exprvarrefp << endl);
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UASSERT_OBJ(!nodep->isNonOutput(), nodep, "Outputs only - inputs use AssignAlias");
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m_modp->addStmtsp(
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new AstAssignW{flp, new AstVarRef{flp, exprvarrefp->varp(), VAccess::WRITE},
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new AstVarRef{flp, nodep, VAccess::READ}});
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m_modp->addStmtsp(new AstAssignW{flp, exprvarrefp->cloneTree(false),
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new AstVarRef{flp, nodep, VAccess::READ}});
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} else if (nodep->isSigPublic() && VN_IS(nodep->dtypep(), UnpackArrayDType)) {
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// Public variable at this end and it is an unpacked array. We need to assign
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// instead of aliased, because otherwise it will pass V3Slice and invalid
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// code will be emitted.
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UINFO(9, "assign to public and unpacked: " << nodep << endl);
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exprvarrefp = exprvarrefp->cloneTree(false);
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exprvarrefp->access(VAccess::READ);
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m_modp->addStmtsp(
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new AstAssignW{flp, new AstVarRef{flp, nodep, VAccess::WRITE},
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new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}});
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new AstAssignW{flp, new AstVarRef{flp, nodep, VAccess::WRITE}, exprvarrefp});
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} else if (nodep->isIfaceRef()) {
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m_modp->addStmtsp(
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new AstAssignVarScope{flp, new AstVarRef{flp, nodep, VAccess::WRITE},
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new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}});
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exprvarrefp = exprvarrefp->cloneTree(false);
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exprvarrefp->access(VAccess::READ);
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m_modp->addStmtsp(new AstAssignVarScope{
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flp, new AstVarRef{flp, nodep, VAccess::WRITE}, exprvarrefp});
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FileLine* const flbp = exprvarrefp->varp()->fileline();
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flp->modifyStateInherit(flbp);
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flbp->modifyStateInherit(flp);
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} else {
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// Do to inlining child's variable now within the same
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// module, so a AstVarRef not AstVarXRef below
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m_modp->addStmtsp(
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new AstAssignAlias{flp, new AstVarRef{flp, nodep, VAccess::WRITE},
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new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}});
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exprvarrefp = exprvarrefp->cloneTree(false);
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exprvarrefp->access(VAccess::READ);
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m_modp->addStmtsp(new AstAssignAlias{
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flp, new AstVarRef{flp, nodep, VAccess::WRITE}, exprvarrefp});
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FileLine* const flbp = exprvarrefp->varp()->fileline();
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flp->modifyStateInherit(flbp);
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flbp->modifyStateInherit(flp);
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@ -376,6 +378,7 @@ class InlineRelinkVisitor final : public VNVisitor {
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return;
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} else if (const AstVarRef* const vrefp = VN_CAST(varp->user2p(), VarRef)) {
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nodep->varp(vrefp->varp());
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nodep->classOrPackagep(vrefp->classOrPackagep());
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} else {
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nodep->v3fatalSrc("Null connection?");
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}
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@ -0,0 +1,20 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2023 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile();
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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@ -0,0 +1,25 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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parameter int HwDataAttr[1] = '{1};
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module flash_mp_data_region_sel (
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input int region_attrs_i[1]
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);
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initial begin
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int o = 0;
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for (int i = 0; i < 1; i++) begin
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o = region_attrs_i[i];
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end
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if (o != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module t;
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flash_mp_data_region_sel u_hw_sel (.region_attrs_i(HwDataAttr));
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endmodule
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@ -64,15 +64,15 @@
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<varref loc="d,14,16,14,17" name="t.d" dtype_id="1"/>
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</assignalias>
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<assignalias loc="d,34,24,34,27" dtype_id="2">
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<varref loc="d,34,24,34,27" name="t.clk" dtype_id="2"/>
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<varref loc="d,21,42,21,45" name="t.clk" dtype_id="2"/>
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<varref loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2"/>
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</assignalias>
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<assignalias loc="d,35,30,35,31" dtype_id="1">
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<varref loc="d,35,30,35,31" name="t.d" dtype_id="1"/>
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<varref loc="d,22,42,22,43" name="t.d" dtype_id="1"/>
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<varref loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1"/>
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</assignalias>
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<assignalias loc="d,36,30,36,31" dtype_id="1">
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<varref loc="d,36,30,36,31" name="t.between" dtype_id="1"/>
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<varref loc="d,20,14,20,21" name="t.between" dtype_id="1"/>
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<varref loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
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</assignalias>
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<always loc="d,41,4,41,10">
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@ -87,15 +87,15 @@
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</assigndly>
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</always>
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<assignalias loc="d,48,10,48,13" dtype_id="2">
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<varref loc="d,48,10,48,13" name="t.clk" dtype_id="2"/>
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<varref loc="d,27,42,27,45" name="t.clk" dtype_id="2"/>
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<varref loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
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</assignalias>
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<assignalias loc="d,49,16,49,17" dtype_id="1">
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<varref loc="d,49,16,49,17" name="t.between" dtype_id="1"/>
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<varref loc="d,25,16,25,23" name="t.between" dtype_id="1"/>
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<varref loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
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</assignalias>
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<assignalias loc="d,50,22,50,23" dtype_id="1">
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<varref loc="d,50,22,50,23" name="t.q" dtype_id="1"/>
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<varref loc="d,26,42,26,43" name="t.q" dtype_id="1"/>
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<varref loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
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</assignalias>
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<contassign loc="d,53,13,53,14" dtype_id="1">
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@ -28,7 +28,7 @@
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<varref loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
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</assignalias>
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<assignalias loc="d,7,24,7,29" dtype_id="1">
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<varref loc="d,7,24,7,29" name="top.i_clk" dtype_id="1"/>
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<varref loc="d,12,7,12,8" name="top.i_clk" dtype_id="1"/>
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<varref loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
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</assignalias>
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</scope>
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@ -28,7 +28,7 @@
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<varref loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
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</assignalias>
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<assignalias loc="d,7,24,7,29" dtype_id="1">
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<varref loc="d,7,24,7,29" name="top.i_clk" dtype_id="1"/>
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<varref loc="d,12,7,12,8" name="top.i_clk" dtype_id="1"/>
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<varref loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
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</assignalias>
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</scope>
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