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Tests: Favor all caps for tests' parameters. No test change.

This commit is contained in:
Wilson Snyder 2025-08-29 18:33:14 -04:00
parent 8868d459a2
commit 91d138248d
46 changed files with 1760 additions and 1604 deletions
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6
test_regress/t/t_array_non_blocking_loop.v
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@ -7,8 +7,8 @@
interface intf
#(
parameter int write_data_width) ();
logic [write_data_width-1:0] writedata;
parameter int WRITE_DATA_WIDTH) ();
logic [WRITE_DATA_WIDTH-1:0] writedata;
endinterface
module t( /*AUTOARG*/
clk
@ -20,7 +20,7 @@ module t( /*AUTOARG*/
for (num_chunks = 1; num_chunks <= 2; num_chunks++) begin : gen_n
localparam int decoded_width = 55 * num_chunks;
intf #(
.write_data_width(decoded_width))
.WRITE_DATA_WIDTH(decoded_width))
the_intf ();
always @(posedge clk) begin
for (int i = 0; i < decoded_width; i++)

8
test_regress/t/t_assert_elab.v
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@ -5,18 +5,18 @@
// SPDX-License-Identifier: CC0-1.0
module t;
localparam str = "string";
localparam STR = "string";
function logic checkParameter(input logic [8:0] N);
$display("x is %d.", N);
if (N == 1)
return 0;
$fatal(1, "Parameter %d is invalid...%s and %s", N, str, "constant both work");
$fatal(1, "Parameter %d is invalid...%s and %s", N, STR, "constant both work");
endfunction
`ifdef FAILING_ASSERTIONS
localparam x = checkParameter(5);
localparam X = checkParameter(5);
`else
localparam x = checkParameter(1);
localparam X = checkParameter(1);
`endif
initial begin

137
test_regress/t/t_bind2.v
View File

@ -7,87 +7,90 @@
// verilator lint_off WIDTH
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] p1;
reg [7:0] p2;
reg [7:0] p3;
module t ( /*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] p1;
reg [7:0] p2;
reg [7:0] p3;
initial begin
p1 = 8'h01;
p2 = 8'h02;
p3 = 8'h03;
end
initial begin
p1 = 8'h01;
p2 = 8'h02;
p3 = 8'h03;
end
parameter int param1 = 8'h11;
parameter int param2 = 8'h12;
parameter int param3 = 8'h13;
parameter int PARAM1 = 8'h11;
parameter int PARAM2 = 8'h12;
parameter int PARAM3 = 8'h13;
targetmod i_targetmod (/*AUTOINST*/
// Inputs
.clk (clk));
targetmod i_targetmod ( /*AUTOINST*/
// Inputs
.clk (clk));
//Binding i_targetmod to mycheck --instantiates i_mycheck inside i_targetmod
//param1 not over-riden (as mycheck) (=> 0x31)
//param2 explicitly bound to targetmod value (=> 0x22)
//param3 explicitly bound to top value (=> 0x13)
//p1 implictly bound (.*), takes value from targetmod (=> 0x04)
//p2 explictly bound to targetmod (=> 0x05)
//p3 explictly bound to top (=> 0x03)
//Binding i_targetmod to mycheck --instantiates i_mycheck inside i_targetmod
//PARAM1 not over-riden (as mycheck) (=> 0x31)
//PARAM2 explicitly bound to targetmod value (=> 0x22)
//PARAM3 explicitly bound to top value (=> 0x13)
//p1 implictly bound (.*), takes value from targetmod (=> 0x04)
//p2 explictly bound to targetmod (=> 0x05)
//p3 explictly bound to top (=> 0x03)
// Alternative unsupported form is i_targetmod
bind targetmod mycheck
#(
.param2(param2),
.param3(param3)
)
i_mycheck (.p2(p2), .p3(p3), .*);
// Alternative unsupported form is i_targetmod
bind targetmod mycheck #(
.PARAM2(PARAM2),
.PARAM3(PARAM3)
) i_mycheck (
.p2(p2),
.p3(p3),
.*);
endmodule
module targetmod (input clk);
reg [7:0] p1;
reg [7:0] p2;
reg [7:0] p3;
module targetmod (
input clk
);
reg [7:0] p1;
reg [7:0] p2;
reg [7:0] p3;
parameter int param1 = 8'h21;
parameter int param2 = 8'h22;
parameter int param3 = 8'h23;
parameter int PARAM1 = 8'h21;
parameter int PARAM2 = 8'h22;
parameter int PARAM3 = 8'h23;
initial begin
p1 = 8'h04;
p2 = 8'h05;
p3 = 8'h06;
end
initial begin
p1 = 8'h04;
p2 = 8'h05;
p3 = 8'h06;
end
endmodule
module mycheck (/*AUTOARG*/
// Inputs
clk, p1, p2, p3
);
module mycheck ( /*AUTOARG*/
// Inputs
clk, p1, p2, p3
);
input clk;
input [7:0] p1;
input [7:0] p2;
input [7:0] p3;
input clk;
input [7:0] p1;
input [7:0] p2;
input [7:0] p3;
parameter int param1 = 8'h31;
parameter int param2 = 8'h32;
parameter int param3 = 8'h33;
parameter int PARAM1 = 8'h31;
parameter int PARAM2 = 8'h32;
parameter int PARAM3 = 8'h33;
always @ (posedge clk) begin
`checkh(param1,8'h31);
`checkh(param2,8'h22);
`checkh(param3,8'h23);
`checkh(p1,8'h04);
`checkh(p2,8'h05);
`checkh(p3,8'h06);
$write("*-* All Finished *-*\n");
$finish;
end
always @(posedge clk) begin
`checkh(PARAM1, 8'h31);
`checkh(PARAM2, 8'h22);
`checkh(PARAM3, 8'h23);
`checkh(p1, 8'h04);
`checkh(p2, 8'h05);
`checkh(p3, 8'h06);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

6
test_regress/t/t_bitsel_2d_slice.v
View File

@ -10,9 +10,9 @@ module t (/*AUTOARG*/
);
input clk;
localparam int width = 8;
typedef logic [width-1:0] [15:0] two_dee_t;
typedef logic[$clog2(width)-1:0] index_t;
localparam int WIDTH = 8;
typedef logic [WIDTH-1:0] [15:0] two_dee_t;
typedef logic[$clog2(WIDTH)-1:0] index_t;
two_dee_t the_two_dee;

10
test_regress/t/t_case_orig.v
View File

@ -24,7 +24,7 @@ module t (/*AUTOARG*/
wire sigone2 = 1'b1;
reg ok;
parameter [1:0] twounkn = 2'b?; // This gets extended to 2'b??
parameter [1:0] TWOUNKN = 2'b?; // This gets extended to 2'b??
// Large case statements should be well optimizable.
reg [2:0] anot;
@ -64,13 +64,13 @@ module t (/*AUTOARG*/
endcase
casez (a)
default: $stop;
{1'b0, twounkn}: $stop;
{1'b1, twounkn}: ;
{1'b0, TWOUNKN}: $stop;
{1'b1, TWOUNKN}: ;
endcase
casez (b)
default: $stop;
{1'b0, twounkn}: $stop;
{1'b1, twounkn}: ;
{1'b0, TWOUNKN}: $stop;
{1'b1, TWOUNKN}: ;
// {1'b0, 2'b??}: $stop;
// {1'b1, 2'b??}: ;
endcase

6
test_regress/t/t_cover_expr.out
View File

@ -47,10 +47,10 @@
-000005 point: comment=(b==0) => 0 hier=top.t
endfunction
localparam int num_intfs = 4;
intf the_intfs [num_intfs-1:0] ();
localparam int NUM_INTFS = 4;
intf the_intfs [NUM_INTFS-1:0] ();
genvar intf_i;
for (intf_i = 0; intf_i < num_intfs; intf_i++) begin
for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin
always_comb the_intfs[intf_i].t = cyc[intf_i];
end

6
test_regress/t/t_cover_expr.v
View File

@ -41,10 +41,10 @@ module t (/*AUTOARG*/
return a & b;
endfunction
localparam int num_intfs = 4;
intf the_intfs [num_intfs-1:0] ();
localparam int NUM_INTFS = 4;
intf the_intfs [NUM_INTFS-1:0] ();
genvar intf_i;
for (intf_i = 0; intf_i < num_intfs; intf_i++) begin
for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin
always_comb the_intfs[intf_i].t = cyc[intf_i];
end

6
test_regress/t/t_cover_expr_max.out
View File

@ -47,10 +47,10 @@
-000005 point: comment=(b==0) => 0 hier=top.t
endfunction
localparam int num_intfs = 4;
intf the_intfs [num_intfs-1:0] ();
localparam int NUM_INTFS = 4;
intf the_intfs [NUM_INTFS-1:0] ();
genvar intf_i;
for (intf_i = 0; intf_i < num_intfs; intf_i++) begin
for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin
always_comb the_intfs[intf_i].t = cyc[intf_i];
end

6
test_regress/t/t_cover_expr_trace.out
View File

@ -47,10 +47,10 @@
-000005 point: comment=(b==0) => 0 hier=top.t
endfunction
localparam int num_intfs = 4;
intf the_intfs [num_intfs-1:0] ();
localparam int NUM_INTFS = 4;
intf the_intfs [NUM_INTFS-1:0] ();
genvar intf_i;
for (intf_i = 0; intf_i < num_intfs; intf_i++) begin
for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin
always_comb the_intfs[intf_i].t = cyc[intf_i];
end

6
test_regress/t/t_cover_line_expr.out
View File

@ -54,10 +54,10 @@
-000005 point: comment=(b==0) => 0 hier=top.t
endfunction
localparam int num_intfs = 4;
intf the_intfs [num_intfs-1:0] ();
localparam int NUM_INTFS = 4;
intf the_intfs [NUM_INTFS-1:0] ();
genvar intf_i;
%000004 for (intf_i = 0; intf_i < num_intfs; intf_i++) begin
%000004 for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin
-000004 point: comment=block hier=top.t
%000004 always_comb the_intfs[intf_i].t = cyc[intf_i];
-000004 point: comment=block hier=top.t

64
test_regress/t/t_foreach_const.v
View File

@ -46,7 +46,7 @@ module t (/*AUTOARG*/);
if (index_a == 1) return 7;
end
endfunction
localparam par1 = test1();
localparam PAR1 = test1();
function [63:0] test2;
test2 = 0;
@ -54,7 +54,7 @@ module t (/*AUTOARG*/);
test2 = crc(test2, index_a, 0, 0, 0);
end
endfunction
localparam par2 = test2();
localparam PAR2 = test2();
function [63:0] test3;
test3 = 0;
@ -62,7 +62,7 @@ module t (/*AUTOARG*/);
test3 = crc(test3, index_a, index_b, 0, 0);
end
endfunction
localparam par3 = test3();
localparam PAR3 = test3();
function [63:0] test4;
test4 = 0;
@ -70,7 +70,7 @@ module t (/*AUTOARG*/);
test4 = crc(test4, index_a, index_b, index_c, 0);
end
endfunction
localparam par4 = test4();
localparam PAR4 = test4();
function [63:0] test5;
test5 = 0;
@ -78,7 +78,7 @@ module t (/*AUTOARG*/);
test5 = crc(test5, index_a, index_b, index_c, index_d);
end
endfunction
localparam par5 = test5();
localparam PAR5 = test5();
function [63:0] test6;
// comma syntax
@ -88,7 +88,7 @@ module t (/*AUTOARG*/);
test6 = crc(test6, 0, index_b, 0, 0);
end
endfunction
localparam par6 = test6();
localparam PAR6 = test6();
function [63:0] test7;
test7 = 0;
@ -96,7 +96,7 @@ module t (/*AUTOARG*/);
test7 = crc(test7, index_a, 0, 0, 0);
end
endfunction
localparam par7 = test7();
localparam PAR7 = test7();
function [63:0] test8;
test8 = 0;
@ -105,7 +105,7 @@ module t (/*AUTOARG*/);
test8 = test8 + {4'b0,index_a[7:0], 4'h0,index_b[7:0]};
end
endfunction
localparam par8 = test8();
localparam PAR8 = test8();
function [63:0] test9;
test9 = 0;
@ -113,7 +113,7 @@ module t (/*AUTOARG*/);
test9 = crc(test9, index_a, index_b, index_c, 0);
end
endfunction
localparam par9 = test9();
localparam PAR9 = test9();
function [63:0] test10;
test10 = 0;
@ -121,7 +121,7 @@ module t (/*AUTOARG*/);
test10 = crc(test10, index_a, index_b, index_c, index_d);
end
endfunction
localparam par10 = test10();
localparam PAR10 = test10();
function [63:0] test11;
automatic mid_t strarray[3];
@ -135,7 +135,7 @@ module t (/*AUTOARG*/);
foreach (strarray[s].mid.subarray[ss])
test11 += strarray[s].mid.subarray[ss];
endfunction
localparam par11 = test11();
localparam PAR11 = test11();
function [63:0] test12;
test12 = 0;
@ -144,7 +144,7 @@ module t (/*AUTOARG*/);
break;
end
endfunction
localparam par12 = test12();
localparam PAR12 = test12();
function [63:0] test13;
test13 = 0;
@ -154,7 +154,7 @@ module t (/*AUTOARG*/);
test13 += 100;
end
endfunction
localparam par13 = test13();
localparam PAR13 = test13();
function [63:0] test14;
test14 = 0;
@ -163,7 +163,7 @@ module t (/*AUTOARG*/);
break;
end
endfunction
localparam par14 = test14();
localparam PAR14 = test14();
function [63:0] test15;
test15 = 0;
@ -175,7 +175,7 @@ module t (/*AUTOARG*/);
foreach (twod[i, j]); // Null body check
endfunction
localparam par15 = test15();
localparam PAR15 = test15();
function automatic [63:0] test16;
string str1 = "";
@ -184,27 +184,27 @@ module t (/*AUTOARG*/);
test16++;
end
endfunction
localparam par16 = test16();
localparam PAR16 = test16();
initial begin
`checkh(par1, 64'h0);
`checkh(par2, 64'h000000c000000000);
`checkh(par3, 64'h000003601e000000);
`checkh(par4, 64'h00003123fc101000);
`checkh(par5, 64'h0030128ab2a8e557);
`checkh(par6, 64'h0000000006000000);
`checkh(par7, 64'h0000009000000000);
`checkh(par8, 64'h000002704b057073);
`checkh(par9, 64'h00002136f9000000);
`checkh(par10, 64'h0020179aa7aa0aaa);
`checkh(par11, 'h19);
`checkh(PAR1, 64'h0);
`checkh(PAR2, 64'h000000c000000000);
`checkh(PAR3, 64'h000003601e000000);
`checkh(PAR4, 64'h00003123fc101000);
`checkh(PAR5, 64'h0030128ab2a8e557);
`checkh(PAR6, 64'h0000000006000000);
`checkh(PAR7, 64'h0000009000000000);
`checkh(PAR8, 64'h000002704b057073);
`checkh(PAR9, 64'h00002136f9000000);
`checkh(PAR10, 64'h0020179aa7aa0aaa);
`checkh(PAR11, 'h19);
`checkh(par12, 1); // 9
`checkh(par13, 3); // 9, 8, 7
`checkh(PAR12, 1); // 9
`checkh(PAR13, 3); // 9, 8, 7
// See https://www.accellera.org/images/eda/sv-bc/10303.html
`checkh(par14, 1); // 3,9
`checkh(par15, 6);
`checkh(par16, 0);
`checkh(PAR14, 1); // 3,9
`checkh(PAR15, 6);
`checkh(PAR16, 0);
$write("*-* All Finished *-*\n");
$finish;

4
test_regress/t/t_func_defaults.v
View File

@ -5,7 +5,7 @@
// without warranty, 2015 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
parameter logic Bar = 1'b1;
parameter logic BAR = 1'b1;
function automatic logic calc_y;
return 1'b1;
@ -13,7 +13,7 @@ endfunction
function automatic logic [1:0] foo
(
input logic x = Bar,
input logic x = BAR,
input logic y = calc_y()
);
return x + y;

10
test_regress/t/t_func_while.v
View File

@ -4,10 +4,10 @@
// without warranty, 2018 by Julien Margetts.
// SPDX-License-Identifier: CC0-1.0
module t #(parameter sz = 4096)
module t #(parameter SZ = 4096)
(
input wire clk,
output reg [tdw(sz)-1:0] data
output reg [tdw(SZ)-1:0] data
);
// bug1330
@ -19,14 +19,14 @@ module t #(parameter sz = 4096)
tmp = tmp>>1;
endfunction
function integer tdw(input integer sz);
tdw = clog2(sz);
function integer tdw(input integer SZ);
tdw = clog2(SZ);
endfunction
integer b;
always @(posedge clk)
for (b=0; b<tdw(sz); b=b+1)
for (b=0; b<tdw(SZ); b=b+1)
if ((data[b] === 1'bx))
$display("WARNING: %1t Writing X's to tag RAM [%m]", $time);

8
test_regress/t/t_gen_if.v
View File

@ -9,8 +9,8 @@
`timescale 1ns / 1ps
module t(data_i, data_o, single);
parameter op_bits = 32;
input [op_bits -1:0] data_i;
parameter OP_BITS = 32;
input [OP_BITS -1:0] data_i;
output [31:0] data_o;
input single;
@ -23,7 +23,7 @@ module t(data_i, data_o, single);
//simplistic example, should choose 1st conditional generate and assign straight through
//the tool also compiles the special case and determines an error (replication value is 0
generate
if (op_bits == 32) begin : general_case
if (OP_BITS == 32) begin : general_case
assign data_o = data_i;
// Test implicit signals
/* verilator lint_off IMPLICIT */
@ -31,7 +31,7 @@ module t(data_i, data_o, single);
/* verilator lint_on IMPLICIT */
end
else begin : special_case
assign data_o = {{(32 -op_bits){1'b0}},data_i};
assign data_o = {{(32 -OP_BITS){1'b0}},data_i};
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */

4
test_regress/t/t_interface_array_bad.v
View File

@ -30,7 +30,7 @@ module t (/*AUTOARG*/);
//assign baz_inst.7 = 1'b1;
//assign baz_inst.qux_t = 1'b1;
//assign baz_inst.the_func = 1'b1;
//assign baz_inst.the_lp = 1'b1;
//assign baz_inst.THE_LP = 1'b1;
//assign bar.x = 1'b1;
//assign fake_inst.x = 1'b1;
@ -50,5 +50,5 @@ module baz;
return val;
endfunction
localparam the_lp = 5;
localparam THE_LP = 5;
endmodule

4
test_regress/t/t_interface_generic_modport_param.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
interface inf;
localparam lparam = 12;
localparam LPARAM = 12;
int v;
modport mp (
@ -16,7 +16,7 @@ endinterface
module GenericModule (interface.mp a);
initial begin
#1;
if (a.lparam != 12) $stop;
if (a.LPARAM != 12) $stop;
if (a.v != 7) $stop;
end
endmodule

18
test_regress/t/t_interface_localparam.v
View File

@ -6,24 +6,24 @@
interface SimpleIntf
#(
parameter int val = 28
parameter int VAL = 28
)
();
// This value is calculated incorrectly for other instances of
// this interface when it is accessed via the HDL for any other
// instance of this interface
localparam int valDiv2 = val/2;
localparam int valDiv2 = VAL/2;
localparam int valDiv4 = valDiv2/2;
localparam bit mismatch2 = (val != (2*valDiv2) );
localparam bit mismatch4 = (val != (4*valDiv4) );
localparam bit mismatch2 = (VAL != (2*valDiv2) );
localparam bit mismatch4 = (VAL != (4*valDiv4) );
initial begin
$write("%m: val %0d, valDiv2 %0d, mismatch2 %0d\n",
val, valDiv2, mismatch2);
$write("%m: val %0d, valDiv4 %0d, mismatch4 %0d\n",
val, valDiv4, mismatch2);
$write("%m: VAL %0d, valDiv2 %0d, mismatch2 %0d\n",
VAL, valDiv2, mismatch2);
$write("%m: VAL %0d, valDiv4 %0d, mismatch4 %0d\n",
VAL, valDiv4, mismatch2);
if (mismatch2) $stop;
if (mismatch4) $stop;
end
@ -37,7 +37,7 @@ module Core(
// this will constify and valDiv2 will have the default value
localparam valDiv4Upper = intf.valDiv2;
SimpleIntf #(.val(68)) core_intf ();
SimpleIntf #(.VAL(68)) core_intf ();
initial begin
if (intf.valDiv2 != valDiv4Upper) begin

4
test_regress/t/t_interface_param1.v
View File

@ -13,7 +13,7 @@ module t (/*AUTOARG*/
input wire clk;
wire [31:0] result;
test_if #(.id(3)) s();
test_if #(.ID(3)) s();
sub_test U_SUB_TEST(s.a.b, result); // the line causing error
endmodule : t
@ -30,7 +30,7 @@ endmodule
// ---------------------------------------------------------------------------
interface test_if
#(parameter id = 0)
#(parameter ID = 0)
();
typedef struct packed {

4
test_regress/t/t_interface_param_acc_bits.v
View File

@ -10,7 +10,7 @@ interface simple_bus #(PARAMETER = 0);
logic [3:0] mask;
} payload_t;
parameter [6:0] dummy = 22;
parameter [6:0] DUMMY = 22;
payload_t payload;
logic [1:0] x;
endinterface
@ -18,7 +18,7 @@ endinterface
module t ();
simple_bus sb_intf();
localparam LP = $bits(sb_intf.payload.data);
simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple();
simple_bus #(.PARAMETER($bits(sb_intf.DUMMY))) simple();
simple_bus #(.PARAMETER($bits(sb_intf.x))) simple2();
initial begin
if (LP != 32) $stop;

4
test_regress/t/t_lint_width_arraydecl.v
View File

@ -32,13 +32,13 @@ module t(
} bar_s;
// Warning due to concatenation, but this is actually a member assignment
localparam foo_s foo = '{
localparam foo_s FOO = '{
y: (1 << e_0) | (1 << e_3)
, default: '0
};
// No warning
localparam bar_s bar = '{
localparam bar_s BAR = '{
y: (1 << e_0) | (1 << e_3)
};

20
test_regress/t/t_math_pow4.v
View File

@ -54,16 +54,16 @@ module test004(a, y);
wire [7:0] y3;
assign y = {y0,y1,y2,y3};
localparam [7:0] v0 = +8'sd1 ** -8'sd2; //'h01
localparam [7:0] v1 = +8'sd2 ** -8'sd2; //'h00
localparam [7:0] v2 = -8'sd2 ** -8'sd3; //'h00
localparam [7:0] v3 = -8'sd1 ** -8'sd3; //'hff
localparam [7:0] zero = 0;
localparam [7:0] V0 = +8'sd1 ** -8'sd2; //'h01
localparam [7:0] V1 = +8'sd2 ** -8'sd2; //'h00
localparam [7:0] V2 = -8'sd2 ** -8'sd3; //'h00
localparam [7:0] V3 = -8'sd1 ** -8'sd3; //'hff
localparam [7:0] ZERO = 0;
initial $display("v0=%x v1=%x v2=%x v3=%x", v0,v1,v2,v3);
initial $display("V0=%x V1=%x V2=%x V3=%x", V0,V1,V2,V3);
assign y0 = a ? v0 : zero;
assign y1 = a ? v1 : zero;
assign y2 = a ? v2 : zero;
assign y3 = a ? v3 : zero;
assign y0 = a ? V0 : ZERO;
assign y1 = a ? V1 : ZERO;
assign y2 = a ? V2 : ZERO;
assign y3 = a ? V3 : ZERO;
endmodule

32
test_regress/t/t_math_swap.v
View File

@ -20,21 +20,21 @@ module t (/*AUTOARG*/
wire Unsigned = crc[48];
reg rst;
parameter wl = 16;
parameter WL = 16;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [wl-1:0] Quotient; // From test of Test.v
wire [wl-1:0] Remainder; // From test of Test.v
wire [WL-1:0] Quotient; // From test of Test.v
wire [WL-1:0] Remainder; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.Quotient (Quotient[wl-1:0]),
.Remainder (Remainder[wl-1:0]),
.Quotient (Quotient[WL-1:0]),
.Remainder (Remainder[WL-1:0]),
// Inputs
.Operand1 (Operand1[wl*2-1:0]),
.Operand2 (Operand2[wl-1:0]),
.Operand1 (Operand1[WL*2-1:0]),
.Operand2 (Operand2[WL-1:0]),
.clk (clk),
.rst (rst),
.Unsigned (Unsigned));
@ -79,17 +79,17 @@ endmodule
module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder);
parameter wl = 16;
parameter WL = 16;
input [wl*2-1:0] Operand1;
input [wl-1:0] Operand2;
input [WL*2-1:0] Operand1;
input [WL-1:0] Operand2;
input clk, rst, Unsigned;
output [wl-1:0] Quotient, Remainder;
output [WL-1:0] Quotient, Remainder;
reg Cy, Overflow, Sign1, Sign2, Zero, Negative;
reg [wl-1:0] ah,al,Quotient, Remainder;
reg [WL-1:0] ah,al,Quotient, Remainder;
reg [3:0] Iteration;
reg [wl-1:0] sub_quot,op;
reg [WL-1:0] sub_quot,op;
reg ah_ext;
reg [1:0] a,b,c,d,e;
@ -118,8 +118,8 @@ module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder);
op = Operand2;
Cy = 0;
Overflow = 0;
Sign1 = (~Unsigned)&ah[wl-1];
Sign2 = (~Unsigned)&(ah[wl-1]^op[wl-1]);
Sign1 = (~Unsigned)&ah[WL-1];
Sign2 = (~Unsigned)&(ah[WL-1]^op[WL-1]);
if (Sign1) {ah,al} = -{ah,al};
end
`define BUG1
@ -136,7 +136,7 @@ module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder);
$display("%x %x %x %x %x %x %x %x %x",
Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy);
`endif
{Cy,sub_quot} = (~Unsigned)&op[wl-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op};
{Cy,sub_quot} = (~Unsigned)&op[WL-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op};
if (Cy)
begin
{ah_ext,ah} = {1'b0,sub_quot};

16
test_regress/t/t_math_yosys.v
View File

@ -59,16 +59,16 @@ module demo_001(y1, y2, y3, y4);
output [7:0] y1, y2, y3, y4;
// verilator lint_off REALCVT
localparam [7:0] p1 = 123.45;
localparam real p2 = 123.45;
localparam real p3 = 123;
localparam p4 = 123.45;
localparam [7:0] P1 = 123.45;
localparam real P2 = 123.45;
localparam real P3 = 123;
localparam P4 = 123.45;
// verilator lint_off WIDTH
assign y1 = p1 + 0.2;
assign y2 = p2 + 0.2;
assign y3 = p3 + 0.2;
assign y4 = p4 + 0.2;
assign y1 = P1 + 0.2;
assign y2 = P2 + 0.2;
assign y3 = P3 + 0.2;
assign y4 = P4 + 0.2;
// verilator lint_on WIDTH
endmodule

14
test_regress/t/t_param_array2.v
View File

@ -5,17 +5,17 @@
// SPDX-License-Identifier: CC0-1.0
module t;
localparam int c[4] = '{5, 6, 7, 8};
a #(.p(c)) i_a ();
localparam int C[4] = '{5, 6, 7, 8};
a #(.P(C)) i_a ();
endmodule
module a
#( parameter int p[4] = '{1, 2, 3, 4} );
#( parameter int P[4] = '{1, 2, 3, 4} );
initial begin
if (p[0] != 5) $stop;
if (p[1] != 6) $stop;
if (p[2] != 7) $stop;
if (p[3] != 8) $stop;
if (P[0] != 5) $stop;
if (P[1] != 6) $stop;
if (P[2] != 7) $stop;
if (P[3] != 8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end

56
test_regress/t/t_param_array7.v
View File

@ -11,26 +11,26 @@ typedef struct packed {
} s_t;
module t;
localparam int c0 [4] = '{5, 6, 7, 8};
localparam bit [255:0] c1 [4] = '{9, 10, 11, 12};
localparam string c2 [2] = '{"baz", "quux"};
localparam s_t c3 [2] = '{'{a: 100, b: 200, c: 300},
localparam int C0 [4] = '{5, 6, 7, 8};
localparam bit [255:0] C1 [4] = '{9, 10, 11, 12};
localparam string C2 [2] = '{"baz", "quux"};
localparam s_t C3 [2] = '{'{a: 100, b: 200, c: 300},
'{a: 1000, b: 2000, c: 3000}};
a #(
.p0(c0),
.p1(c1),
.p2(c2),
.p3(c3)
.P0(C0),
.P1(C1),
.P2(C2),
.P3(C3)
) i_a ();
endmodule
module a
#(
parameter int p0 [4] = '{1, 2, 3, 4},
parameter bit [255:0] p1 [4] = '{1, 2, 3, 4},
parameter string p2 [2] = '{"foo", "bar"},
parameter s_t p3 [2] = '{'{a: 1, b: 2, c: 3},
parameter int P0 [4] = '{1, 2, 3, 4},
parameter bit [255:0] P1 [4] = '{1, 2, 3, 4},
parameter string P2 [2] = '{"foo", "bar"},
parameter s_t P3 [2] = '{'{a: 1, b: 2, c: 3},
'{a: 1, b: 2, c: 3}}
);
@ -38,22 +38,22 @@ module a
initial begin
// Go via $c to ensure parameters are emitted
i = $c("0"); if (p0[i] != 5) $stop;
i = $c("1"); if (p0[i] != 6) $stop;
i = $c("2"); if (p0[i] != 7) $stop;
i = $c("3"); if (p0[i] != 8) $stop;
i = $c("0"); if (p1[i] != 9) $stop;
i = $c("1"); if (p1[i] != 10) $stop;
i = $c("2"); if (p1[i] != 11) $stop;
i = $c("3"); if (p1[i] != 12) $stop;
i = $c("0"); if (p2[i] != "baz") $stop;
i = $c("1"); if (p2[i] != "quux") $stop;
i = $c("0"); if (p3[i].a != 100) $stop;
i = $c("0"); if (p3[i].b != 200) $stop;
i = $c("0"); if (p3[i].c != 300) $stop;
i = $c("1"); if (p3[i].a != 1000) $stop;
i = $c("1"); if (p3[i].b != 2000) $stop;
i = $c("1"); if (p3[i].c != 3000) $stop;
i = $c("0"); if (P0[i] != 5) $stop;
i = $c("1"); if (P0[i] != 6) $stop;
i = $c("2"); if (P0[i] != 7) $stop;
i = $c("3"); if (P0[i] != 8) $stop;
i = $c("0"); if (P1[i] != 9) $stop;
i = $c("1"); if (P1[i] != 10) $stop;
i = $c("2"); if (P1[i] != 11) $stop;
i = $c("3"); if (P1[i] != 12) $stop;
i = $c("0"); if (P2[i] != "baz") $stop;
i = $c("1"); if (P2[i] != "quux") $stop;
i = $c("0"); if (P3[i].a != 100) $stop;
i = $c("0"); if (P3[i].b != 200) $stop;
i = $c("0"); if (P3[i].c != 300) $stop;
i = $c("1"); if (P3[i].a != 1000) $stop;
i = $c("1"); if (P3[i].b != 2000) $stop;
i = $c("1"); if (P3[i].c != 3000) $stop;
$write("*-* All Finished *-*\n");
$finish;
end

4
test_regress/t/t_param_bit_sel.v
View File

@ -16,8 +16,8 @@ module t (/*AUTOARG*/
input clk;
// At this point it is ambiguous whether a is scalar or vector
parameter a = 1'b0;
wire b = a[0];
parameter A = 1'b0;
wire b = A[0];
// Note however b[0] is illegal.
always @(posedge clk) begin

6
test_regress/t/t_param_const_part.v
View File

@ -17,11 +17,11 @@ module t;
bottom_2_unknown[1:0] = i[1:0];
endfunction
localparam p = bottom_4bits(8'h13);
localparam bu = bottom_2_unknown(8'h13);
localparam P = bottom_4bits(8'h13);
localparam BU = bottom_2_unknown(8'h13);
initial begin
if (p != 3) $stop;
if (P != 3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end

10
test_regress/t/t_param_func.v
View File

@ -8,16 +8,16 @@
// SPDX-License-Identifier: CC0-1.0
module test#(
parameter size = 4,
parameter p = sum({32'h1,32'h2,32'h3,32'h4}, size))
parameter SIZE = 4,
parameter P = sum({32'h1,32'h2,32'h3,32'h4}, SIZE))
(input clk,
input logic sel,
output [p:0] res);
output [P:0] res);
logic [p:0] cc = 'h45;
logic [P:0] cc = 'h45;
assign res = sel ? cc : {(p+1){1'b1}};
assign res = sel ? cc : {(P+1){1'b1}};
function integer sum;
input [3:0][31:0] values;

20
test_regress/t/t_param_in_func.v
View File

@ -70,27 +70,27 @@ function automatic logic [7:0] getUnpacked(logic[3:0] d);
`ifdef NO_INLINE
/* verilator no_inline_task */
`endif
localparam logic [7:0] digits [10] =
localparam logic [7:0] DIGITS [10] =
'{"0", "1", "2", "3", "4", "5", "6", "7", "8", "9"};
return digits[d];
return DIGITS[d];
endfunction
function automatic logic [7:0] getPacked(logic[3:0] d);
`ifdef NO_INLINE
/* verilator no_inline_task */
`endif
localparam logic [9:0][7:0] digits =
localparam logic [9:0][7:0] DIGITS =
{"9", "8", "7", "6", "5", "4", "3", "2", "1", "0"};
return digits[d];
return DIGITS[d];
endfunction
function automatic string getString(logic[3:0] d);
`ifdef NO_INLINE
/* verilator no_inline_task */
`endif
localparam string digits [10] =
localparam string DIGITS [10] =
'{"0", "1", "2", "3", "4", "5", "6", "7", "8", "9"};
return digits[d];
return DIGITS[d];
endfunction
function automatic logic [7:0] getStruct(logic[3:0] d);
@ -102,7 +102,7 @@ function automatic logic [7:0] getStruct(logic[3:0] d);
logic [7:0] result;
longint index;
} lut_t;
localparam lut_t digits [10] =
localparam lut_t DIGITS [10] =
'{
'{result: "1", index: 9},
'{result: "2", index: 0},
@ -115,7 +115,7 @@ function automatic logic [7:0] getStruct(logic[3:0] d);
'{result: "9", index: 7},
'{result: "0", index: 8}
};
return digits[4'(digits[d].index)].result;
return DIGITS[4'(DIGITS[d].index)].result;
endfunction
function automatic logic [7:0] getType(logic[3:0] d);
@ -123,7 +123,7 @@ function automatic logic [7:0] getType(logic[3:0] d);
/* verilator no_inline_task */
`endif
localparam type octet_t = logic [7:0];
localparam octet_t [9:0] digits =
localparam octet_t [9:0] DIGITS =
{"9", "8", "7", "6", "5", "4", "3", "2", "1", "0"};
return digits[d];
return DIGITS[d];
endfunction

6
test_regress/t/t_param_mem_attr.v
View File

@ -24,7 +24,7 @@ module t (/*AUTOARG*/
wire [71:0] ctrl;
wire [7:0] cl; // this line is added
memory #(.words(72)) i_memory (.clk (clk));
memory #(.WORDS(72)) i_memory (.clk (clk));
assign ctrl = i_memory.mem[0];
assign cl = i_memory.mem[0][7:0]; // and this line
@ -35,8 +35,8 @@ endmodule
module memory (clk);
input clk;
parameter words = 16384, bits = 72;
parameter WORDS = 16384, BITS = 72;
reg [bits-1 :0] mem[words-1 : 0];
reg [BITS-1 :0] mem[WORDS-1 : 0];
endmodule

12
test_regress/t/t_param_real2.v
View File

@ -4,7 +4,7 @@
// SPDX-License-Identifier: CC0-1.0
module foo
#( parameter real bar = 2.0)
#( parameter real BAR = 2.0)
();
endmodule
@ -15,16 +15,16 @@ module t();
generate
for (m = 10; m <= 20; m+=10) begin : gen_m
for (r = 0; r <= 1; r++) begin : gen_r
localparam real lparam = m + (r + 0.5);
localparam real LPARAM = m + (r + 0.5);
initial begin
if (lparam != foo_inst.bar) begin
$display("%m: lparam != foo_inst.bar (%f, %f)",
lparam, foo_inst.bar);
if (LPARAM != foo_inst.BAR) begin
$display("%m: LPARAM != foo_inst.BAR (%f, %f)",
LPARAM, foo_inst.BAR);
$stop();
end
end
foo #(.bar (lparam)) foo_inst ();
foo #(.BAR (LPARAM)) foo_inst ();
end
end
endgenerate

2
test_regress/t/t_param_shift.v
View File

@ -21,7 +21,7 @@ module t
wire [95: 0] lfsr_w = 1 >> P;
localparam [95: 0] lfsr_p = 1 >> P;
localparam [95: 0] LFSR_P = 1 >> P;
initial begin
$write("*-* All Finished *-*\n");

6
test_regress/t/t_param_type6.v
View File

@ -23,7 +23,7 @@ module t (/*AUTOARG*/
intf #(.the_type (logic [7:0])) intf_eight();
no_param_intf the_no_param_intf();
sub #(.type_bits (8)) sub_eight (
sub #(.TYPE_BITS (8)) sub_eight (
.intf_pin (intf_eight),
.no_param_intf_pin (the_no_param_intf)
);
@ -36,7 +36,7 @@ module t (/*AUTOARG*/
endmodule
module sub #(
parameter int type_bits
parameter int TYPE_BITS
)(
intf intf_pin,
no_param_intf no_param_intf_pin
@ -45,7 +45,7 @@ module sub #(
localparam type intf_type = type(intf_pin.foo);
localparam type no_param_intf_type = type(no_param_intf_pin.bar);
initial begin
if ($bits(intf_type) != type_bits) $stop();
if ($bits(intf_type) != TYPE_BITS) $stop();
if ($bits(no_param_intf_type) != 14) $stop();
end

4
test_regress/t/t_param_width_loc_bad.out
View File

@ -1,6 +1,6 @@
%Warning-WIDTHTRUNC: t/t_param_width_loc_bad.v:20:21: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
%Warning-WIDTHTRUNC: t/t_param_width_loc_bad.v:20:21: Operator VAR 'PARAM' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
: ... note: In instance 't.test_i'
20 | parameter logic param = 1'b0
20 | parameter logic PARAM = 1'b0
| ^~~~~
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.

4
test_regress/t/t_param_width_loc_bad.v
View File

@ -7,7 +7,7 @@
module t (/*AUTOARG*/);
// bug1624
test #(.param(32'd0)) test_i();
test #(.PARAM(32'd0)) test_i();
initial begin
$write("*-* All Finished *-*\n");
@ -17,6 +17,6 @@ endmodule
module test
#(
parameter logic param = 1'b0
parameter logic PARAM = 1'b0
) ();
endmodule

12
test_regress/t/t_real_param.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
module foo
#( parameter real bar = 2.0)
#( parameter real BAR = 2.0)
();
endmodule
@ -14,16 +14,16 @@ module t();
generate
for (m = 10; m <= 20; m+=10) begin : gen_m
for (r = 0; r <= 1; r++) begin : gen_r
localparam real lparam = m + (r + 0.5);
localparam real LPARAM = m + (r + 0.5);
initial begin
if (lparam != foo_inst.bar) begin
$display("%m: lparam != foo_inst.bar (%f, %f)",
lparam, foo_inst.bar);
if (LPARAM != foo_inst.BAR) begin
$display("%m: LPARAM != foo_inst.BAR (%f, %f)",
LPARAM, foo_inst.BAR);
$stop();
end
end
foo #(.bar (lparam)) foo_inst ();
foo #(.BAR (LPARAM)) foo_inst ();
end
end
endgenerate

4
test_regress/t/t_select_bound1.v
View File

@ -77,11 +77,11 @@ module Test (/*AUTOARG*/
input [2:0] in;
output reg [3:0] out;
output reg [3:0] mask;
localparam [15:5] p = 11'h1ac;
localparam [15:5] P = 11'h1ac;
always @(posedge clk) begin
// verilator lint_off WIDTH
out <= p[15 + in -: 5];
out <= P[15 + in -: 5];
// verilator lint_on WIDTH
end
always @(posedge clk) begin

4
test_regress/t/t_select_bound2.v
View File

@ -77,11 +77,11 @@ module Test (/*AUTOARG*/
input [6:0] in; // Note much wider than any index
output reg [3:0] out;
output reg [3:0] mask;
localparam [15:5] p = 11'h1ac;
localparam [15:5] P = 11'h1ac;
always @(posedge clk) begin
// verilator lint_off WIDTH
out <= p[15 + in -: 5];
out <= P[15 + in -: 5];
// verilator lint_on WIDTH
mask[3] <= ((15 + in - 5) < 12);
mask[2] <= ((15 + in - 5) < 13);

6
test_regress/t/t_split_var_0.v
View File

@ -151,13 +151,13 @@ module barshift_1d_unpacked_struct1 #(parameter DEPTH = 2, localparam WIDTH = 2*
typedef struct packed { int data; } data_type;
data_type tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/;
localparam [32-WIDTH-1:0] pad = 0;
localparam [32-WIDTH-1:0] PAD = 0;
generate
for(genvar i = 0; i < DEPTH; ++i) begin
always_comb
if (shift[i]) begin
/*verilator lint_off ALWCOMBORDER*/
tmp[i+1+OFFSET] = {pad, tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]};
tmp[i+1+OFFSET] = {PAD, tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]};
/*verilator lint_on ALWCOMBORDER*/
end
else begin
@ -165,7 +165,7 @@ module barshift_1d_unpacked_struct1 #(parameter DEPTH = 2, localparam WIDTH = 2*
end
end
endgenerate
assign tmp[0+OFFSET] = {pad, in};
assign tmp[0+OFFSET] = {PAD, in};
logic _dummy;
always_comb {_dummy, out[WIDTH-1:1], out[0]} = tmp[DEPTH+OFFSET][WIDTH:0];
endmodule

2767
test_regress/t/t_split_var_2_trace.out
View File

File diff suppressed because it is too large Load Diff

6
test_regress/t/t_struct_array.v
View File

@ -26,10 +26,10 @@ module t(clk);
endmodule
module sub(a_out);
parameter n = 4;
output TEST_TYPES::a_struct_t [n-1:0] a_out;
parameter N = 4;
output TEST_TYPES::a_struct_t [N-1:0] a_out;
always_comb begin
for (int i=0;i<n;i++)
for (int i=0;i<N;i++)
a_out[i].stuff = i[0];
end
endmodule

8
test_regress/t/t_struct_pat_width.v
View File

@ -13,14 +13,14 @@ module t (clk);
logic [2:0] meh;
struct_t param;
localparam integer twentyone = 21;
localparam integer TWENTYONE = 21;
// verilator lint_off WIDTH
assign param = '{
_foo: twentyone % 8 + 1,
_bar: (twentyone / 8) + 1
_foo: TWENTYONE % 8 + 1,
_bar: (TWENTYONE / 8) + 1
};
assign meh = twentyone % 8 + 1;
assign meh = TWENTYONE % 8 + 1;
// verilator lint_on WIDTH
always @ (posedge clk) begin

4
test_regress/t/t_vams_wreal.v
View File

@ -51,9 +51,9 @@ module t (/*autoarg*/
first_level first_level(.in(cyc[0]), .out(wreal_implicit_net));
// verilator lint_on IMPLICIT
parameter real lsb = 1;
parameter real LSB = 1;
// verilator lint_off WIDTH
assign aout = $itor(in) * lsb;
assign aout = $itor(in) * LSB;
// verilator lint_on WIDTH
always @ (posedge clk) begin

6
test_regress/t/t_var_init.v
View File

@ -11,14 +11,14 @@ module t (/*AUTOARG*/
input clk;
parameter [31:0] p2=2, p3=3;
parameter [31:0] P2=2, P3=3;
integer i2=2, i3=3;
reg [31:0] r2=2, r3=3;
wire [31:0] w2=2, w3=3;
always @ (posedge clk) begin
if (p2 !== 2) $stop;
if (p3 !== 3) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
if (i2 !== 2) $stop;
if (i3 !== 3) $stop;
if (r2 !== 2) $stop;

8
test_regress/t/t_vpi_dump.out
View File

@ -1,17 +1,17 @@
t (vpiModule) t vpiDefName=t
vpiReg:
DO_GENERATE (vpiParameter) t.DO_GENERATE vpiConstType=vpiDecConst
LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND (vpiReg) t.LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND
LONG_INT (vpiParameter) t.LONG_INT vpiConstType=vpiDecConst
a (vpiReg) TOP.a
bus1 (vpiReg) t.bus1
clk (vpiReg) TOP.clk
count (vpiReg) t.count
do_generate (vpiParameter) t.do_generate vpiConstType=vpiDecConst
fourthreetwoone (vpiRegArray) t.fourthreetwoone
vpiReg:
fourthreetwoone (vpiReg) t.fourthreetwoone[3]
fourthreetwoone (vpiReg) t.fourthreetwoone[4]
half_count (vpiReg) t.half_count
long_int (vpiParameter) t.long_int vpiConstType=vpiDecConst
onebit (vpiReg) t.onebit
quads (vpiRegArray) t.quads
vpiReg:
@ -28,8 +28,8 @@ t (vpiModule) t vpiDefName=t
twoone (vpiReg) t.twoone
x (vpiReg) TOP.x
vpiParameter:
do_generate (vpiParameter) t.do_generate vpiConstType=vpiDecConst
long_int (vpiParameter) t.long_int vpiConstType=vpiDecConst
DO_GENERATE (vpiParameter) t.DO_GENERATE vpiConstType=vpiDecConst
LONG_INT (vpiParameter) t.LONG_INT vpiConstType=vpiDecConst
vpiInternalScope:
arr[1] (vpiGenScope) t.arr[1]
vpiReg:

6
test_regress/t/t_vpi_dump.v
View File

@ -31,8 +31,8 @@ module t ( /*AUTOARG*/
);
parameter int do_generate = 1;
parameter longint long_int = 64'h123456789abcdef;
parameter int DO_GENERATE = 1;
parameter longint LONG_INT = 64'h123456789abcdef;
input clk;
@ -100,7 +100,7 @@ module t ( /*AUTOARG*/
generate
if (do_generate == 1) begin : cond_scope
if (DO_GENERATE == 1) begin : cond_scope
ModSub scoped_sub ();
parameter int scoped_wire = 1;