Commentary: Changes update

Changes

@@ -18,12 +18,14 @@ Verilator 5.039 devel
 * Add SPECIFYIGN warning for specify constructs that were previously silently ignored.
 * Add enum base data type, and wire data type checking per IEEE.
 * Add error on missing forward declarations (#6206). [Alex Solomatnikov]
+* Add error when trying to assign class object to variable of non-class types (#6237). [Igor Zaworski, Antmicro Ltd.]
 * Add `-DVERILATOR=1` definition to compiler flags when using verilated.mk.
 * Support member-level triggers for virtual interfaces (#5166) (#6148). [Yilou Wang]
 * Support randomization of scope variables with 'std::randomize()' (#5438) (#6185). [Yilou Wang]
 * Support disabling a fork in additional contexts (#5432 partial) (#6174) (#6183). [Ryszard Rozak, Antmicro Ltd.]
 * Support bit queue streaming (#5830) (#6103). [Paul Swirhun]
 * Support Verilog real ports as SystemC double ports (#6136) (#6158). [George Polack]
+* Support `$countones` in constraints (#6144 partial) (#6235). [Ryszard Rozak, Antmicro Ltd.]
 * Support disable dotted references (#6154). [Ryszard Rozak, Antmicro Ltd.]
 * Support randomize() on class member selects (#6161) (#6195). [Igor Zaworski, Ryszard Rozak, Antmicro Ltd.]
 * Support multiple variables on RHS of a `force` assignment (#6163). [Artur Bieniek, Antmicro Ltd.]
@@ -57,6 +59,7 @@ Verilator 5.039 devel
 * Fix MODDUP with duplicate packages to take first package (#6222).
 * Fix replicate with unsigned count but MSB set (#6231) (#6233). [Geza Lore]
 * Fix queue typedef with unbounded slice (#6236).
+* Fix error when force assignment is used with ref function args (#6244). [Ryszard Rozak, Antmicro Ltd.]
 
 
 Verilator 5.038 2025-07-08