Support non-ansi ports with `wire` before `input`

src/V3AstNodeOther.h

@@ -2315,17 +2315,7 @@ public:
         declDirection(fromp->declDirection());
         lifetime(fromp->lifetime());
     }
-    void combineType(const AstVar* typevarp) {
-        // This is same as typevarp (for combining input & reg decls)
-        // "this" is the input var. typevarp is the reg var.
-        propagateAttrFrom(typevarp);
-        combineType(typevarp->varType());
-        if (typevarp->isSigPublic()) sigPublic(true);
-        if (typevarp->isSigModPublic()) sigModPublic(true);
-        if (typevarp->isSigUserRdPublic()) sigUserRdPublic(true);
-        if (typevarp->isSigUserRWPublic()) sigUserRWPublic(true);
-        if (typevarp->attrScClocked()) attrScClocked(true);
-    }
+    void combineType(const AstVar* otherp);
     void inlineAttrReset(const string& name) {
         if (direction() == VDirection::INOUT && varType() == VVarType::WIRE) {
             m_varType = VVarType::TRIWIRE;

src/V3AstNodes.cpp

@@ -489,7 +489,20 @@ bool AstVar::isScBigUint() const {
     return ((isSc() && v3Global.opt.pinsScBigUint() && width() >= 65 && width() <= 512)
             && !isScBv());
 }
-
+void AstVar::combineType(const AstVar* otherp) {
+    // "this" is the port var. otherp is the reg var, or vice-versa
+    propagateAttrFrom(otherp);
+    combineType(otherp->varType());
+    if (otherp->isSigPublic()) sigPublic(true);
+    if (otherp->isSigModPublic()) sigModPublic(true);
+    if (otherp->isSigUserRdPublic()) sigUserRdPublic(true);
+    if (otherp->isSigUserRWPublic()) sigUserRWPublic(true);
+    if (otherp->attrScClocked()) attrScClocked(true);
+    if (otherp->varType() == VVarType::PORT) {
+        varType(otherp->varType());
+        direction(otherp->direction());
+    }
+}
 void AstVar::combineType(VVarType type) {
     // These flags get combined with the existing settings of the flags.
     // We don't test varType for certain types, instead set flags since

test_regress/t/t_inst_nansi.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_inst_nansi.v

@@ -0,0 +1,33 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(b, si, i, li, w3, w4);
+  output b;  // Output before type
+  output si;
+  byte b;
+  shortint si;
+
+  int i;
+  longint li;
+  output i;  // Output after type
+  output li;
+
+  input w3;
+  wire [2:0] w3;
+  wire [3:0] w4;
+  input w4;
+
+  initial begin
+    if ($bits(b) != 8) $stop;
+    if ($bits(si) != 16) $stop;
+    if ($bits(i) != 32) $stop;
+    if ($bits(li) != 64) $stop;
+    if ($bits(w3) != 3) $stop;
+    if ($bits(w4) != 4) $stop;
+    $finish;
+  end
+
+endmodule