Fix DFG removing forceable signals (#4942)
DFG could remove forceable signals by replacing them with their in-design driver. This is a bit of a pain to prevent, and ideally the forcing transform should happen before DFG, but implementing it there is a pain due to having to rewrite ports based on direction. This is an attempted fix in DFG. More cases might remain.
This commit is contained in:
Geza Lore
GitHub
parent
0fbd4313b2
commit
745605efe3
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@ -439,11 +439,14 @@ class AstToDfgVisitor final : public VNVisitor {
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if (nodep->isSc()) return;
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// No need to (and in fact cannot) handle variables with unsupported dtypes
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if (!DfgVertex::isSupportedDType(nodep->dtypep())) return;
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// Mark ports as having external references
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if (nodep->isIO()) getNet(nodep)->setHasExtRefs();
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// Mark variables that are the target of a hierarchical reference
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// (these flags were set up in DataflowPrepVisitor)
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if (nodep->user2()) getNet(nodep)->setHasExtRefs();
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// Mark variables with external references
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if (nodep->isIO() // Ports
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|| nodep->user2() // Target of a hierarchical reference
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|| nodep->isForceable() // Forceable
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) {
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getNet(nodep)->setHasExtRefs();
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}
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}
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void visit(AstAssignW* nodep) override {
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@ -167,9 +167,14 @@ void V3DfgPasses::inlineVars(const DfgGraph& dfg) {
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if (varp->hasSinks() && varp->isDrivenFullyByDfg() && !varp->varp()->isSc()) {
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DfgVertex* const driverp = varp->source(0);
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// If driven from a SystemC variable, don't inline this variable
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// We must keep the original driver in certain cases, when swapping them would
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// not be functionally or technically (implementation reasons) equivalent
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if (DfgVertexVar* const driverVarp = driverp->cast<DfgVarPacked>()) {
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if (driverVarp->varp()->isSc()) continue;
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const AstVar* const varp = driverVarp->varp();
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// If driven from a SystemC variable
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if (varp->isSc()) continue;
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// If the variable is forceable
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if (varp->isForceable()) continue;
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}
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varp->forEachSinkEdge([=](DfgEdge& edge) {
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@ -248,7 +248,9 @@ public:
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: DfgVertexVar{dfg, dfgType(), varp, 1u} {}
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ASTGEN_MEMBERS_DfgVarPacked;
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bool isDrivenFullyByDfg() const { return arity() == 1 && source(0)->dtypep() == dtypep(); }
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bool isDrivenFullyByDfg() const {
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return arity() == 1 && source(0)->dtypep() == dtypep() && !varp()->isForceable();
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}
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void addDriver(FileLine* flp, uint32_t lsb, DfgVertex* vtxp) {
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m_driverData.emplace_back(flp, lsb);
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@ -32,41 +32,44 @@ module t (
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assign net_1 = ~cyc[0];
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assign net_8 = ~cyc[1 +: 8];
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wire obs_1 = net_1;
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wire [7:0] obs_8 = net_8;
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always @ (posedge clk) begin
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$display("%d: %x %x", cyc, net_8, net_1);
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$display("%d: %x %x", cyc, obs_8, obs_1);
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if (!rst) begin
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case (cyc)
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3: begin
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`checkh (net_1, 0);
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`checkh (net_8, ~cyc[1 +: 8]);
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`checkh (obs_1, 0);
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`checkh (obs_8, ~cyc[1 +: 8]);
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end
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4: begin
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`checkh (net_1, 0);
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`checkh (net_8, 8'h5f);
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`checkh (obs_1, 0);
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`checkh (obs_8, 8'h5f);
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end
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5: begin
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`checkh (net_1, 1);
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`checkh (net_8, 8'h5f);
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`checkh (obs_1, 1);
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`checkh (obs_8, 8'h5f);
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end
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6, 7: begin
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`checkh (net_1, 1);
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`checkh (net_8, 8'hf5);
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`checkh (obs_1, 1);
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`checkh (obs_8, 8'hf5);
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end
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8: begin
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`checkh (net_1, ~cyc[0]);
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`checkh (net_8, 8'hf5);
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`checkh (obs_1, ~cyc[0]);
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`checkh (obs_8, 8'hf5);
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end
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10, 11: begin
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`checkh (net_1, 1);
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`checkh (net_8, 8'h5a);
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`checkh (obs_1, 1);
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`checkh (obs_8, 8'h5a);
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end
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12, 13: begin
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`checkh (net_1, 0);
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`checkh (net_8, 8'ha5);
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`checkh (obs_1, 0);
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`checkh (obs_8, 8'ha5);
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end
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default: begin
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`checkh ({net_8, net_1}, ~cyc[0 +: 9]);
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`checkh ({obs_8, obs_1}, ~cyc[0 +: 9]);
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end
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endcase
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end
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@ -1,6 +1,5 @@
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$version Generated by VerilatedVcd $end
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$timescale 1ps $end
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$scope module top $end
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$var wire 1 # clk $end
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$var wire 1 $ rst $end
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@ -11,6 +10,8 @@ $timescale 1ps $end
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$var wire 32 % cyc [31:0] $end
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$var wire 1 & net_1 $end
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$var wire 8 ' net_8 [7:0] $end
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$var wire 1 & obs_1 $end
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$var wire 8 ' obs_8 [7:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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@ -21,6 +21,19 @@ module t (
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end
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end
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reg tmp_1;
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reg [7:0] tmp_8;
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always @(posedge clk) begin
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if (rst) begin
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tmp_1 <= 0;
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tmp_8 <= 0;
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end else begin
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tmp_1 <= cyc[0];
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tmp_8 <= cyc[1 +: 8];
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end
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end
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`ifdef CMT
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reg var_1 /* verilator forceable */;
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reg [7:0] var_8 /* verilator forceable */;
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@ -29,55 +42,54 @@ module t (
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reg [7:0] var_8;
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`endif
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always @(posedge clk) begin
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if (rst) begin
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var_1 <= 0;
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var_8 <= 0;
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end else begin
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var_1 <= cyc[0];
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var_8 <= cyc[1 +: 8];
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end
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end
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always @* var_1 = tmp_1;
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always @* var_8 = tmp_8;
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reg obs_1;
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reg [7:0] obs_8;
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always @* obs_1 = var_1;
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always @* obs_8 = var_8;
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always @ (posedge clk) begin
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$display("%d: %x %x", cyc, var_8, var_1);
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$display("%d: %x %x", cyc, obs_8, obs_1);
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if (!rst) begin
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case (cyc)
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0: begin // Reset values
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`checkh (var_1, 0);
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`checkh (var_8, 0);
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`checkh (obs_1, 0);
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`checkh (obs_8, 0);
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end
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13: begin
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`checkh (var_1, 1);
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`checkh ({1'b0, var_8}, (cyc[0 +: 9] - 1) >> 1);
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`checkh (obs_1, 1);
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`checkh ({1'b0, obs_8}, (cyc[0 +: 9] - 1) >> 1);
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end
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14: begin
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`checkh (var_1, 1);
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`checkh (var_8, 8'hf5);
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`checkh (obs_1, 1);
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`checkh (obs_8, 8'hf5);
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end
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15: begin
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`checkh (var_1, 0);
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`checkh (var_8, 8'hf5);
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`checkh (obs_1, 0);
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`checkh (obs_8, 8'hf5);
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end
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16, 17: begin
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`checkh (var_1, 0);
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`checkh (var_8, 8'h5f);
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`checkh (obs_1, 0);
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`checkh (obs_8, 8'h5f);
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end
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18: begin
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`checkh (var_1, ~cyc[0]);
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`checkh (var_8, 8'h5f);
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`checkh (obs_1, ~cyc[0]);
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`checkh (obs_8, 8'h5f);
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end
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20, 21: begin
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`checkh (var_1, 1);
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`checkh (var_8, 8'h5a);
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`checkh (obs_1, 1);
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`checkh (obs_8, 8'h5a);
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end
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22, 23: begin
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`checkh (var_1, 0);
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`checkh (var_8, 8'ha5);
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`checkh (obs_1, 0);
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`checkh (obs_8, 8'ha5);
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end
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default: begin
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`checkh ({var_8, var_1}, cyc[0 +: 9] - 1);
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`checkh ({obs_8, obs_1}, cyc[0 +: 9] - 1);
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end
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endcase
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end
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@ -1,6 +1,5 @@
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$version Generated by VerilatedVcd $end
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$timescale 1ps $end
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$scope module top $end
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$var wire 1 # clk $end
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$var wire 1 $ rst $end
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@ -9,8 +8,12 @@ $timescale 1ps $end
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$var wire 1 # clk $end
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$var wire 1 $ rst $end
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$var wire 32 % cyc [31:0] $end
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$var wire 1 & var_1 $end
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$var wire 8 ' var_8 [7:0] $end
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$var wire 1 & tmp_1 $end
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$var wire 8 ' tmp_8 [7:0] $end
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$var wire 1 ( var_1 $end
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$var wire 8 ) var_8 [7:0] $end
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$var wire 1 ( obs_1 $end
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$var wire 8 ) obs_8 [7:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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@ -22,6 +25,8 @@ $enddefinitions $end
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b00000000000000000000000000000000 %
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0&
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b00000000 '
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0(
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b00000000 )
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#5
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1#
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0$
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@ -36,6 +41,7 @@ b00000000000000000000000000000001 %
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1#
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b00000000000000000000000000000010 %
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1&
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1(
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#30
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0#
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#35
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@ -43,12 +49,15 @@ b00000000000000000000000000000010 %
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b00000000000000000000000000000011 %
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0&
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b00000001 '
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0(
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b00000001 )
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#40
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0#
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#45
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1#
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b00000000000000000000000000000100 %
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1&
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1(
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#50
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0#
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#55
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@ -56,12 +65,15 @@ b00000000000000000000000000000100 %
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b00000000000000000000000000000101 %
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0&
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b00000010 '
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0(
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b00000010 )
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#60
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0#
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#65
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1#
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b00000000000000000000000000000110 %
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1&
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1(
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#70
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0#
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#75
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@ -69,12 +81,15 @@ b00000000000000000000000000000110 %
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b00000000000000000000000000000111 %
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0&
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b00000011 '
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0(
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b00000011 )
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#80
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0#
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#85
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1#
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b00000000000000000000000000001000 %
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1&
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1(
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#90
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0#
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#95
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@ -82,12 +97,15 @@ b00000000000000000000000000001000 %
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b00000000000000000000000000001001 %
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0&
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b00000100 '
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0(
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b00000100 )
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#100
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0#
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#105
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1#
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b00000000000000000000000000001010 %
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1&
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1(
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#110
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0#
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#115
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@ -95,47 +113,59 @@ b00000000000000000000000000001010 %
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b00000000000000000000000000001011 %
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0&
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b00000101 '
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0(
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b00000101 )
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#120
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0#
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#125
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1#
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b00000000000000000000000000001100 %
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1&
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1(
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#130
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0#
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#135
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1#
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b00000000000000000000000000001101 %
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0&
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b00000110 '
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b00000110 )
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#140
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0#
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#145
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1#
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b00000000000000000000000000001110 %
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b11110101 '
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1&
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b11110101 )
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#150
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0#
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#155
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1#
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b00000000000000000000000000001111 %
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0&
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b00000111 '
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0(
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#160
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0#
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#165
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1#
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b00000000000000000000000000010000 %
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b01011111 '
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1&
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b01011111 )
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#170
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0#
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#175
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1#
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b00000000000000000000000000010001 %
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0&
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b00001000 '
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#180
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0#
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#185
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1#
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b00000000000000000000000000010010 %
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1&
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1(
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#190
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0#
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#195
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@ -143,37 +173,46 @@ b00000000000000000000000000010010 %
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b00000000000000000000000000010011 %
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0&
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b00001001 '
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0(
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b00001001 )
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#200
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0#
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#205
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1#
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b00000000000000000000000000010100 %
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1&
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b01011010 '
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1(
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b01011010 )
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#210
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0#
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#215
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1#
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b00000000000000000000000000010101 %
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0&
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b00001010 '
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#220
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0#
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#225
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1#
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b00000000000000000000000000010110 %
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0&
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b10100101 '
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1&
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0(
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b10100101 )
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#230
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0#
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#235
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1#
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b00000000000000000000000000010111 %
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0&
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b00001011 '
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#240
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0#
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#245
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1#
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b00000000000000000000000000011000 %
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1&
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b00001011 '
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1(
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b00001011 )
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#250
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0#
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#255
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@ -181,12 +220,15 @@ b00001011 '
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b00000000000000000000000000011001 %
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0&
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b00001100 '
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0(
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b00001100 )
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#260
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0#
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#265
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1#
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b00000000000000000000000000011010 %
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1&
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1(
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#270
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0#
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#275
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@ -194,12 +236,15 @@ b00000000000000000000000000011010 %
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b00000000000000000000000000011011 %
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0&
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b00001101 '
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0(
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b00001101 )
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#280
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0#
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#285
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1#
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b00000000000000000000000000011100 %
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1&
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1(
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#290
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0#
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#295
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@ -207,12 +252,15 @@ b00000000000000000000000000011100 %
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b00000000000000000000000000011101 %
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0&
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b00001110 '
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0(
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b00001110 )
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#300
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0#
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#305
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1#
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b00000000000000000000000000011110 %
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1&
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1(
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#310
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0#
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#315
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@ -220,3 +268,5 @@ b00000000000000000000000000011110 %
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b00000000000000000000000000011111 %
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0&
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b00001111 '
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0(
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b00001111 )
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