luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix wrong fileline on 1step

This commit is contained in:
Wilson Snyder 2025-02-25 20:40:33 -05:00
parent 6a8f97e184
commit b52e1d3ede
2 changed files with 4 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/verilog.l
View File

@ -653,7 +653,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
<VA5,SAX>{
/* Generic unsupported warnings */
"1step" { FL; return ya1STEP; }
"1step" { FL; return y1STEP; }
"above" { ERROR_RSVD_WORD("AMS"); }
"abs" { ERROR_RSVD_WORD("AMS"); }
"absdelay" { ERROR_RSVD_WORD("AMS"); }
@ -964,9 +964,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
FL; yylval.cdouble = V3ParseImp::lexParseTimenum(yytext);
return yaTIMENUM;
}
1step {
return ya1STEP;
}
1step { FL; return y1STEP; }
}
/************************************************************************/

4
src/verilog.y
View File

@ -545,7 +545,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
// for example yP_ for punctuation based operators.
// Double underscores "yX__Y" means token X followed by Y,
// and "yX__ETC" means X folled by everything but Y(s).
%token<fl> ya1STEP "1step"
%token<fl> y1STEP "1step"
%token<fl> yACCEPT_ON "accept_on"
%token<fl> yALIAS "alias"
%token<fl> yALWAYS "always"
@ -6077,7 +6077,7 @@ clocking_skewE<nodeExprp>: // IEEE: [clocking_skew]
clocking_skew<nodeExprp>: // IEEE: clocking_skew
delay_control { $$ = $1->lhsp()->unlinkFrBack(); $1->deleteTree(); }
| '#' ya1STEP { $$ = new AstConst{$<fl>1, AstConst::OneStep{}}; }
| '#' y1STEP { $$ = new AstConst{$<fl>1, AstConst::OneStep{}}; }
| yPOSEDGE delay_controlE { $$ = nullptr;
BBUNSUP($1, "Unsupported: clocking event edge override"); }
| yNEGEDGE delay_controlE { $$ = nullptr;