Tests: Add test for unfixed (#4038)

test_regress/t/t_unroll_delay.out

@@ -0,0 +1,18 @@
+
+[0] A 1 6
+[0] B 0 0
+[1] C 1 6
+[1] A 1 7
+[1] B 0 7
+[2] C 1 7
+[2] B 0 8
+
+[11] A 2 6
+[11] B 2 8
+[12] C 2 6
+[12] A 2 7
+[12] B 2 7
+[13] C 2 7
+[13] B 2 8
+[22] B 3 8
+*-* All Finished *-*

test_regress/t/t_unroll_delay.pl

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+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['--binary --timing --trace'],
+    verilator_make_cmake => 0,
+    verilator_make_gmake => 0,
+    make_main => 0,
+    );
+
+execute(
+    check_finished => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_unroll_delay.v

@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+   integer i;
+   integer j;
+
+   always @(i, j) $display("[%0t] B %0d %0d", $time, i, j);
+
+   // See issue #4237
+   initial begin
+      for(i = 1; i < 3 ; i = i + 1) begin
+         $display("");
+         for(j = 6; j < 8; j = j + 1) begin
+            $display("[%0t] A %0d %0d", $time, i, j);
+            #1;
+            $display("[%0t] C %0d %0d", $time, i, j);
+         end
+         #9;
+      end
+      #10;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule