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Improve `resetall support (#5728) (#5730)

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Ethan Sifferman 2025-01-11 19:53:11 -08:00 committed by GitHub
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commit dc43071f1c
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1 changed files with 5 additions and 1 deletions
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src/verilog.l
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@ -1062,7 +1062,11 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"`protect" { FL_FWD; FL_BRK; }
"`remove_gatenames" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
"`remove_netnames" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
"`resetall" { FL; PARSEP->lexFileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true);
"`resetall" { FL;
PARSEP->lexFileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true);
v3Global.rootp()->timeInit();
PARSEP->lexFileline()->celldefineOn(false);
PARSEP->unconnectedDrive(VOptionBool::OPT_DEFAULT_FALSE);
return yaT_RESETALL; } // Rest handled by preproc
"`suppress_faults" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
"`timescale"{ws}+[^\n\r]* { FL; PARSEP->lexTimescaleParse(yylval.fl,