Fix upcasting class type parameters (#6344)
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
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@ -1337,7 +1337,8 @@ public:
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}
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void visit(AstCCast* nodep) override {
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// Extending a value of the same word width is just a NOP.
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if (const AstClassRefDType* const classDtypep = VN_CAST(nodep->dtypep(), ClassRefDType)) {
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if (const AstClassRefDType* const classDtypep
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= VN_CAST(nodep->dtypep()->skipRefp(), ClassRefDType)) {
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putns(nodep, "(" + classDtypep->cType("", false, false) + ")(");
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} else if (nodep->size() <= VL_BYTESIZE) {
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putns(nodep, "(CData)(");
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.passes()
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@ -0,0 +1,33 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class factory #(type T);
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static function T create;
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T obj = new;
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return obj;
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endfunction
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endclass
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class foo;
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endclass
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class bar extends foo;
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static function bar create;
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bar b = new;
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return b;
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endfunction
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endclass
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module t;
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initial begin
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foo f;
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if (bit'($random))
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f = bar::create;
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else
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f = factory#(foo)::create();
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$finish;
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end
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endmodule;
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