Commentary

2026-10-02 16:13:34 +02:00 · 2024-01-05 07:14:40 -05:00
parent 1a0c8f1573
commit 47b129bf07
1 changed files with 1 additions and 0 deletions
@@ -971,6 +971,7 @@ void VerilatedContext::timeprecision(int value) VL_MT_SAFE {
        } else if (sc_res == sc_core::sc_time(1, sc_core::SC_FS)) {
            sc_prec = 15;
        }
+        // SC_AS, SC_ZS, SC_YS not supported as no Verilog equivalent; will error below
 #endif
    }
 #if VM_SC