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Revert 'Fix --x-initial and --x-assign random stability (#2662) (#5958).' See (#6018). 

Reverts 4581023805 plus line in Changes file
This commit is contained in:
Wilson Snyder 2025-05-17 20:27:03 -04:00
parent 647404ec1e
commit 640339ec36
36 changed files with 45 additions and 675 deletions
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1
Changes
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@ -18,7 +18,6 @@ Verilator 5.037 devel
* Support SARIF JSON diagnostic output with `--diagnostics-sarif`. (#6017)
* Add BADVLTPRAGMA on unknown Verilator pragmas (#5945). [Shou-Li Hsu]
* Add PROCINITASSIGN on initial assignments to process variables (#2481). [Niraj Menon]
* Fix --x-initial and --x-assign random stability (#2662) (#5958). [Todd Strader]
* Fix filename backslash escapes in C code (#5947).
* Fix C++ widths in V3Expand (#5953) (#5975). [Geza Lore]
* Fix dependencies from different hierarchical schedules (#5954). [Bartłomiej Chmiel, Antmicro Ltd.]

74
include/verilated.cpp
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@ -406,38 +406,6 @@ IData VL_URANDOM_SEEDED_II(IData seed) VL_MT_SAFE {
Verilated::threadContextp()->randSeed(static_cast<int>(seed));
return VL_RANDOM_I();
}
IData VL_SCOPED_RAND_RESET_I(int obits, uint64_t scopeHash, uint64_t salt) VL_MT_UNSAFE {
if (Verilated::threadContextp()->randReset() == 0) return 0;
IData data = ~0;
if (Verilated::threadContextp()->randReset() != 1) { // if 2, randomize
VlRNG rng(Verilated::threadContextp()->randSeed() ^ scopeHash ^ salt);
data = rng.rand64();
}
data &= VL_MASK_I(obits);
return data;
}
QData VL_SCOPED_RAND_RESET_Q(int obits, uint64_t scopeHash, uint64_t salt) VL_MT_UNSAFE {
if (Verilated::threadContextp()->randReset() == 0) return 0;
QData data = ~0ULL;
if (Verilated::threadContextp()->randReset() != 1) { // if 2, randomize
VlRNG rng(Verilated::threadContextp()->randSeed() ^ scopeHash ^ salt);
data = rng.rand64();
}
data &= VL_MASK_Q(obits);
return data;
}
WDataOutP VL_SCOPED_RAND_RESET_W(int obits, WDataOutP outwp, uint64_t scopeHash,
uint64_t salt) VL_MT_UNSAFE {
if (Verilated::threadContextp()->randReset() != 2) { return VL_RAND_RESET_W(obits, outwp); }
VlRNG rng(Verilated::threadContextp()->randSeed() ^ scopeHash ^ salt);
for (int i = 0; i < VL_WORDS_I(obits) - 1; ++i) outwp[i] = rng.rand64();
outwp[VL_WORDS_I(obits) - 1] = rng.rand64() & VL_MASK_E(obits);
return outwp;
}
IData VL_RAND_RESET_I(int obits) VL_MT_SAFE {
if (Verilated::threadContextp()->randReset() == 0) return 0;
IData data = ~0;
@ -1732,48 +1700,6 @@ IData VL_SSCANF_INNX(int, const std::string& ld, const std::string& format, int
return got;
}
// MurmurHash64A
uint64_t VL_HASH(const char* key) VL_PURE {
const size_t len = strlen(key);
const uint64_t seed = 0;
const uint64_t m = 0xc6a4a7935bd1e995ULL;
const int r = 47;
uint64_t h = seed ^ (len * m);
const uint64_t* data = (const uint64_t*)key;
const uint64_t* end = data + (len / 8);
while (data != end) {
uint64_t k = *data++;
k *= m;
k ^= k >> r;
k *= m;
h ^= k;
h *= m;
}
const unsigned char* data2 = (const unsigned char*)data;
switch (len & 7) {
case 7: h ^= uint64_t(data2[6]) << 48; /* fallthrough */
case 6: h ^= uint64_t(data2[5]) << 40; /* fallthrough */
case 5: h ^= uint64_t(data2[4]) << 32; /* fallthrough */
case 4: h ^= uint64_t(data2[3]) << 24; /* fallthrough */
case 3: h ^= uint64_t(data2[2]) << 16; /* fallthrough */
case 2: h ^= uint64_t(data2[1]) << 8; /* fallthrough */
case 1: h ^= uint64_t(data2[0]); h *= m; /* fallthrough */
};
h ^= h >> r;
h *= m;
h ^= h >> r;
return h;
}
IData VL_FREAD_I(int width, int array_lsb, int array_size, void* memp, IData fpi, IData start,
IData count) VL_MT_SAFE {
// While threadsafe, each thread can only access different file handles

10
include/verilated_funcs.h
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@ -101,14 +101,6 @@ inline IData VL_URANDOM_RANGE_I(IData hi, IData lo) {
}
}
/// Random reset a signal of given width (init time only, var-specific PRNG)
extern IData VL_SCOPED_RAND_RESET_I(int obits, uint64_t scopeHash, uint64_t salt) VL_MT_UNSAFE;
/// Random reset a signal of given width (init time only, var-specific PRNG)
extern QData VL_SCOPED_RAND_RESET_Q(int obits, uint64_t scopeHash, uint64_t salt) VL_MT_UNSAFE;
/// Random reset a signal of given width (init time only, var-specific PRNG)
extern WDataOutP VL_SCOPED_RAND_RESET_W(int obits, WDataOutP outwp, uint64_t scopeHash,
uint64_t salt) VL_MT_UNSAFE;
/// Random reset a signal of given width (init time only)
extern IData VL_RAND_RESET_I(int obits) VL_MT_SAFE;
/// Random reset a signal of given width (init time only)
@ -2815,8 +2807,6 @@ inline IData VL_VALUEPLUSARGS_INQ(int rbits, const std::string& ld, double& rdr)
}
extern IData VL_VALUEPLUSARGS_INN(int, const std::string& ld, std::string& rdr) VL_MT_SAFE;
uint64_t VL_HASH(const char* key) VL_PURE;
//======================================================================
#endif // Guard

20
src/V3AstNodeExpr.h
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@ -1802,8 +1802,14 @@ class AstRand final : public AstNodeExpr {
// Return a random number, based upon width()
// @astgen op1 := seedp : Optional[AstNode]
const bool m_urandom = false; // $urandom vs $random
const bool m_reset = false; // Random reset, versus always random
public:
class Reset {};
AstRand(FileLine* fl, Reset, AstNodeDType* dtp, bool reset)
: ASTGEN_SUPER_Rand(fl)
, m_reset{reset} {
dtypep(dtp);
}
AstRand(FileLine* fl, AstNode* seedp, bool urandom)
: ASTGEN_SUPER_Rand(fl)
, m_urandom{urandom} {
@ -1815,6 +1821,14 @@ public:
: (m_urandom ? "%f$urandom()" : "%f$random()");
}
string emitC() override {
if (m_reset) {
if (v3Global.opt.xAssign() == "unique") {
return "VL_RAND_RESET_ASSIGN_%nq(%nw, %P)";
} else {
// This follows xInitial randomization
return "VL_RAND_RESET_%nq(%nw, %P)";
}
}
if (seedp()) {
if (urandom()) {
return "VL_URANDOM_SEEDED_%nq%lq(%li)";
@ -1831,12 +1845,14 @@ public:
bool cleanOut() const override { return false; }
bool isGateOptimizable() const override { return false; }
bool isPredictOptimizable() const override { return false; }
bool isPure() override { return !seedp(); }
bool isPure() override { return !m_reset && !seedp(); }
int instrCount() const override { return INSTR_COUNT_PLI; }
bool sameNode(const AstNode* /*samep*/) const override { return true; }
bool combinable(const AstRand* samep) const {
return !seedp() && !samep->seedp() && urandom() == samep->urandom();
return !seedp() && !samep->seedp() && reset() == samep->reset()
&& urandom() == samep->urandom();
}
bool reset() const { return m_reset; }
bool urandom() const { return m_urandom; }
};
class AstRandRNG final : public AstNodeExpr {

39
src/V3EmitCFunc.cpp
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@ -753,9 +753,7 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing,
|| varp->isFuncLocal() // Randomization too slow
|| (basicp && basicp->isZeroInit())
|| (v3Global.opt.underlineZero() && !varp->name().empty() && varp->name()[0] == '_')
|| (varp->isXTemp()
? (v3Global.opt.xAssign() != "unique")
: (v3Global.opt.xInitial() == "fast" || v3Global.opt.xInitial() == "0")));
|| (v3Global.opt.xInitial() == "fast" || v3Global.opt.xInitial() == "0"));
const bool slow = !varp->isFuncLocal() && !varp->isClassMember();
splitSizeInc(1);
if (dtypep->isWide()) { // Handle unpacked; not basicp->isWide
@ -768,20 +766,9 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing,
out += cvtToStr(constp->num().edataWord(w)) + "U;\n";
}
} else {
out += zeroit ? (slow ? "VL_ZERO_RESET_W(" : "VL_ZERO_W(")
: "VL_SCOPED_RAND_RESET_W(";
out += zeroit ? (slow ? "VL_ZERO_RESET_W(" : "VL_ZERO_W(") : "VL_RAND_RESET_W(";
out += cvtToStr(dtypep->widthMin());
out += ", " + varNameProtected + suffix;
if (!zeroit) {
emitVarResetScopeHash();
const uint64_t salt = VString::hashMurmur(varp->prettyName());
out += ", ";
out += m_classOrPackage ? m_classOrPackageHash : "__VscopeHash";
out += ", ";
out += std::to_string(salt);
out += "ull";
}
out += ");\n";
out += ", " + varNameProtected + suffix + ");\n";
}
return out;
} else {
@ -794,13 +781,9 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing,
if (zeroit || (v3Global.opt.xInitialEdge() && varp->isUsedClock())) {
out += " = 0;\n";
} else {
emitVarResetScopeHash();
const uint64_t salt = VString::hashMurmur(varp->prettyName());
out += " = VL_SCOPED_RAND_RESET_";
out += " = VL_RAND_RESET_";
out += dtypep->charIQWN();
out += "(" + cvtToStr(dtypep->widthMin()) + ", "
+ (m_classOrPackage ? m_classOrPackageHash : "__VscopeHash") + ", "
+ std::to_string(salt) + "ull);\n";
out += "(" + cvtToStr(dtypep->widthMin()) + ");\n";
}
return out;
}
@ -809,15 +792,3 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing,
}
return "";
}
void EmitCFunc::emitVarResetScopeHash() {
if (VL_LIKELY(m_createdScopeHash)) { return; }
if (m_classOrPackage) {
m_classOrPackageHash
= std::to_string(VString::hashMurmur(m_classOrPackage->name())) + "ULL";
} else {
puts(string("const uint64_t __VscopeHash = VL_HASH(")
+ (m_useSelfForThis ? "vlSelf" : "this") + "->name());\n");
}
m_createdScopeHash = true;
}

5
src/V3EmitCFunc.h
View File

@ -120,7 +120,6 @@ class EmitCFunc VL_NOT_FINAL : public EmitCConstInit {
int m_labelNum = 0; // Next label number
bool m_inUC = false; // Inside an AstUCStmt or AstUCExpr
bool m_emitConstInit = false; // Emitting constant initializer
bool m_createdScopeHash = false; // Already created a scope hash
// State associated with processing $display style string formatting
struct EmitDispState final {
@ -151,8 +150,6 @@ protected:
const AstNodeModule* m_modp = nullptr; // Current module being emitted
const AstCFunc* m_cfuncp = nullptr; // Current function being emitted
bool m_instantiatesOwnProcess = false;
const AstClassPackage* m_classOrPackage = nullptr; // Pointer to current class or package
string m_classOrPackageHash; // Hash of class or package name
bool constructorNeedsProcess(const AstClass* const classp) {
const AstNode* const newp = m_memberMap.findMember(classp, "new");
@ -217,7 +214,6 @@ public:
string emitVarResetRecurse(const AstVar* varp, bool constructing,
const string& varNameProtected, AstNodeDType* dtypep, int depth,
const string& suffix);
void emitVarResetScopeHash();
void emitChangeDet();
void emitConstInit(AstNode* initp) {
// We should refactor emit to produce output into a provided buffer, not go through members
@ -289,7 +285,6 @@ public:
VL_RESTORER(m_useSelfForThis);
VL_RESTORER(m_cfuncp);
VL_RESTORER(m_instantiatesOwnProcess);
VL_RESTORER(m_createdScopeHash);
m_cfuncp = nodep;
m_instantiatesOwnProcess = false;

2
src/V3EmitCImp.cpp
View File

@ -506,9 +506,7 @@ class EmitCImp final : EmitCFunc {
};
gather(modp);
VL_RESTORER(m_classOrPackage);
if (const AstClassPackage* const packagep = VN_CAST(modp, ClassPackage)) {
m_classOrPackage = packagep;
gather(packagep->classp());
}

1
src/V3Options.cpp
View File

@ -2102,7 +2102,6 @@ V3Options::V3Options() {
m_makeDir = "obj_dir";
m_unusedRegexp = "*unused*";
m_xAssign = "fast";
m_xInitial = "unique";
m_defaultLanguage = V3LangCode::mostRecent();

43
src/V3String.cpp
View File

@ -342,49 +342,6 @@ string VString::aOrAn(const char* word) {
}
}
// MurmurHash64A
uint64_t VString::hashMurmur(const string& str) VL_PURE {
const char* key = str.c_str();
const size_t len = str.size();
const uint64_t seed = 0;
const uint64_t m = 0xc6a4a7935bd1e995ULL;
const int r = 47;
uint64_t h = seed ^ (len * m);
const uint64_t* data = (const uint64_t*)key;
const uint64_t* end = data + (len / 8);
while (data != end) {
uint64_t k = *data++;
k *= m;
k ^= k >> r;
k *= m;
h ^= k;
h *= m;
}
const unsigned char* data2 = (const unsigned char*)data;
switch (len & 7) {
case 7: h ^= uint64_t(data2[6]) << 48; /* fallthrough */
case 6: h ^= uint64_t(data2[5]) << 40; /* fallthrough */
case 5: h ^= uint64_t(data2[4]) << 32; /* fallthrough */
case 4: h ^= uint64_t(data2[3]) << 24; /* fallthrough */
case 3: h ^= uint64_t(data2[2]) << 16; /* fallthrough */
case 2: h ^= uint64_t(data2[1]) << 8; /* fallthrough */
case 1: h ^= uint64_t(data2[0]); h *= m; /* fallthrough */
};
h ^= h >> r;
h *= m;
h ^= h >> r;
return h;
}
//######################################################################
// VHashSha256

2
src/V3String.h
View File

@ -141,8 +141,6 @@ public:
// Return proper article (a/an) for a word. May be inaccurate for some special words
static string aOrAn(const char* word);
static string aOrAn(const string& word) { return aOrAn(word.c_str()); }
// Hash the string
static uint64_t hashMurmur(const string& str) VL_PURE;
};
//######################################################################

7
src/V3Unknown.cpp
View File

@ -359,9 +359,10 @@ class UnknownVisitor final : public VNVisitor {
nodep->fileline(),
new AstVarRef{nodep->fileline(), newvarp, VAccess::WRITE},
new AstOr{nodep->fileline(), new AstConst{nodep->fileline(), numb1},
new AstAnd{
nodep->fileline(), new AstConst{nodep->fileline(), numbx},
new AstVarRef{nodep->fileline(), newvarp, VAccess::READ}}}}};
new AstAnd{nodep->fileline(),
new AstConst{nodep->fileline(), numbx},
new AstRand{nodep->fileline(), AstRand::Reset{},
nodep->dtypep(), true}}}}};
// Add inits in front of other statement.
// In the future, we should stuff the initp into the module's constructor.
AstNode* const afterp = m_modp->stmtsp()->unlinkFrBackWithNext();

21
test_regress/t/t_debug_emitv.py
View File

@ -9,30 +9,23 @@
import vltest_bootstrap
test.scenarios("vlt")
test.scenarios('vlt')
test.lint(
# We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions
# Likewise XML
v_flags=["--lint-only --dumpi-tree 9 --dumpi-V3EmitV 9 --debug-emitv"])
output_vs = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "_*_width.tree.v")
output_v = test.glob_one(test.obj_dir + "/" + test.vm_prefix + "_*_width.tree.v")
for output_v in output_vs:
test.files_identical(output_v, test.golden_filename)
test.files_identical(output_v, test.golden_filename)
if test.verbose:
# Print if that the output Verilog is clean
# TODO not yet round-trip clean
test.run(
cmd=[
os.environ["VERILATOR_ROOT"] + "/bin/verilator",
"--lint-only",
output_vs[0],
],
logfile=test.obj_dir + "/sim_roundtrip.log",
fails=True,
verilator_run=True,
)
test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--lint-only", output_v],
logfile=test.obj_dir + "/sim_roundtrip.log",
fails=True,
verilator_run=True)
test.passes()

4
test_regress/t/t_flag_xinitial_unique.py
View File

@ -9,13 +9,13 @@
import vltest_bootstrap
test.scenarios("vlt_all")
test.scenarios('vlt_all')
test.compile(verilator_flags2=["--x-initial unique"])
test.execute()
files = glob.glob(test.obj_dir + "/" + test.vm_prefix + "___024root__DepSet_*__Slow.cpp")
test.file_grep_any(files, r"VL_SCOPED_RAND_RESET")
test.file_grep_any(files, r'VL_RAND_RESET')
test.passes()

24
test_regress/t/t_x_assign.cpp
View File

@ -21,37 +21,31 @@ double sc_time_stamp() { return 0; }
# define EXPECTED 0
#elif defined(T_X_ASSIGN_1)
# define EXPECTED 1
#elif defined(T_X_ASSIGN_UNIQUE_0)
# define EXPECTED 0
#elif defined(T_X_ASSIGN_UNIQUE_1)
# define EXPECTED 1
#else
# error "Don't know expectd output for test" #TEST
#endif
// clang-format on
int main(int argc, const char** argv) {
VM_PREFIX* top = new VM_PREFIX{};
#if defined(T_X_ASSIGN_UNIQUE_0)
Verilated::randReset(0);
#elif defined(T_X_ASSIGN_UNIQUE_1)
Verilated::randReset(1);
#elif defined(T_X_ASSIGN_UNIQUE_2)
Verilated::randReset(2);
#endif
VM_PREFIX* top = new VM_PREFIX{};
// Evaluate one clock posedge
top->clk = 0;
top->eval();
top->clk = 1;
top->eval();
#if defined(T_X_ASSIGN_UNIQUE_0)
if (top->o_int != 0) {
vl_fatal(__FILE__, __LINE__, "TOP.t", "x assign was not correct");
exit(1);
}
#elif defined(T_X_ASSIGN_UNIQUE_1)
if (top->o_int != -1) {
vl_fatal(__FILE__, __LINE__, "TOP.t", "x assign was not correct");
exit(1);
}
#elif defined(T_X_ASSIGN_UNIQUE_2)
#if defined(T_X_ASSIGN_UNIQUE_0) || defined(T_X_ASSIGN_UNIQUE_1)
if (top->o_int == 0 || top->o_int == -1) {
vl_fatal(__FILE__, __LINE__, "TOP.t", "x assign was not unique");
exit(1);

24
test_regress/t/t_x_assign_unique_2.py
View File

@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios("vlt_all")
test.pli_filename = "t/t_x_assign.cpp"
test.top_filename = "t/t_x_assign.v"
test.compile(
make_top_shell=False,
make_main=False,
verilator_flags2=["--x-assign unique --exe", "--x-initial 0", test.pli_filename],
)
test.execute()
test.passes()

17
test_regress/t/t_x_rand_mt_stability.out
View File

@ -1,17 +0,0 @@
uninitialized = 0xf5bbcbc0
x_assigned (initial) = 0x00000000
uninitialized2 = 0xa979eb54
big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33
random_init = 0x952aaa76
top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8
top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9
top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd
top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6
rand = 0xb3cf9302
rand = 0xf0acf3e4
rand = 0xca0ac74c
rand = 0x4eddfc2c
rand = 0x1919db69
x_assigned = 0xc0391efd
Last rand = 0x2d118c9b
*-* All Finished *-*

24
test_regress/t/t_x_rand_mt_stability.py
View File

@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import glob
test.scenarios("vltmt")
test.top_filename = "t/t_x_rand_stability.v"
test.compile(verilator_flags2=["--x-initial unique"])
test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename)
test.passes()
other_logs = [x for x in glob.glob("t/t_x_rand_mt_stability_*.out") if "_zero" not in x]
for other_log in other_logs:
test.files_identical(test.golden_filename, other_log)

17
test_regress/t/t_x_rand_mt_stability_add.out
View File

@ -1,17 +0,0 @@
uninitialized = 0xf5bbcbc0
x_assigned (initial) = 0x00000000
uninitialized2 = 0xa979eb54
big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33
random_init = 0x952aaa76
top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8
top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9
top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd
top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6
rand = 0xb3cf9302
rand = 0xf0acf3e4
rand = 0xca0ac74c
rand = 0x4eddfc2c
rand = 0x1919db69
x_assigned = 0xc0391efd
Last rand = 0x2d118c9b
*-* All Finished *-*

19
test_regress/t/t_x_rand_mt_stability_add.py
View File

@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios("vltmt")
test.top_filename = "t/t_x_rand_stability.v"
test.compile(verilator_flags2=["--x-initial unique", "-DADD_SIGNAL"])
test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename)
test.passes()

17
test_regress/t/t_x_rand_mt_stability_add_trace.out
View File

@ -1,17 +0,0 @@
uninitialized = 0xf5bbcbc0
x_assigned (initial) = 0x00000000
uninitialized2 = 0xa979eb54
big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33
random_init = 0x952aaa76
top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8
top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9
top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd
top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6
rand = 0xb3cf9302
rand = 0xf0acf3e4
rand = 0xca0ac74c
rand = 0x4eddfc2c
rand = 0x1919db69
x_assigned = 0xc0391efd
Last rand = 0x2d118c9b
*-* All Finished *-*

19
test_regress/t/t_x_rand_mt_stability_add_trace.py
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@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios("vltmt")
test.top_filename = "t/t_x_rand_stability.v"
test.compile(verilator_flags2=["--x-initial unique", "-DADD_SIGNAL", "--trace"])
test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename)
test.passes()

17
test_regress/t/t_x_rand_mt_stability_trace.out
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@ -1,17 +0,0 @@
uninitialized = 0xf5bbcbc0
x_assigned (initial) = 0x00000000
uninitialized2 = 0xa979eb54
big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33
random_init = 0x952aaa76
top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8
top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9
top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd
top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6
rand = 0xb3cf9302
rand = 0xf0acf3e4
rand = 0xca0ac74c
rand = 0x4eddfc2c
rand = 0x1919db69
x_assigned = 0xc0391efd
Last rand = 0x2d118c9b
*-* All Finished *-*

19
test_regress/t/t_x_rand_mt_stability_trace.py
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@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios("vltmt")
test.top_filename = "t/t_x_rand_stability.v"
test.compile(verilator_flags2=["--x-initial unique", "--trace"])
test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename)
test.passes()

17
test_regress/t/t_x_rand_mt_stability_zeros.out
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@ -1,17 +0,0 @@
uninitialized = 0x00000000
x_assigned (initial) = 0x00000000
uninitialized2 = 0x00000000
big = 0x0000000000000000000000000000000000000000000000000000000000000000
random_init = 0x952aaa76
top.t.the_sub_yes_inline_1 no_init 0x0
top.t.the_sub_yes_inline_2 no_init 0x0
top.t.the_sub_no_inline_1 no_init 0x0
top.t.the_sub_no_inline_2 no_init 0x0
rand = 0xb3cf9302
rand = 0xf0acf3e4
rand = 0xca0ac74c
rand = 0x4eddfc2c
rand = 0x1919db69
x_assigned = 0x00000000
Last rand = 0x2d118c9b
*-* All Finished *-*

19
test_regress/t/t_x_rand_mt_stability_zeros.py
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@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios("vltmt")
test.top_filename = "t/t_x_rand_stability.v"
test.compile(verilator_flags2=["--x-initial unique", "-DNOT_RAND"])
test.execute(all_run_flags=["+verilator+rand+reset+0"], expect_filename=test.golden_filename)
test.passes()

17
test_regress/t/t_x_rand_stability.out
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@ -1,17 +0,0 @@
uninitialized = 0xf5bbcbc0
x_assigned (initial) = 0x00000000
uninitialized2 = 0xa979eb54
big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33
random_init = 0x952aaa76
top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8
top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9
top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd
top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6
rand = 0xe3e54aaa
rand = 0xe85acf2d
rand = 0x15e12c6a
rand = 0x0f7f28c0
rand = 0xe189c52a
x_assigned = 0xc0391efd
Last rand = 0xf0700dbf
*-* All Finished *-*

23
test_regress/t/t_x_rand_stability.py
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@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import glob
test.scenarios("vlt")
test.compile(verilator_flags2=["--x-initial unique"])
test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename)
test.passes()
other_logs = [x for x in glob.glob("t/t_x_rand_stability_*.out") if "_zero" not in x]
for other_log in other_logs:
test.files_identical(test.golden_filename, other_log)

74
test_regress/t/t_x_rand_stability.v
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@ -1,74 +0,0 @@
// DESCRIPTION: Verilator: Confirm x randomization stability
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
int cyc = 0;
logic [31:0] uninitialized;
logic [31:0] x_assigned = '0;
`ifdef ADD_SIGNAL
logic [31:0] added;
logic [31:0] x_assigned_added = '0;
`endif
logic [31:0] unused;
logic [31:0] uninitialized2;
logic [255:0] big;
int random_init = $random();
sub_no_inline the_sub_no_inline_1();
sub_no_inline the_sub_no_inline_2();
sub_yes_inline the_sub_yes_inline_1();
sub_yes_inline the_sub_yes_inline_2();
initial begin
$display("uninitialized = 0x%x", uninitialized);
$display("x_assigned (initial) = 0x%x", x_assigned);
$display("uninitialized2 = 0x%x", uninitialized2);
$display("big = 0x%x", big);
$display("random_init = 0x%x", random_init);
end
always @(posedge clk) begin
x_assigned <= 'x;
`ifdef ADD_SIGNAL
x_assigned_added <= 'x;
`endif
cyc <= cyc + 1;
$display("rand = 0x%x", $random());
if (cyc == 4) begin
$display("x_assigned = 0x%x", x_assigned);
`ifndef NOT_RAND
if (uninitialized == uninitialized2) $stop();
if (the_sub_yes_inline_1.no_init == the_sub_yes_inline_2.no_init) $stop();
if (the_sub_no_inline_1.no_init == the_sub_no_inline_2.no_init) $stop();
`endif
`ifdef ADD_SIGNAL
if (added == 0) $stop();
if (x_assigned_added == 0) $stop();
`endif
$display("Last rand = 0x%x", $random());
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub_no_inline; /* verilator no_inline_module */
logic [63:0] no_init;
initial $display("%m no_init 0x%0x", no_init);
endmodule
module sub_yes_inline; /* verilator inline_module */
logic [63:0] no_init;
initial $display("%m no_init 0x%0x", no_init);
endmodule

17
test_regress/t/t_x_rand_stability_add.out
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@ -1,17 +0,0 @@
uninitialized = 0xf5bbcbc0
x_assigned (initial) = 0x00000000
uninitialized2 = 0xa979eb54
big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33
random_init = 0x952aaa76
top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8
top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9
top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd
top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6
rand = 0xe3e54aaa
rand = 0xe85acf2d
rand = 0x15e12c6a
rand = 0x0f7f28c0
rand = 0xe189c52a
x_assigned = 0xc0391efd
Last rand = 0xf0700dbf
*-* All Finished *-*

19
test_regress/t/t_x_rand_stability_add.py
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@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios("vlt")
test.top_filename = "t/t_x_rand_stability.v"
test.compile(verilator_flags2=["--x-initial unique", "-DADD_SIGNAL"])
test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename)
test.passes()

17
test_regress/t/t_x_rand_stability_add_trace.out
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@ -1,17 +0,0 @@
uninitialized = 0xf5bbcbc0
x_assigned (initial) = 0x00000000
uninitialized2 = 0xa979eb54
big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33
random_init = 0x952aaa76
top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8
top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9
top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd
top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6
rand = 0xe3e54aaa
rand = 0xe85acf2d
rand = 0x15e12c6a
rand = 0x0f7f28c0
rand = 0xe189c52a
x_assigned = 0xc0391efd
Last rand = 0xf0700dbf
*-* All Finished *-*

19
test_regress/t/t_x_rand_stability_add_trace.py
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@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios("vlt")
test.top_filename = "t/t_x_rand_stability.v"
test.compile(verilator_flags2=["--x-initial unique", "-DADD_SIGNAL", "--trace"])
test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename)
test.passes()

17
test_regress/t/t_x_rand_stability_trace.out
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@ -1,17 +0,0 @@
uninitialized = 0xf5bbcbc0
x_assigned (initial) = 0x00000000
uninitialized2 = 0xa979eb54
big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33
random_init = 0x952aaa76
top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8
top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9
top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd
top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6
rand = 0xe3e54aaa
rand = 0xe85acf2d
rand = 0x15e12c6a
rand = 0x0f7f28c0
rand = 0xe189c52a
x_assigned = 0xc0391efd
Last rand = 0xf0700dbf
*-* All Finished *-*

19
test_regress/t/t_x_rand_stability_trace.py
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@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios("vlt")
test.top_filename = "t/t_x_rand_stability.v"
test.compile(verilator_flags2=["--x-initial unique", "--trace"])
test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename)
test.passes()

17
test_regress/t/t_x_rand_stability_zeros.out
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@ -1,17 +0,0 @@
uninitialized = 0x00000000
x_assigned (initial) = 0x00000000
uninitialized2 = 0x00000000
big = 0x0000000000000000000000000000000000000000000000000000000000000000
random_init = 0x952aaa76
top.t.the_sub_yes_inline_1 no_init 0x0
top.t.the_sub_yes_inline_2 no_init 0x0
top.t.the_sub_no_inline_1 no_init 0x0
top.t.the_sub_no_inline_2 no_init 0x0
rand = 0xe3e54aaa
rand = 0xe85acf2d
rand = 0x15e12c6a
rand = 0x0f7f28c0
rand = 0xe189c52a
x_assigned = 0x00000000
Last rand = 0xf0700dbf
*-* All Finished *-*

19
test_regress/t/t_x_rand_stability_zeros.py
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@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios("vlt")
test.top_filename = "t/t_x_rand_stability.v"
test.compile(verilator_flags2=["--x-initial unique", "-DNOT_RAND"])
test.execute(all_run_flags=["+verilator+rand+reset+0"], expect_filename=test.golden_filename)
test.passes()