Improve message for priority case assertion failure (#4905)
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@ -286,13 +286,19 @@ class AssertVisitor final : public VNVisitor {
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itemp = VN_AS(itemp->nextp(), CaseItem)) {
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if (itemp->isDefault()) has_default = true;
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}
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const AstNodeDType* exprDtypep = nodep->exprp()->dtypep()->skipRefp();
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string valFmt;
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if (exprDtypep->isIntegralOrPacked())
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valFmt = " for '" + cvtToStr(exprDtypep->widthMin()) + "'h%X'";
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if (nodep->fullPragma() || nodep->priorityPragma()) {
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// Need to add a default if there isn't one already
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++m_statAsFull;
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if (!has_default) {
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nodep->addItemsp(new AstCaseItem{
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nodep->fileline(), nullptr /*DEFAULT*/,
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newFireAssert(nodep, "synthesis full_case, but non-match found")});
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newFireAssert(
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nodep, nodep->pragmaString() + ", but non-match found" + valFmt,
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valFmt.empty() ? nullptr : nodep->exprp()->cloneTreePure(false))});
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}
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}
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if (nodep->parallelPragma() || nodep->uniquePragma() || nodep->unique0Pragma()) {
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@ -344,14 +350,13 @@ class AssertVisitor final : public VNVisitor {
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new AstLogNot{nodep->fileline(), propp->cloneTreePure(false)}};
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AstNodeExpr* const exprp = nodep->exprp();
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const string pragmaStr = nodep->pragmaString();
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const string valFmt = "'" + cvtToStr(exprp->dtypep()->widthMin()) + "'h%X'";
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if (!allow_none)
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zeroIfp->addThensp(
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newFireAssert(nodep, pragmaStr + ", but none matched for " + valFmt,
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exprp->cloneTreePure(false)));
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zeroIfp->addElsesp(newFireAssert(
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nodep, pragmaStr + ", but multiple matches found for " + valFmt,
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exprp->cloneTreePure(false)));
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newFireAssert(nodep, pragmaStr + ", but none matched" + valFmt,
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valFmt.empty() ? nullptr : exprp->cloneTreePure(false)));
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zeroIfp->addElsesp(
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newFireAssert(nodep, pragmaStr + ", but multiple matches found" + valFmt,
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valFmt.empty() ? nullptr : exprp->cloneTreePure(false)));
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ohotIfp->addThensp(zeroIfp);
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ohotIfp->isBoundsCheck(true); // To avoid LATCH warning
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ohotIfp->branchPred(VBranchPred::BP_UNLIKELY);
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@ -1,6 +1,6 @@
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[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
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[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
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[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
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[40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found
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[40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found for '2'h3'
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%Error: t/t_assert_synth.v:31: Verilog $stop
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Aborting...
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@ -1,6 +1,6 @@
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[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
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[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
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[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
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[40] %Error: t_assert_synth.v:40: Assertion failed in top.t: synthesis full_case, but non-match found
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[40] %Error: t_assert_synth.v:40: Assertion failed in top.t: priority case, but non-match found for '2'h3'
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%Error: t/t_assert_synth.v:40: Verilog $stop
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Aborting...
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@ -1,12 +1,19 @@
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[0] %Error: t_assert_unique_case_bad.v:56: Assertion failed in top.t: priority case, but non-match found
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match_item0
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[20] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched
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match_item0
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match_item0
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[40] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched
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match_item0
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match_item0
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[60] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched
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match_item0
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match_item0
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[80] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched
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match_item0
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[90] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched
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match_item0
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match_item0
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[90] %Error: t_assert_unique_case_bad.v:36: Assertion failed in top.t: unique case, but multiple matches found for '12'h388'
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[90] %Error: t_assert_unique_case_bad.v:38: Assertion failed in top.t: unique case, but multiple matches found for '12'h388'
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*-* All Finished *-*
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[100] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched
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match_item0
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@ -12,7 +12,7 @@ scenarios(simulator => 1);
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top_filename("t/t_assert_unique_case_bad.v");
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compile(
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verilator_flags2 => ["-x-assign 0 --assert --no-stop-fail"],
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verilator_flags2 => ["-x-assign 0 --assert --no-stop-fail +define+NO_STOP_FAIL"],
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);
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execute(
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@ -7,6 +7,6 @@ match_item0
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match_item0
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match_item0
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match_item0
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[90] %Error: t_assert_unique_case_bad.v:36: Assertion failed in top.t: unique case, but multiple matches found for '12'h388'
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%Error: t/t_assert_unique_case_bad.v:36: Verilog $stop
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[90] %Error: t_assert_unique_case_bad.v:38: Assertion failed in top.t: unique case, but multiple matches found for '12'h388'
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%Error: t/t_assert_unique_case_bad.v:38: Verilog $stop
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Aborting...
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@ -17,6 +17,7 @@ module t (/*AUTOARG*/
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logic [31:0] addr;
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logic [11:0] match_item0, match_item1;
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int cyc;
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string s;
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initial addr = 32'h380;
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@ -25,6 +26,7 @@ module t (/*AUTOARG*/
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addr <= 32'h380 + cyc;
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match_item0 = 12'h 380 + cyc[11:0];
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match_item1 = 12'h 390 - cyc[11:0];
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$sformat(s, "%1d", cyc);
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if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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@ -40,4 +42,23 @@ module t (/*AUTOARG*/
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endcase
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end
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`ifdef NO_STOP_FAIL
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always_comb begin
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unique case (s)
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"": ;
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"0": ;
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"2": ;
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"4": ;
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"6": ;
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endcase
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end
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always_comb begin
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priority case (s)
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$sformatf("%1d", cyc - 1): ;
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"0": ;
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"6": ;
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endcase
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end
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`endif
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endmodule
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