Snapshot 20060809

Add support for real valued modulus.
Handle 64bit delay constants.
2026-08-23 14:27:01 +02:00 · 2006-08-10 01:23:29 +00:00 · 2006-08-09 05:19:08 +00:00 · 2006-08-08 05:11:37 +00:00 · 2006-08-06 18:17:00 +00:00 · 2006-08-04 04:37:37 +00:00
459 changed files with 68360 additions and 34590 deletions
@@ -2,10 +2,14 @@ lexor_keyword.cc
 parse.h
 parse.cc
 parse.cc.output
+parse.output
 syn-rules.cc
 syn-rules.cc.output
+syn-rules.output
 lexor.cc
 iverilog-vpi
+iverilog-vpi.pdf
+iverilog-vpi.ps
 ivl
 ivl.exp
 dep
@@ -16,5 +20,7 @@ check.cc
 config.status
 config.log
 config.cache
+autom4te.cache
 config.h
+_pli_types.h
 dosify
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: Attrib.cc,v 1.5 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: Attrib.cc,v 1.6 2004/02/20 18:53:33 steve Exp $"
 #endif

 # include "config.h"
@@ -36,25 +36,8 @@ Attrib::~Attrib()
      delete[] list_;
 }

-#if 0
-void Attrib::copy_attributes(const map<string,verinum>&attr)
-{
-      assert(list_ == 0);

-      nlist_ = attr.size();
-      list_ = new cell_[nlist_];
-
-      map<string,verinum>::const_iterator idx;
-      unsigned jdx;
-      for (idx = attr.begin(), jdx = 0 ;  idx != attr.end() ;  idx ++, jdx++) {
-	    struct cell_*tmp = list_ + jdx;
-	    tmp->key = (*idx).first;
-	    tmp->val = (*idx).second;
-      }
-}
-#endif
-
-const verinum& Attrib::attribute(const string&key) const
+const verinum& Attrib::attribute(perm_string key) const
 {
      for (unsigned idx = 0 ;  idx < nlist_ ;  idx += 1) {

@@ -66,7 +49,7 @@ const verinum& Attrib::attribute(const string&key) const
      return null;
 }

-void Attrib::attribute(const string&key, const verinum&value)
+void Attrib::attribute(perm_string key, const verinum&value)
 {
      unsigned idx;

@@ -108,10 +91,10 @@ unsigned Attrib::attr_cnt() const
      return nlist_;
 }

-const char* Attrib::attr_key(unsigned idx) const
+perm_string Attrib::attr_key(unsigned idx) const
 {
      assert(idx < nlist_);
-      return list_[idx].key.c_str();
+      return list_[idx].key;
 }

 const verinum& Attrib::attr_value(unsigned idx) const
@@ -123,6 +106,9 @@ const verinum& Attrib::attr_value(unsigned idx) const

 /*
 * $Log: Attrib.cc,v $
+ * Revision 1.6  2004/02/20 18:53:33  steve
+ *  Addtrbute keys are perm_strings.
+ *
 * Revision 1.5  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -19,10 +19,10 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: Attrib.h,v 1.4 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: Attrib.h,v 1.5 2004/02/20 18:53:33 steve Exp $"
 #endif

-# include  <string>
+# include  "StringHeap.h"
 # include  "verinum.h"

 /*
@@ -35,20 +35,20 @@ class Attrib {
      Attrib();
      ~Attrib();

-      const verinum&attribute(const string&key) const;
-      void attribute(const string&key, const verinum&value);
+      const verinum&attribute(perm_string key) const;
+      void attribute(perm_string key, const verinum&value);
      bool has_compat_attributes(const Attrib&that) const;


 	/* Provide a means of iterating over the entries in the map. */
      unsigned       attr_cnt() const;
-      const char*    attr_key(unsigned idx) const;
+      perm_string    attr_key(unsigned idx) const;
      const verinum& attr_value(unsigned idx) const;


    private:
      struct cell_ {
-	    string  key;
+	    perm_string  key;
 	    verinum val;
      };

@@ -62,6 +62,9 @@ class Attrib {

 /*
 * $Log: Attrib.h,v $
+ * Revision 1.5  2004/02/20 18:53:33  steve
+ *  Addtrbute keys are perm_strings.
+ *
 * Revision 1.4  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -16,7 +16,7 @@ compilation tools you are using. Specifically, I need to know:
 	- Operating system and processor type,
 	- Compiler w/ version,
 	- Library version, and
-	- anything else you think relevent.
+	- anything else you think relevant.

 Be aware that I do not have at my disposal a porting lab. I have the
 alpha on my desk, and the Linux/Intel box with a logic analyzer and
@@ -110,6 +110,24 @@ program and include a GPL license statement if you can. Your test
 program may find its way into the test suite, and the notices will
 make it all nice and legal.

+RESEARCHING EXISTING/PAST BUGS, AND FILING REPORTS
+
+The URL <http://www.icarus.com/cgi-bin/ivl-bugs> is the main bug
+tracking system. Once you believe you have found a bug, you may browse
+the bugs database for existing bugs that may be related to yours. You
+might find that your bug has already been fixed in a later release or
+snapshot. If that's the case, then you are set.
+
+The bug database supports basic keyword searches, and you can
+optionally limit your search to active bugs, or fixed bugs. You may
+also browse the bug database, just to get an idea what is still
+broken. You may for example find a related bug that explains your
+symptom.
+
+The root page of the bug report database describes how to submit your
+completed bug report. You may submit it via the web form, or via
+e-mail.
+
 HOW TO SEND PATCHES

 Bug reports with patches are very welcome, especially if they are
@@ -130,7 +148,7 @@ patch is for, I will ask for clarification before applying it.)

 COPYRIGHT ISSUES

-Icarus Verilog is Copyright (c) 1998-1999 Stephen Williams except
+Icarus Verilog is Copyright (c) 1998-2003 Stephen Williams except
 where otherwise noted. Minor patches are covered as derivative works
 (or editorial comment or whatever the appropriate legal term is) and
 folded into the rest of ivl. However, if a submission can reasonably
@@ -141,8 +159,15 @@ then falls under the "otherwise noted" category.
 I must insist that any copyright material submitted for inclusion
 include the GPL license notice as shown in the rest of the source.

-$Id: BUGS.txt,v 1.2 1999/08/06 04:05:28 steve Exp $
+
+$Id: BUGS.txt,v 1.4 2003/02/19 04:36:31 steve Exp $
 $Log: BUGS.txt,v $
+Revision 1.4  2003/02/19 04:36:31  steve
+ Notes on hte bug database.
+
+Revision 1.3  2003/01/30 16:23:07  steve
+ Spelling fixes.
+
 Revision 1.2  1999/08/06 04:05:28  steve
 Handle scope of parameters.

@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: HName.cc,v 1.4 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: HName.cc,v 1.5 2002/11/02 03:27:52 steve Exp $"
 #endif

 # include  "config.h"
@@ -75,6 +75,11 @@ hname_t::~hname_t()
      }
 }

+unsigned hname_t::component_count() const
+{
+      return count_;
+}
+
 void hname_t::append(const char*text)
 {
      char**tmp;
@@ -253,6 +258,10 @@ ostream& operator<< (ostream&out, const hname_t&that)

 /*
 * $Log: HName.cc,v $
+ * Revision 1.5  2002/11/02 03:27:52  steve
+ *  Allow named events to be referenced by
+ *  hierarchical names.
+ *
 * Revision 1.4  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -19,7 +19,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: HName.h,v 1.3 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: HName.h,v 1.4 2002/11/02 03:27:51 steve Exp $"
 #endif

 # include  <iostream>
@@ -61,6 +61,10 @@ class hname_t {
      const char*peek_name(unsigned idx) const;
      const char*peek_tail_name() const;

+	// Return the number of components in the hierarchical
+	// name. If this is a simple name, this will return 1.
+      unsigned component_count() const;
+
      friend ostream& operator<< (ostream&, const hname_t&);

    private:
@@ -79,6 +83,10 @@ extern bool operator == (const hname_t&, const hname_t&);

 /*
 * $Log: HName.h,v $
+ * Revision 1.4  2002/11/02 03:27:51  steve
+ *  Allow named events to be referenced by
+ *  hierarchical names.
+ *
 * Revision 1.3  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -17,13 +17,18 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: LineInfo.cc,v 1.3 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: LineInfo.cc,v 1.4 2003/01/17 05:49:03 steve Exp $"
 #endif

 # include "config.h"

 # include  "LineInfo.h"
-# include  <cstdio>
+# include  <sstream>
+
+LineInfo::LineInfo()
+: file_(0), lineno_(0)
+{
+}

 LineInfo::~LineInfo()
 {
@@ -31,9 +36,11 @@ LineInfo::~LineInfo()

 string LineInfo::get_line() const
 {
-      char buf[8];
-      sprintf(buf, "%u", lineno_);
-      return string(file_? file_ : "") + ":" + buf;
+      ostringstream buf;
+      buf << (file_? file_ : "") << ":" << lineno_;
+
+      string res = buf.str();
+      return res;
 }

 void LineInfo::set_line(const LineInfo&that)
@@ -42,8 +49,21 @@ void LineInfo::set_line(const LineInfo&that)
      lineno_ = that.lineno_;
 }

+void LineInfo::set_file(const char*f)
+{
+      file_ = f;
+}
+
+void LineInfo::set_lineno(unsigned n)
+{
+      lineno_ = n;
+}
+
 /*
 * $Log: LineInfo.cc,v $
+ * Revision 1.4  2003/01/17 05:49:03  steve
+ *  Use stringstream in place of sprintf.
+ *
 * Revision 1.3  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -19,11 +19,13 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: LineInfo.h,v 1.6 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: LineInfo.h,v 1.8 2005/06/14 19:13:43 steve Exp $"
 #endif

 # include  <string>

+using namespace std;
+
 /*
 * This class holds line information for an internal object.
 *
@@ -35,15 +37,15 @@

 class LineInfo {
    public:
-      LineInfo() : file_(0), lineno_(0) { }
+      LineInfo();
      ~LineInfo();

      string get_line() const;

      void set_line(const LineInfo&that);

-      void set_file(const char*f) { file_ = f; }
-      void set_lineno(unsigned n) { lineno_ = n; }
+      void set_file(const char*f);
+      void set_lineno(unsigned n);

    private:
      const char* file_;
@@ -52,6 +54,12 @@ class LineInfo {

 /*
 * $Log: LineInfo.h,v $
+ * Revision 1.8  2005/06/14 19:13:43  steve
+ *  gcc3/4 compile errors.
+ *
+ * Revision 1.7  2003/01/17 05:49:03  steve
+ *  Use stringstream in place of sprintf.
+ *
 * Revision 1.6  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -16,7 +16,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.134 2002/09/16 00:30:33 steve Exp $"
+#ident "$Id: Makefile.in,v 1.176 2006/05/01 20:47:29 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -25,7 +25,7 @@ SHELL = /bin/sh
 # by the compiler. It reflects the assigned version number for the
 # product as a whole. Most components also print the CVS Name: token
 # in order to get a more automatic version stamp as well.
-VERSION = 0.6
+VERSION = 0.9.devel

 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -37,11 +37,12 @@ VPATH = $(srcdir)

 bindir = @bindir@
 libdir = @libdir@
-includedir = $(prefix)/include
+includedir = @includedir@
 mandir = @mandir@

+libdir64 = @libdir64@
+
 dllib=@DLLIB@
-rdynamic=@rdynamic@
 strip_dynamic=@strip_dynamic@

 CC = @CC@
@@ -54,130 +55,105 @@ STRIP = @STRIP@
 LEX = @LEX@
 YACC = @YACC@

-CPPFLAGS = @CPPFLAGS@ @DEFS@
-CXXFLAGS = @CXXFLAGS@ -I. -I$(srcdir)
+CPPFLAGS = @ident_support@ @DEFS@ -I. -I$(srcdir) @CPPFLAGS@
+CXXFLAGS = -Wall @CXXFLAGS@
 PICFLAGS = @PICFLAG@
-LDFLAGS = @LDFLAGS@
+LDFLAGS = @rdynamic@ @LDFLAGS@

-# The TARGETS variable lists the target modules that can be build and
-# installed. Some of them depend on external things, so are only
-# compiled if the prerequisites are installed.
-TARGETS = tgt-null
-ifeq ('@HAVE_IPAL@','yes')
-TARGETS += tgt-pal
-endif
-
-all: ivl@EXEEXT@ libvpi.a
-	for dir in $(SUBDIRS) ; do (cd $$dir ; $(MAKE) all); done
-	cd vpi ; $(MAKE) all
-	cd ivlpp ; $(MAKE) all
-	cd driver ; $(MAKE) VERSION=$(VERSION) all
-	cd tgt-verilog ; $(MAKE) all
-	cd tgt-stub ; $(MAKE) all
-	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) all); done
+all: dep ivl@EXEEXT@
+	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) $@); done
+	for dir in ivlpp tgt-verilog ; \
+	    do (cd $$dir ; $(MAKE) $@); done
+	cd driver ; $(MAKE) VERSION=$(VERSION) $@

 # In the windows world, the installer will need a dosify program to
 # dosify text files.
 ifeq (@WIN32@,yes)
-all: dosify.exe
+all: dep dosify.exe
 dosify.exe: dosify.c
 	$(CC) -o dosify.exe dosify.c
-
-else
-all: iverilog-vpi
 endif

 # This rule rules the compiler in the trivial hello.vl program to make
 # sure the basics were compiled properly.
 check: all
 	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) check); done
-	driver/iverilog -Ccheck.conf -ocheck.vvp -tvvp-check -B./ivlpp $(srcdir)/examples/hello.vl
-	vvp/vvp -M./vpi ./check.vvp | grep 'Hello, World'
+	test -r check.conf || cp $(srcdir)/check.conf .
+	driver/iverilog -B. -BPivlpp -tcheck -ocheck.vvp $(srcdir)/examples/hello.vl
+	vvp/vvp -M- -M./vpi ./check.vvp | grep 'Hello, World'

 clean:
-	rm -f *.o parse.cc parse.cc.output parse.h dep/*.d lexor.cc lexor_keyword.cc ivl@EXEEXT@ libivl.a libvpi.a iverilog-vpi
-	cd vpi ; $(MAKE) clean
-	cd driver ; $(MAKE) clean
-	cd ivlpp ; $(MAKE) clean
-	cd tgt-verilog ; $(MAKE) clean
-	cd tgt-stub ; $(MAKE) clean
-	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) clean); done
-	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) clean); done
+	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) $@); done
+	for dir in vpi ivlpp tgt-verilog driver; \
+	    do (cd $$dir ; $(MAKE) $@); done
+	rm -f *.o parse.cc parse.cc.output parse.h lexor.cc
+	rm -f lexor_keyword.cc libivl.a libvpi.a iverilog-vpi syn-rules.cc*
+	rm -rf dep ivl@EXEEXT@

 distclean: clean
-	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) distclean); done
-	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) distclean); done
-	rm -f vpi/Makefile
-	rm -f ivlpp/Makefile
-	rm -f driver/Makefile
-	rm -f config.status config.cache config.log
-	rm -f Makefile
-	rm -f tgt-pal/Makefile tgt-stub/Makefile tgt-verilog/Makefile
+	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) $@); done
+	for dir in vpi ivlpp tgt-verilog driver; \
+	    do (cd $$dir ; $(MAKE) $@); done
+	rm -f Makefile config.status config.log config.cache config.h

-TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o t-xnf.o
-FF = cprop.o nodangle.o synth.o synth2.o syn-rules.o xnfio.o
+TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o
+FF = cprop.o nodangle.o synth.o synth2.o syn-rules.o

 O = main.o async.o design_dump.o dup_expr.o elaborate.o elab_expr.o \
-elab_lval.o elab_net.o elab_anet.o elab_pexpr.o elab_scope.o \
-elab_sig.o emit.o eval.o eval_attrib.o eval_rconst.o \
+elab_lval.o elab_net.o elab_pexpr.o elab_scope.o \
+elab_sig.o emit.o eval.o eval_attrib.o \
 eval_tree.o expr_synth.o functor.o lexor.o lexor_keyword.o link_const.o \
 load_module.o netlist.o netmisc.o net_assign.o \
 net_design.o net_event.o net_expr.o net_force.o net_func.o \
 net_link.o net_modulo.o net_nex_input.o net_nex_output.o \
 net_proc.o net_scope.o net_udp.o pad_to_width.o \
 parse.o parse_misc.o pform.o pform_dump.o \
-set_width.o sync.o \
+set_width.o symbol_search.o sync.o sys_funcs.o \
 verinum.o verireal.o target.o targets.o \
 Attrib.o HName.o LineInfo.o Module.o PDelays.o PEvent.o \
-PExpr.o PGate.o \
-PTask.o PFunction.o PWire.o Statement.o StringHeap.o \
+PExpr.o PGate.o PGenerate.o \
+PTask.o PUdp.o PFunction.o PWire.o Statement.o StringHeap.o \
 $(FF) $(TT)

 Makefile: Makefile.in config.h.in config.status
 	./config.status


-libvpi.a: vpithunk.o
-	rm -f $@
-	ar cvq $@ vpithunk.o
-	ranlib $@
-
-# The vpithunk.c file (that makes up the libvpi.a library) needs to
-# be make with PIC flags, because shared objects load it.
-vpithunk.o: vpithunk.c
-	@[ -d dep ] || mkdir dep
-	$(CC) $(CPPFLAGS) $(CFLAGS) $(PICFLAGS) -MD -c $< -o $*.o
-	mv $*.d dep/$*.d
-
-
 ifeq (@WIN32@,yes)
 # Under Windows (mingw) I need to make the ivl.exe in two steps.
 # The first step makes an ivl.exe that dlltool can use to make an
 # export and import library, and the last link makes a, ivl.exe
 # that really exports the things that the import library imports.
 ivl@EXEEXT@: $O ivl.def
-	$(CXX) -o ivl@EXEEXT@ $O $(dllib) @EXTRALIBS@	
+	$(CXX) -o ivl@EXEEXT@ $O $(dllib) @EXTRALIBS@
 	dlltool --dllname ivl@EXEEXT@ --def ivl.def \
 		--output-lib libivl.a --output-exp ivl.exp
-	$(CXX) -o ivl@EXEEXT@ ivl.exp $O $(dllib) @EXTRALIBS@	
+	$(CXX) -o ivl@EXEEXT@ ivl.exp $O $(dllib) @EXTRALIBS@
 else
 ivl@EXEEXT@: $O
-	$(CXX) $(CXXFLAGS) $(rdynamic) $(LDFLAGS) -o ivl@EXEEXT@ $O $(dllib)
+	$(CXX) $(LDFLAGS) -o ivl@EXEEXT@ $O $(dllib)
+
 endif

-
-ifeq (@WIN32@,yes)
-
+ifeq (@MINGW32@,yes)
+SUBDIRS += driver-vpi
 else
+all: dep iverilog-vpi
+
 iverilog-vpi: iverilog-vpi.sh
 	sed -e 's;@SHARED@;@shared@;' -e 's;@PIC@;@PICFLAG@;' \
-	    -e 's;@INCLUDEDIR@;@includedir@;' -e 's;@LIBDIR@;@libdir@;' $< > $@
+	    -e 's;@INCLUDEDIR@;@includedir@;' \
+	    -e 's;@LIBDIR64@;@libdir64@;' \
+	    -e 's;@VPIDIR1@;@vpidir1@;' -e 's;@VPIDIR2@;@vpidir2@;' \
+	    -e 's;@LIBDIR@;@libdir@;' $< > $@
 	chmod +x $@
 endif

+dep:
+	mkdir dep
+
 %.o: %.cc
-	@[ -d dep ] || mkdir dep
-	$(CXX) @ident_support@ $(CPPFLAGS) $(CXXFLAGS) -MD -c $< -o $*.o
+	$(CXX) $(CPPFLAGS) $(CXXFLAGS) -MD -c $< -o $*.o
 	mv $*.d dep/$*.d


@@ -185,9 +161,9 @@ lexor.o: lexor.cc parse.h

 parse.o: parse.cc

-parse.h parse.cc: $(srcdir)/parse.y
+parse.cc parse.h: $(srcdir)/parse.y
 	$(YACC) --verbose -t -p VL -d -o parse.cc $(srcdir)/parse.y
-	mv parse.cc.h parse.h || mv parse.hh parse.h
+	mv parse.cc.h parse.h 2>/dev/null || mv parse.hh parse.h

 syn-rules.cc: $(srcdir)/syn-rules.y
 	$(YACC) --verbose -p syn_ -o syn-rules.cc $(srcdir)/syn-rules.y
@@ -195,7 +171,7 @@ syn-rules.cc: $(srcdir)/syn-rules.y
 lexor.cc: $(srcdir)/lexor.lex
 	$(LEX) -PVL -s -olexor.cc $(srcdir)/lexor.lex

-lexor_keyword.o: lexor_keyword.cc
+lexor_keyword.o: lexor_keyword.cc parse.h

 lexor_keyword.cc: lexor_keyword.gperf
 	gperf -o -i 7 -C -k 1-3,$$ -L ANSI-C -H keyword_hash -N check_identifier -t $(srcdir)/lexor_keyword.gperf > lexor_keyword.cc || (rm -f lexor_keyword.cc ; false)
@@ -207,43 +183,46 @@ iverilog-vpi.pdf: iverilog-vpi.ps
 	ps2pdf iverilog-vpi.ps iverilog-vpi.pdf

 ifeq (@WIN32@,yes)
-INSTALL_DOC = $(prefix)/iverilog-vpi.pdf
-INSTALL_DOCDIR =
-all: iverilog-vpi.pdf
+INSTALL_DOC = $(prefix)/iverilog-vpi.pdf $(mandir)/man1/iverilog-vpi.1
+INSTALL_DOCDIR = $(mandir)/man1
+all: dep iverilog-vpi.pdf
 else
 INSTALL_DOC = $(mandir)/man1/iverilog-vpi.1
 INSTALL_DOCDIR = $(mandir)/man1
 endif

-ifeq (@WIN32@,yes)
-WIN32_INSTALL = $(prefix)/hello.vl $(prefix)/sqrt.vl $(prefix)/QUICK_START.txt
+ifeq (@MINGW32@,yes)
+WIN32_INSTALL = $(prefix)/hello.vl $(prefix)/sqrt.vl $(prefix)/sqrt-virtex.v $(prefix)/QUICK_START.txt
 else
 WIN32_INSTALL = $(bindir)/iverilog-vpi
 endif

-install: all installdirs $(libdir)/ivl/ivl@EXEEXT@ $(libdir)/ivl/iverilog.conf $(includedir)/ivl_target.h $(includedir)/vpi_user.h $(includedir)/acc_user.h $(includedir)/veriuser.h $(libdir)/libvpi.a $(WIN32_INSTALL) $(INSTALL_DOC)
-	cd vpi ; $(MAKE) install
-	cd ivlpp ; $(MAKE) install
-	cd driver ; $(MAKE) install
-	for tgt in $(SUBDIRS); do (cd $$tgt ; $(MAKE) install); done
-	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) install); done
+XNF_INSTALL = $(libdir)/ivl/xnf.conf $(libdir)/ivl/xnf-s.conf
+
+install: all installdirs $(libdir)/ivl/ivl@EXEEXT@  $(includedir)/ivl_target.h $(includedir)/_pli_types.h $(includedir)/vpi_user.h $(includedir)/acc_user.h $(includedir)/veriuser.h $(WIN32_INSTALL) $(INSTALL_DOC)
+	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) $@); done
+	for dir in vpi ivlpp driver; \
+	    do (cd $$dir ; $(MAKE) $@); done

 $(bindir)/iverilog-vpi: ./iverilog-vpi
-	$(INSTALL_PROGRAM) ./iverilog-vpi $(bindir)/iverilog-vpi
-
-$(libdir)/libvpi.a : ./libvpi.a
-	$(INSTALL_DATA) libvpi.a $(libdir)/libvpi.a
+	$(INSTALL_SCRIPT) ./iverilog-vpi $(bindir)/iverilog-vpi

 $(libdir)/ivl/ivl@EXEEXT@: ./ivl@EXEEXT@
 	$(INSTALL_PROGRAM) ./ivl@EXEEXT@ $(libdir)/ivl/ivl@EXEEXT@
 	$(STRIP) $(strip_dynamic) $(libdir)/ivl/ivl@EXEEXT@

-$(libdir)/ivl/iverilog.conf: $(srcdir)/iverilog.conf
-	$(INSTALL_DATA) $(srcdir)/iverilog.conf $(libdir)/ivl/iverilog.conf
+$(libdir)/ivl/xnf-s.conf: $(srcdir)/xnf-s.conf
+	$(INSTALL_DATA) $(srcdir)/xnf-s.conf $(libdir)/ivl/xnf-s.conf
+
+$(libdir)/ivl/xnf.conf: $(srcdir)/xnf.conf
+	$(INSTALL_DATA) $(srcdir)/xnf.conf $(libdir)/ivl/xnf.conf

 $(includedir)/ivl_target.h: $(srcdir)/ivl_target.h
 	$(INSTALL_DATA) $(srcdir)/ivl_target.h $(includedir)/ivl_target.h

+$(includedir)/_pli_types.h: _pli_types.h
+	$(INSTALL_DATA) $< $(includedir)/_pli_types.h
+
 $(includedir)/vpi_user.h: $(srcdir)/vpi_user.h
 	$(INSTALL_DATA) $(srcdir)/vpi_user.h $(includedir)/vpi_user.h

@@ -261,7 +240,7 @@ $(prefix)/iverilog-vpi.pdf: iverilog-vpi.pdf

 # In windows installations, put a few examples and the quick_start
 # into the destination directory.
-ifeq (@WIN32@,yes)
+ifeq (@MINGW32@,yes)
 $(prefix)/hello.vl: $(srcdir)/examples/hello.vl
 	./dosify.exe $(srcdir)/examples/hello.vl tmp.vl
 	mv tmp.vl $(prefix)/hello.vl
@@ -270,6 +249,10 @@ $(prefix)/sqrt.vl: $(srcdir)/examples/sqrt.vl
 	./dosify.exe $(srcdir)/examples/sqrt.vl tmp.vl
 	mv tmp.vl $(prefix)/sqrt.vl

+$(prefix)/sqrt-virtex.v: $(srcdir)/examples/sqrt-virtex.v
+	./dosify.exe $(srcdir)/examples/sqrt-virtex.v tmp.vl
+	mv tmp.vl $(prefix)/sqrt-virtex.v
+
 $(prefix)/QUICK_START.txt: $(srcdir)/QUICK_START.txt
 	./dosify.exe $(srcdir)/QUICK_START.txt tmp.txt
 	mv tmp.txt $(prefix)/QUICK_START.txt
@@ -280,23 +263,17 @@ installdirs: mkinstalldirs
 	    $(mandir) $(mandir)/man1

 uninstall:
-	rm -f $(libdir)/ivl/iverilog.conf
-	rm -f $(libdir)/ivl/ivl
+	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) $@); done
+	for dir in vpi ivlpp driver; \
+	    do (cd $$dir ; $(MAKE) $@); done
+	for f in xnf.conf xnf-s.conf ivl; \
+	    do rm -f $(libdir)/ivl/$$f; done
 	-rmdir $(libdir)/ivl
-	rm -f $(libdir)/libvpi.a
-	rm -f $(bindir)/verilog
-	rm -f $(bindir)/iverilog-vpi
-	rm -f $(bindir)/gverilog@EXEEXT@
-	rm -f $(includedir)/ivl_target.h
-	rm -f $(includedir)/vpi_user.h
-	rm -f $(includedir)/acc_user.h
-	rm -f $(includedir)/veriuser.h
+	for f in verilog iverilog-vpi gverilog@EXEEXT@; \
+	    do rm -f $(bindir)/$$f; done
+	for f in ivl_target.h vpi_user.h _pli_types.h acc_user.h veriuser.h; \
+	    do rm -f $(includedir)/$$f; done
 	rm -f $(mandir)/man1/iverilog-vpi.1
-	cd driver ; $(MAKE) uninstall
-	cd vpi ; $(MAKE) uninstall
-	cd ivlpp ; $(MAKE) uninstall
-	for tgt in $(SUBDIRS); do (cd $$tgt ; $(MAKE) uninstall); done
-	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) uninstall); done


 -include $(patsubst %.o, dep/%.d, $O)
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: Module.cc,v 1.19 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: Module.cc,v 1.25 2004/10/04 01:10:51 steve Exp $"
 #endif

 # include "config.h"
@@ -27,14 +27,15 @@
 # include  "PWire.h"
 # include  <assert.h>

-Module::Module(const char*name)
-: name_(strdup(name))
+/* n is a permallocated string. */
+Module::Module(perm_string n)
+: name_(n)
 {
+      default_nettype = NetNet::NONE;
 }

 Module::~Module()
 {
-      free(name_);
 }

 void Module::add_gate(PGate*gate)
@@ -42,12 +43,12 @@ void Module::add_gate(PGate*gate)
      gates_.push_back(gate);
 }

-void Module::add_task(const string&name, PTask*task)
+void Module::add_task(perm_string name, PTask*task)
 {
      tasks_[name] = task;
 }

-void Module::add_function(const string &name, PFunction *func)
+void Module::add_function(perm_string name, PFunction *func)
 {
      funcs_[name] = func;
 }
@@ -75,7 +76,7 @@ unsigned Module::port_count() const
 /*
 * Return the array of PEIdent object that are at this port of the
 * module. If the port is internally unconnected, return an empty
- * array. 
+ * array.
 */
 const svector<PEIdent*>& Module::get_port(unsigned idx) const
 {
@@ -88,12 +89,22 @@ const svector<PEIdent*>& Module::get_port(unsigned idx) const
 	    return zero;
 }

-unsigned Module::find_port(const string&name) const
+unsigned Module::find_port(const char*name) const
 {
      assert(name != "");
-      for (unsigned idx = 0 ;  idx < ports.count() ;  idx += 1)
+      for (unsigned idx = 0 ;  idx < ports.count() ;  idx += 1) {
+	    if (ports[idx] == 0) {
+		    /* It is possible to have undeclared ports. These
+		       are ports that are skipped in the declaration,
+		       for example like so: module foo(x ,, y); The
+		       port between x and y is unnamed and thus
+		       inaccessible to binding by name. */
+		  continue;
+	    }
+	    assert(ports[idx]);
 	    if (ports[idx]->name == name)
 		  return idx;
+      }

      return ports.count();
 }
@@ -108,7 +119,7 @@ PWire* Module::get_wire(const hname_t&name) const
 	    return (*obj).second;
 }

-PGate* Module::get_gate(const string&name)
+PGate* Module::get_gate(perm_string name)
 {
      for (list<PGate*>::iterator cur = gates_.begin()
 		 ; cur != gates_.end()
@@ -139,6 +150,24 @@ const list<PProcess*>& Module::get_behaviors() const

 /*
 * $Log: Module.cc,v $
+ * Revision 1.25  2004/10/04 01:10:51  steve
+ *  Clean up spurious trailing white space.
+ *
+ * Revision 1.24  2004/06/13 04:56:53  steve
+ *  Add support for the default_nettype directive.
+ *
+ * Revision 1.23  2004/02/20 06:22:56  steve
+ *  parameter keys are per_strings.
+ *
+ * Revision 1.22  2004/02/18 17:11:54  steve
+ *  Use perm_strings for named langiage items.
+ *
+ * Revision 1.21  2003/04/02 03:00:14  steve
+ *  Cope with empty module ports while binding by name.
+ *
+ * Revision 1.20  2003/03/06 04:37:12  steve
+ *  lex_strings.add module names earlier.
+ *
 * Revision 1.19  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -1,7 +1,7 @@
 #ifndef __Module_H
 #define __Module_H
 /*
- * Copyright (c) 1998-2000 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2004 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,20 +19,22 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: Module.h,v 1.27 2002/08/19 02:39:16 steve Exp $"
+#ident "$Id: Module.h,v 1.40 2006/04/10 00:37:42 steve Exp $"
 #endif

 # include  <list>
 # include  <map>
 # include  "svector.h"
+# include  "StringHeap.h"
 # include  "HName.h"
 # include  "named.h"
 # include  "LineInfo.h"
-# include  <string>
+# include  "netlist.h"
 class PEvent;
 class PExpr;
 class PEIdent;
 class PGate;
+class PGenerate;
 class PTask;
 class PFunction;
 class PWire;
@@ -55,14 +57,17 @@ class Module : public LineInfo {
 	   the port. */
    public:
      struct port_t {
-	    string name;
+	    perm_string name;
 	    svector<PEIdent*> expr;
      };

    public:
-      explicit Module(const char*name);
+	/* The name passed here is the module name, not the instance
+	   name. This make must be a permallocated string. */
+      explicit Module(perm_string name);
      ~Module();

+      NetNet::Type default_nettype;

 	/* The module has parameters that are evaluated when the
 	   module is elaborated. During parsing, I put the parameters
@@ -73,8 +78,14 @@ class Module : public LineInfo {
 	    PExpr*lsb;
 	    bool signed_flag;
      };
-      map<string,param_expr_t>parameters;
-      map<string,param_expr_t>localparams;
+      map<perm_string,param_expr_t>parameters;
+      map<perm_string,param_expr_t>localparams;
+
+
+	/* specparams are simpler then other params, in that they have
+	   no type information. They are merely constant
+	   expressions. */
+      map<perm_string,PExpr*>specparams;

 	/* The module also has defparam assignments which don't create
 	   new parameters within the module, but may be used to set
@@ -88,20 +99,30 @@ class Module : public LineInfo {
           appear in the instantiated module.  Therefore a
           list of names in module-order is needed to pass from
           a parameter-index to its name. */
-      list<string> param_names;
+      list<perm_string> param_names;

 	/* This is an array of port descriptors, which is in turn a
 	   named array of PEident pointers. */
      svector<port_t*> ports;

 	/* Keep a table of named events declared in the module. */
-      map<string,PEvent*>events;
+      map<perm_string,PEvent*>events;
+
+      map<perm_string,PExpr*> attributes;

 	/* These are the timescale for this module. The default is
 	   set by the `timescale directive. */
      int time_unit, time_precision;

-      const char*mod_name() const { return name_; }
+	/* The module has a list of genvars that may be used in
+	   various generate schemes. */
+      list<perm_string> genvars;
+
+	/* the module has a list of generate schemes that appear in
+	   the module definition. These are used at elaboration time. */
+      list<PGenerate*> generate_schemes;
+
+      perm_string mod_name() const { return name_; }

      void add_gate(PGate*gate);

@@ -111,17 +132,17 @@ class Module : public LineInfo {
      PWire* add_wire(PWire*wire);

      void add_behavior(PProcess*behave);
-      void add_task(const string&name, PTask*def);
-      void add_function(const string&name, PFunction*def);
+      void add_task(perm_string name, PTask*def);
+      void add_function(perm_string name, PFunction*def);

      unsigned port_count() const;
      const svector<PEIdent*>& get_port(unsigned idx) const;
-      unsigned find_port(const string&) const;
+      unsigned find_port(const char*name) const;

 	// Find a wire by name. This is used for connecting gates to
 	// existing wires, etc.
      PWire* get_wire(const hname_t&name) const;
-      PGate* get_gate(const string&name);
+      PGate* get_gate(perm_string name);

      const map<hname_t,PWire*>& get_wires() const;
      const list<PGate*>& get_gates() const;
@@ -130,18 +151,19 @@ class Module : public LineInfo {
      void dump(ostream&out) const;
      bool elaborate(Design*, NetScope*scope) const;

-      bool elaborate_scope(Design*, NetScope*scope) const;
+      typedef map<perm_string,NetExpr*> replace_t;
+      bool elaborate_scope(Design*, NetScope*scope, const replace_t&rep) const;

      bool elaborate_sig(Design*, NetScope*scope) const;

    private:
-      char* name_;
+      perm_string name_;

      map<hname_t,PWire*> wires_;
      list<PGate*> gates_;
      list<PProcess*> behaviors_;
-      map<string,PTask*> tasks_;
-      map<string,PFunction*> funcs_;
+      map<perm_string,PTask*> tasks_;
+      map<perm_string,PFunction*> funcs_;

    private: // Not implemented
      Module(const Module&);
@@ -151,105 +173,13 @@ class Module : public LineInfo {

 /*
 * $Log: Module.h,v $
- * Revision 1.27  2002/08/19 02:39:16  steve
- *  Support parameters with defined ranges.
+ * Revision 1.40  2006/04/10 00:37:42  steve
+ *  Add support for generate loops w/ wires and gates.
 *
- * Revision 1.26  2002/08/12 01:34:58  steve
- *  conditional ident string using autoconfig.
- *
- * Revision 1.25  2002/05/19 23:37:28  steve
- *  Parse port_declaration_lists from the 2001 Standard.
- *
- * Revision 1.24  2001/12/03 04:47:14  steve
- *  Parser and pform use hierarchical names as hname_t
- *  objects instead of encoded strings.
- *
- * Revision 1.23  2001/10/31 03:11:15  steve
- *  detect module ports not declared within the module.
- *
- * Revision 1.22  2001/10/20 05:21:51  steve
- *  Scope/module names are char* instead of string.
- *
- * Revision 1.21  2000/11/05 06:05:59  steve
- *  Handle connectsion to internally unconnected modules (PR#38)
- *
- * Revision 1.20  2000/07/22 22:09:03  steve
- *  Parse and elaborate timescale to scopes.
- *
- * Revision 1.19  2000/05/16 04:05:15  steve
- *  Module ports are really special PEIdent
- *  expressions, because a name can be used
- *  many places in the port list.
- *
- * Revision 1.18  2000/05/02 16:27:38  steve
- *  Move signal elaboration to a seperate pass.
- *
- * Revision 1.17  2000/04/01 19:31:57  steve
- *  Named events as far as the pform.
- *
- * Revision 1.16  2000/03/12 17:09:40  steve
- *  Support localparam.
- *
- * Revision 1.15  2000/03/08 04:36:53  steve
- *  Redesign the implementation of scopes and parameters.
- *  I now generate the scopes and notice the parameters
- *  in a separate pass over the pform. Once the scopes
- *  are generated, I can process overrides and evalutate
- *  paremeters before elaboration begins.
- *
- * Revision 1.14  2000/02/23 02:56:53  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.13  2000/01/09 20:37:57  steve
- *  Careful with wires connected to multiple ports.
- *
- * Revision 1.12  2000/01/09 05:50:48  steve
- *  Support named parameter override lists.
- *
- * Revision 1.11  1999/12/11 05:45:41  steve
- *  Fix support for attaching attributes to primitive gates.
- *
- * Revision 1.10  1999/11/27 19:07:57  steve
- *  Support the creation of scopes.
- *
- * Revision 1.9  1999/08/23 16:48:39  steve
- *  Parameter overrides support from Peter Monta
- *  AND and XOR support wide expressions.
- *
- * Revision 1.8  1999/08/04 02:13:02  steve
- *  Elaborate module ports that are concatenations of
- *  module signals.
- *
- * Revision 1.7  1999/08/03 04:14:49  steve
- *  Parse into pform arbitrarily complex module
- *  port declarations.
- *
- * Revision 1.6  1999/07/31 19:14:47  steve
- *  Add functions up to elaboration (Ed Carter)
- *
- * Revision 1.5  1999/07/03 02:12:51  steve
- *  Elaborate user defined tasks.
- *
- * Revision 1.4  1999/06/15 03:44:53  steve
- *  Get rid of the STL vector template.
- *
- * Revision 1.3  1999/02/21 17:01:57  steve
- *  Add support for module parameters.
- *
- * Revision 1.2  1999/01/25 05:45:56  steve
- *  Add the LineInfo class to carry the source file
- *  location of things. PGate, Statement and PProcess.
- *
- *  elaborate handles module parameter mismatches,
- *  missing or incorrect lvalues for procedural
- *  assignment, and errors are propogated to the
- *  top of the elaboration call tree.
- *
- *  Attach line numbers to processes, gates and
- *  assignment statements.
- *
- * Revision 1.1  1998/11/03 23:28:52  steve
- *  Introduce verilog to CVS.
+ * Revision 1.39  2006/03/30 01:49:07  steve
+ *  Fix instance arrays indexed by overridden parameters.
 *
+ * Revision 1.38  2005/07/11 16:56:50  steve
+ *  Remove NetVariable and ivl_variable_t structures.
 */
 #endif
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PDelays.cc,v 1.9 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PDelays.cc,v 1.15 2006/07/08 21:48:46 steve Exp $"
 #endif

 # include "config.h"
@@ -62,54 +62,92 @@ void PDelays::set_delays(const svector<PExpr*>*del, bool df)
      delete_flag_ = df;
 }

-static unsigned long calculate_val(Design*des, const NetScope*scope,
-				   const PExpr*expr)
+static NetExpr*calculate_val(Design*des, NetScope*scope, const PExpr*expr)
 {
-      assert(expr);
-      unsigned long val;

-      int shift = scope->time_unit() - des->get_precision();
-
-      if (verireal*dr = expr->eval_rconst(des, scope)) {
-	    val = dr->as_long(shift);
-	    delete dr;
-
-      } else {
-	    verinum*dv = expr->eval_const(des, scope);
-	    if (dv == 0) {
-		  cerr << expr->get_line() << ": sorry: non-constant "
-		       << "delays not supported here: " << *expr << endl;
-		  des->errors += 1;
-		  return 0;
-	    }
-
-	    assert(dv);
-	    val = dv->as_ulong();
-	    val = des->scale_to_precision(val, scope);
-	    delete dv;
+      NetExpr*dex = expr->elaborate_expr(des, scope, -1, false);
+      if (NetExpr*tmp = dex->eval_tree()) {
+	    delete dex;
+	    dex = tmp;
      }

-      return val;
+	/* If the delay expression is a real constant or vector
+	   constant, then evaluate it, scale it to the local time
+	   units, and return an adjusted value. */
+
+      if (NetECReal*tmp = dynamic_cast<NetECReal*>(dex)) {
+	    verireal fn = tmp->value();
+
+	    int shift = scope->time_unit() - des->get_precision();
+	    long delay = fn.as_long(shift);
+	    if (delay < 0)
+		  delay = 0;
+
+	    delete tmp;
+	    NetEConst*tmp2 = new NetEConst(verinum(delay));
+	    tmp2->set_line(*expr);
+	    return tmp2;
+      }
+
+
+      if (NetEConst*tmp = dynamic_cast<NetEConst*>(dex)) {
+	    verinum fn = tmp->value();
+
+	    unsigned long delay =
+		  des->scale_to_precision(fn.as_ulong(), scope);
+
+	    delete tmp;
+	    NetEConst*tmp2 = new NetEConst(verinum(delay));
+	    tmp2->set_line(*expr);
+	    return tmp2;
+      }
+
+	/* Oops, cannot evaluate down to a constant. */
+      return dex;
+}
+
+static NetExpr* make_delay_nets(Design*des, NetExpr*expr)
+{
+      if (dynamic_cast<NetESignal*> (expr))
+	    return expr;
+
+      if (dynamic_cast<NetEConst*> (expr))
+	    return expr;
+
+      NetNet*sig = expr->synthesize(des);
+      if (sig == 0) {
+	    cerr << expr->get_line() << ": error: Expression " << *expr
+		 << " is not suitable for delay expression." << endl;
+	    return 0;
+      }
+
+      expr = new NetESignal(sig);
+      return expr;
 }

 void PDelays::eval_delays(Design*des, NetScope*scope,
-			  unsigned long&rise_time,
-			  unsigned long&fall_time,
-			  unsigned long&decay_time) const
+			  NetExpr*&rise_time,
+			  NetExpr*&fall_time,
+			  NetExpr*&decay_time,
+			  bool as_nets_flag) const
 {
      assert(scope);

-      int shift = scope->time_unit() - des->get_precision();
-

      if (delay_[0]) {
 	    rise_time = calculate_val(des, scope, delay_[0]);
+	    if (as_nets_flag)
+		  rise_time = make_delay_nets(des, rise_time);

 	    if (delay_[1]) {
 		  fall_time = calculate_val(des, scope, delay_[1]);
+		  if (as_nets_flag)
+			fall_time = make_delay_nets(des, fall_time);

 		  if (delay_[2]) {
 			decay_time = calculate_val(des, scope, delay_[2]);
+		  if (as_nets_flag)
+			decay_time = make_delay_nets(des, decay_time);

 		  } else {
 			if (rise_time < fall_time)
@@ -131,6 +169,30 @@ void PDelays::eval_delays(Design*des, NetScope*scope,

 /*
 * $Log: PDelays.cc,v $
+ * Revision 1.15  2006/07/08 21:48:46  steve
+ *  Handle real valued literals in net contexts.
+ *
+ * Revision 1.14  2006/06/02 04:48:49  steve
+ *  Make elaborate_expr methods aware of the width that the context
+ *  requires of it. In the process, fix sizing of the width of unary
+ *  minus is context determined sizes.
+ *
+ * Revision 1.13  2006/01/03 05:22:14  steve
+ *  Handle complex net node delays.
+ *
+ * Revision 1.12  2006/01/02 05:33:19  steve
+ *  Node delays can be more general expressions in structural contexts.
+ *
+ * Revision 1.11  2003/06/21 01:21:42  steve
+ *  Harmless fixup of warnings.
+ *
+ * Revision 1.10  2003/02/08 19:49:21  steve
+ *  Calculate delay statement delays using elaborated
+ *  expressions instead of pre-elaborated expression
+ *  trees.
+ *
+ *  Remove the eval_pexpr methods from PExpr.
+ *
 * Revision 1.9  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -19,7 +19,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PDelays.h,v 1.7 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PDelays.h,v 1.9 2006/01/03 05:22:14 steve Exp $"
 #endif

 # include  "svector.h"
@@ -34,6 +34,7 @@ using namespace std;

 class Design;
 class NetScope;
+class NetExpr;
 class PExpr;

 /*
@@ -53,9 +54,10 @@ class PDelays {
      void set_delays(const svector<PExpr*>*del, bool delete_flag=true);

      void eval_delays(Design*des, NetScope*scope,
-		       unsigned long&rise_time,
-		       unsigned long&fall_time,
-		       unsigned long&decay_time) const;
+		       NetExpr*&rise_time,
+		       NetExpr*&fall_time,
+		       NetExpr*&decay_time,
+		       bool as_nets_flag =false) const;

      void dump_delays(ostream&out) const;

@@ -72,6 +74,12 @@ ostream& operator << (ostream&o, const PDelays&);

 /*
 * $Log: PDelays.h,v $
+ * Revision 1.9  2006/01/03 05:22:14  steve
+ *  Handle complex net node delays.
+ *
+ * Revision 1.8  2006/01/02 05:33:19  steve
+ *  Node delays can be more general expressions in structural contexts.
+ *
 * Revision 1.7  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 200Stephen Williams ([email protected])
+ * Copyright (c) 2004 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,14 +17,14 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PEvent.cc,v 1.3 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PEvent.cc,v 1.5 2004/02/19 06:57:10 steve Exp $"
 #endif

 # include "config.h"

 # include  "PEvent.h"

-PEvent::PEvent(const string&n)
+PEvent::PEvent(perm_string n)
 : name_(n)
 {
 }
@@ -33,13 +33,22 @@ PEvent::~PEvent()
 {
 }

-string PEvent::name() const
+perm_string  PEvent::name() const
 {
      return name_;
 }

 /*
 * $Log: PEvent.cc,v $
+ * Revision 1.5  2004/02/19 06:57:10  steve
+ *  Memory and Event names use perm_string.
+ *
+ * Revision 1.4  2003/03/01 06:25:30  steve
+ *  Add the lex_strings string handler, and put
+ *  scope names and system task/function names
+ *  into this table. Also, permallocate event
+ *  names from the beginning.
+ *
 * Revision 1.3  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -1,7 +1,7 @@
 #ifndef __PEvent_H
 #define __PEvent_H
 /*
- * Copyright (c) 2000 Stephen Williams ([email protected])
+ * Copyright (c) 2000-2004 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,10 +19,11 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PEvent.h,v 1.6 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PEvent.h,v 1.9 2004/02/19 06:57:10 steve Exp $"
 #endif

 # include  "LineInfo.h"
+# include  "StringHeap.h"
 # include  <string>

 class Design;
@@ -31,20 +32,22 @@ class NetScope;
 /*
 * The PEvent class represents event objects. These are things that
 * are declared in Verilog as ``event foo;'' The name passed to the
- * constructure is the "foo" part of the declaration.
+ * constructor is the "foo" part of the declaration.
 */
 class PEvent : public LineInfo {

    public:
-      explicit PEvent(const string&name);
+	// The name is a perm-allocated string. It is the simple name
+	// of the event, without any scope.
+      explicit PEvent(perm_string name);
      ~PEvent();

-      string name() const;
+      perm_string name() const;

      void elaborate_scope(Design*des, NetScope*scope) const;

    private:
-      string name_;
+      perm_string name_;

    private: // not implemented
      PEvent(const PEvent&);
@@ -53,6 +56,18 @@ class PEvent : public LineInfo {

 /*
 * $Log: PEvent.h,v $
+ * Revision 1.9  2004/02/19 06:57:10  steve
+ *  Memory and Event names use perm_string.
+ *
+ * Revision 1.8  2003/03/01 06:25:30  steve
+ *  Add the lex_strings string handler, and put
+ *  scope names and system task/function names
+ *  into this table. Also, permallocate event
+ *  names from the beginning.
+ *
+ * Revision 1.7  2003/01/30 16:23:07  steve
+ *  Spelling fixes.
+ *
 * Revision 1.6  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PExpr.cc,v 1.31 2002/08/19 02:39:16 steve Exp $"
+#ident "$Id: PExpr.cc,v 1.37 2005/10/04 04:09:25 steve Exp $"
 #endif

 # include "config.h"
@@ -46,13 +46,21 @@ bool PExpr::is_constant(Module*) const
      return false;
 }

-NetNet* PExpr::elaborate_lnet(Design*des, NetScope*) const
+NetNet* PExpr::elaborate_lnet(Design*des, NetScope*, bool) const
 {
      cerr << get_line() << ": error: expression not valid in assign l-value: "
 	   << *this << endl;
      return 0;
 }

+NetNet* PExpr::elaborate_bi_net(Design*des, NetScope*) const
+{
+      cerr << get_line() << ": error: "
+	   << "expression not valid as argument to inout port: "
+	   << *this << endl;
+      return 0;
+}
+
 PEBinary::PEBinary(char op, PExpr*l, PExpr*r)
 : op_(op), left_(l), right_(r)
 {
@@ -67,12 +75,12 @@ bool PEBinary::is_constant(Module*mod) const
      return left_->is_constant(mod) && right_->is_constant(mod);
 }

-PECallFunction::PECallFunction(const hname_t&n, const svector<PExpr *> &parms) 
+PECallFunction::PECallFunction(const hname_t&n, const svector<PExpr *> &parms)
 : path_(n), parms_(parms)
 {
 }

-PECallFunction::PECallFunction(const hname_t&n) 
+PECallFunction::PECallFunction(const hname_t&n)
 : path_(n)
 {
 }
@@ -140,7 +148,7 @@ bool PEFNumber::is_constant(Module*) const
 }

 PEIdent::PEIdent(const hname_t&s)
-: path_(s), msb_(0), lsb_(0), idx_(0)
+: path_(s), msb_(0), lsb_(0), sel_(SEL_NONE), idx_(0)
 {
 }

@@ -154,20 +162,26 @@ const hname_t& PEIdent::path() const
 }

 /*
- * An identifier can be in a constant expresion if (and only if) it is
+ * An identifier can be in a constant expression if (and only if) it is
 * a parameter.
 */
 bool PEIdent::is_constant(Module*mod) const
 {
      if (mod == 0) return false;

-      { map<string,Module::param_expr_t>::const_iterator cur;
-        cur = mod->parameters.find(path_.peek_name(0));
+	/* This is a work-around for map not matching < even when
+	   there is a perm_string operator that can do the comprare.
+
+	   The real fix is to make the path_ carry perm_strings. */
+      perm_string tmp = perm_string::literal(path_.peek_name(0));
+
+      { map<perm_string,Module::param_expr_t>::const_iterator cur;
+        cur = mod->parameters.find(tmp);
 	if (cur != mod->parameters.end()) return true;
      }

-      { map<string,Module::param_expr_t>::const_iterator cur;
-        cur = mod->localparams.find(path_.peek_name(0));
+      { map<perm_string,Module::param_expr_t>::const_iterator cur;
+        cur = mod->localparams.find(tmp);
 	if (cur != mod->localparams.end()) return true;
      }

@@ -256,6 +270,24 @@ bool PEUnary::is_constant(Module*m) const

 /*
 * $Log: PExpr.cc,v $
+ * Revision 1.37  2005/10/04 04:09:25  steve
+ *  Add support for indexed select attached to parameters.
+ *
+ * Revision 1.36  2005/08/06 17:58:16  steve
+ *  Implement bi-directional part selects.
+ *
+ * Revision 1.35  2004/10/04 01:10:51  steve
+ *  Clean up spurious trailing white space.
+ *
+ * Revision 1.34  2004/02/20 06:22:56  steve
+ *  parameter keys are per_strings.
+ *
+ * Revision 1.33  2003/01/27 05:09:17  steve
+ *  Spelling fixes.
+ *
+ * Revision 1.32  2002/11/09 19:20:48  steve
+ *  Port expressions for output ports are lnets, not nets.
+ *
 * Revision 1.31  2002/08/19 02:39:16  steve
 *  Support parameters with defined ranges.
 *
@@ -19,13 +19,13 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PExpr.h,v 1.62 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PExpr.h,v 1.83 2006/06/18 04:15:50 steve Exp $"
 #endif

 # include  <string>
+# include  <vector>
 # include  "netlist.h"
 # include  "verinum.h"
-# include  "verireal.h"
 # include  "LineInfo.h"

 class Design;
@@ -51,11 +51,13 @@ class PExpr : public LineInfo {

      virtual void dump(ostream&) const;

-	// Procedural elaboration of the expression. Set thie
-	// bare_memory_ok flag if the result is allowed to be a
-	// NetEMemory without an index.
+	// Procedural elaboration of the expression. The expr_width is
+	// the width of the context of the expression (i.e. the
+	// l-value width of an assignment) or -1 if the expression is
+	// self-determinted. The sys_task_arg flag is true if
+	// expressions are allowed to be incomplete.
      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
-				     bool sys_task_arg =false) const;
+				     int expr_width, bool sys_task_arg) const;

 	// Elaborate expressions that are the r-value of parameter
 	// assignments. This elaboration follows the restrictions of
@@ -67,34 +69,37 @@ class PExpr : public LineInfo {
 	// continuous assign or other wholly structural context.
      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned lwidth,
-				    unsigned long rise,
-				    unsigned long fall,
-				    unsigned long decay,
+				    const NetExpr* rise,
+				    const NetExpr* fall,
+				    const NetExpr* decay,
 				    Link::strength_t drive0 =Link::STRONG,
 				    Link::strength_t drive1 =Link::STRONG)
 	    const;

-	// This method elaborates the expression as NetNet objects. It
-	// only allows regs suitable for procedural continuous assignments.
-      virtual NetNet* elaborate_anet(Design*des, NetScope*scope) const;
-
 	// This method elaborates the expression as gates, but
 	// restricted for use as l-values of continuous assignments.
-      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope) const;
+      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope,
+				     bool implicit_net_ok =false) const;
+
+	// This is similar to elaborate_lnet, except that the
+	// expression is evaluated to be bi-directional. This is
+	// useful for arguments to inout ports of module instances and
+	// ports of tran primitives.
+      virtual NetNet* elaborate_bi_net(Design*des, NetScope*scope) const;

 	// Expressions that can be in the l-value of procedural
-	// assignments can be elaborated with this method.
-      virtual NetAssign_* elaborate_lval(Design*des, NetScope*scope) const;
+	// assignments can be elaborated with this method. If the
+	// is_force flag is true, then the set of valid l-value types
+	// is slightly modified to accomodate the Verilog force
+	// statement
+      virtual NetAssign_* elaborate_lval(Design*des,
+					 NetScope*scope,
+					 bool is_force) const;

 	// This attempts to evaluate a constant expression, and return
 	// a verinum as a result. If the expression cannot be
 	// evaluated, return 0.
-      virtual verinum* eval_const(const Design*des, const NetScope*sc) const;
-
-	// This attempts to evaluate a constant expression as a
-	// decimal floating point. This is used when calculating delay
-	// constants.
-      virtual verireal* eval_rconst(const Design*, const NetScope*) const;
+      virtual verinum* eval_const(const Design*des, NetScope*sc) const;

 	// This method returns true if that expression is the same as
 	// this expression. This method is used for comparing
@@ -104,7 +109,7 @@ class PExpr : public LineInfo {
 	// Return true if this expression is a valid constant
 	// expression. the Module pointer is needed to find parameter
 	// identifiers and any other module specific interpretations
-	// of expresions.
+	// of expressions.
      virtual bool is_constant(Module*) const;

    private: // not implemented
@@ -120,26 +125,31 @@ class PEConcat : public PExpr {
      PEConcat(const svector<PExpr*>&p, PExpr*r =0);
      ~PEConcat();

+      virtual verinum* eval_const(const Design*des, NetScope*sc) const;
      virtual void dump(ostream&) const;

-	// Concatenated Regs can be on the left of procedural
-	// continuous assignments.
-      virtual NetNet* elaborate_anet(Design*des, NetScope*scope) const;
-
-      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope) const;
+      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope,
+				     bool implicit_net_ok =false) const;
+      virtual NetNet* elaborate_bi_net(Design*des, NetScope*scope) const;
      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned width,
-				    unsigned long rise,
-				    unsigned long fall,
-				    unsigned long decay,
+				    const NetExpr* rise,
+				    const NetExpr* fall,
+				    const NetExpr* decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
      virtual NetExpr*elaborate_expr(Design*des, NetScope*,
-				     bool sys_task_arg =false) const;
+				     int expr_width, bool sys_task_arg) const;
      virtual NetEConcat*elaborate_pexpr(Design*des, NetScope*) const;
-      virtual NetAssign_* elaborate_lval(Design*des, NetScope*scope) const;
+      virtual NetAssign_* elaborate_lval(Design*des,
+					 NetScope*scope,
+					 bool is_force) const;
      virtual bool is_constant(Module*) const;

+    private:
+      NetNet* elaborate_lnet_common_(Design*des, NetScope*scope,
+				     bool implicit_net_ok,
+				     bool bidirectional_flag) const;
    private:
      svector<PExpr*>parms_;
      PExpr*repeat_;
@@ -164,7 +174,7 @@ class PEEvent : public PExpr {

      edge_t type() const;
      PExpr* expr() const;
- 
+
      virtual void dump(ostream&) const;

    private:
@@ -186,18 +196,23 @@ class PEFNumber : public PExpr {
 	/* The eval_const method as applied to a floating point number
 	   gets the *integer* value of the number. This accounts for
 	   any rounding that is needed to get the value. */
-      virtual verinum* eval_const(const Design*des, const NetScope*sc) const;
-
-	/* This method returns the full floating point value. */
-      virtual verireal* eval_rconst(const Design*, const NetScope*) const;
+      virtual verinum* eval_const(const Design*des, NetScope*sc) const;

 	/* A PEFNumber is a constant, so this returns true. */
      virtual bool is_constant(Module*) const;

      virtual NetExpr*elaborate_expr(Design*des, NetScope*,
-				     bool sys_task_arg =false) const;
+				     int expr_width, bool sys_task_arg) const;
      virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;

+      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
+				    unsigned lwidth,
+				    const NetExpr* rise,
+				    const NetExpr* fall,
+				    const NetExpr* decay,
+				    Link::strength_t drive0,
+				    Link::strength_t drive1) const;
+
      virtual void dump(ostream&) const;

    private:
@@ -212,26 +227,28 @@ class PEIdent : public PExpr {

      virtual void dump(ostream&) const;

-	// Regs can be on the left of procedural continuous assignments
-      virtual NetNet* elaborate_anet(Design*des, NetScope*scope) const;
-
 	// Identifiers are allowed (with restrictions) is assign l-values.
-      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope) const;
+      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope,
+				     bool implicit_net_ok =false) const;
+
+      virtual NetNet* elaborate_bi_net(Design*des, NetScope*scope) const;

 	// Identifiers are also allowed as procedural assignment l-values.
-      virtual NetAssign_* elaborate_lval(Design*des, NetScope*scope) const;
+      virtual NetAssign_* elaborate_lval(Design*des,
+					 NetScope*scope,
+					 bool is_force) const;

 	// Structural r-values are OK.
      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned lwidth,
-				    unsigned long rise,
-				    unsigned long fall,
-				    unsigned long decay,
+				    const NetExpr* rise,
+				    const NetExpr* fall,
+				    const NetExpr* decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;

      virtual NetExpr*elaborate_expr(Design*des, NetScope*,
-				     bool sys_task_arg =false) const;
+				     int expr_width, bool sys_task_arg) const;
      virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;

 	// Elaborate the PEIdent as a port to a module. This method
@@ -239,34 +256,67 @@ class PEIdent : public PExpr {
      NetNet* elaborate_port(Design*des, NetScope*sc) const;

      virtual bool is_constant(Module*) const;
-      verinum* eval_const(const Design*des, const NetScope*sc) const;
-      verireal*eval_rconst(const Design*des, const NetScope*sc) const;
+      verinum* eval_const(const Design*des, NetScope*sc) const;

      const hname_t& path() const;

    private:
+      NetAssign_*elaborate_lval_net_part_(Design*, NetScope*, NetNet*) const;
+      NetAssign_*elaborate_lval_net_idx_up_(Design*, NetScope*, NetNet*) const;
+      NetAssign_*elaborate_lval_net_idx_do_(Design*, NetScope*, NetNet*) const;
+
+    private:
+      NetExpr*elaborate_expr_param(Design*des,
+				   NetScope*scope,
+				   const NetExpr*par,
+				   NetScope*found,
+				   const NetExpr*par_msb,
+				   const NetExpr*par_lsb) const;
+      NetExpr*elaborate_expr_net(Design*des,
+				   NetScope*scope,
+				   NetNet*net,
+				   NetScope*found) const;
+      NetExpr*elaborate_expr_net_part_(Design*des,
+				   NetScope*scope,
+				   NetNet*net,
+				   NetScope*found) const;
+      NetExpr*elaborate_expr_net_idx_up_(Design*des,
+				   NetScope*scope,
+				   NetNet*net,
+				   NetScope*found) const;
+      NetExpr*elaborate_expr_net_idx_do_(Design*des,
+				   NetScope*scope,
+				   NetNet*net,
+				   NetScope*found) const;
+      NetExpr*elaborate_expr_net_bit_(Design*des,
+				   NetScope*scope,
+				   NetNet*net,
+				   NetScope*found) const;
      hname_t path_;

    public:
-	// Use these to support bit- and part-select operators.
+	// Use these to support part-select operators.
      PExpr*msb_;
      PExpr*lsb_;

-	// If this is a reference to a memory, this is the index
-	// expression.
-      PExpr*idx_;
+      enum { SEL_NONE, SEL_PART, SEL_IDX_UP, SEL_IDX_DO } sel_;
+
+	// If this is a reference to a memory/array, this is the index
+	// expression. If this is a reference to a vector, this is a
+	// bit select.
+      std::vector<PExpr*> idx_;

      NetNet* elaborate_net_ram_(Design*des, NetScope*scope,
 				 NetMemory*mem, unsigned lwidth,
-				 unsigned long rise,
-				 unsigned long fall,
-				 unsigned long decay) const;
+				 const NetExpr* rise,
+				 const NetExpr* fall,
+				 const NetExpr* decay) const;

      NetNet* elaborate_net_bitmux_(Design*des, NetScope*scope,
 				    NetNet*sig,
-				    unsigned long rise,
-				    unsigned long fall,
-				    unsigned long decay,
+				    const NetExpr* rise,
+				    const NetExpr* fall,
+				    const NetExpr* decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;

@@ -274,6 +324,15 @@ class PEIdent : public PExpr {
      NetAssign_* elaborate_mem_lval_(Design*des, NetScope*scope,
 				      NetMemory*mem) const;

+      NetNet* elaborate_lnet_common_(Design*des, NetScope*scope,
+				     bool implicit_net_ok,
+				     bool bidirectional_flag) const;
+
+      NetNet*make_implicit_net_(Design*des, NetScope*scope) const;
+
+      bool eval_part_select_(Design*des, NetScope*scope, NetNet*sig,
+			     unsigned&midx, unsigned&lidx) const;
+
 };

 class PENumber : public PExpr {
@@ -287,18 +346,19 @@ class PENumber : public PExpr {
      virtual void dump(ostream&) const;
      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned lwidth,
-				    unsigned long rise,
-				    unsigned long fall,
-				    unsigned long decay,
+				    const NetExpr* rise,
+				    const NetExpr* fall,
+				    const NetExpr* decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
      virtual NetEConst*elaborate_expr(Design*des, NetScope*,
-				     bool sys_task_arg =false) const;
+				       int expr_width, bool) const;
      virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
-      virtual NetAssign_* elaborate_lval(Design*des, NetScope*scope) const;
+      virtual NetAssign_* elaborate_lval(Design*des,
+					 NetScope*scope,
+					 bool is_force) const;

-      virtual verinum* eval_const(const Design*des, const NetScope*sc) const;
-      virtual verireal*eval_rconst(const Design*, const NetScope*) const;
+      virtual verinum* eval_const(const Design*des, NetScope*sc) const;

      virtual bool is_the_same(const PExpr*that) const;
      virtual bool is_constant(Module*) const;
@@ -324,15 +384,15 @@ class PEString : public PExpr {
      virtual void dump(ostream&) const;
      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned width,
-				    unsigned long rise,
-				    unsigned long fall,
-				    unsigned long decay,
+				    const NetExpr* rise,
+				    const NetExpr* fall,
+				    const NetExpr* decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
      virtual NetEConst*elaborate_expr(Design*des, NetScope*,
-				     bool sys_task_arg =false) const;
+				       int expr_width, bool) const;
      virtual NetEConst*elaborate_pexpr(Design*des, NetScope*sc) const;
-      verinum* PEString::eval_const(const Design*, const NetScope*) const;
+      verinum* eval_const(const Design*, NetScope*) const;

      virtual bool is_constant(Module*) const;

@@ -349,15 +409,15 @@ class PEUnary : public PExpr {
      virtual void dump(ostream&out) const;
      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned width,
-				    unsigned long rise,
-				    unsigned long fall,
-				    unsigned long decay,
+				    const NetExpr* rise,
+				    const NetExpr* fall,
+				    const NetExpr* decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
      virtual NetExpr*elaborate_expr(Design*des, NetScope*,
-				     bool sys_task_arg =false) const;
+				     int expr_width, bool sys_task_arg) const;
      virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
-      virtual verinum* eval_const(const Design*des, const NetScope*sc) const;
+      virtual verinum* eval_const(const Design*des, NetScope*sc) const;

      virtual bool is_constant(Module*) const;

@@ -377,16 +437,15 @@ class PEBinary : public PExpr {
      virtual void dump(ostream&out) const;
      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned width,
-				    unsigned long rise,
-				    unsigned long fall,
-				    unsigned long decay,
+				    const NetExpr* rise,
+				    const NetExpr* fall,
+				    const NetExpr* decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
      virtual NetEBinary*elaborate_expr(Design*des, NetScope*,
-					bool sys_task_arg =false) const;
+					int expr_width, bool sys_task_arg) const;
      virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
-      virtual verinum* eval_const(const Design*des, const NetScope*sc) const;
-      virtual verireal*eval_rconst(const Design*des, const NetScope*sc) const;
+      virtual verinum* eval_const(const Design*des, NetScope*sc) const;

    private:
      char op_;
@@ -397,44 +456,44 @@ class PEBinary : public PExpr {

      NetNet* elaborate_net_add_(Design*des, NetScope*scope,
 				 unsigned lwidth,
-				 unsigned long rise,
-				 unsigned long fall,
-				 unsigned long decay) const;
+				 const NetExpr* rise,
+				 const NetExpr* fall,
+				 const NetExpr* decay) const;
      NetNet* elaborate_net_bit_(Design*des, NetScope*scope,
 				 unsigned lwidth,
-				 unsigned long rise,
-				 unsigned long fall,
-				 unsigned long decay) const;
+				 const NetExpr* rise,
+				 const NetExpr* fall,
+				 const NetExpr* decay) const;
      NetNet* elaborate_net_cmp_(Design*des, NetScope*scope,
 				 unsigned lwidth,
-				 unsigned long rise,
-				 unsigned long fall,
-				 unsigned long decay) const;
+				 const NetExpr* rise,
+				 const NetExpr* fall,
+				 const NetExpr* decay) const;
      NetNet* elaborate_net_div_(Design*des, NetScope*scope,
 				 unsigned lwidth,
-				 unsigned long rise,
-				 unsigned long fall,
-				 unsigned long decay) const;
+				 const NetExpr* rise,
+				 const NetExpr* fall,
+				 const NetExpr* decay) const;
      NetNet* elaborate_net_mod_(Design*des, NetScope*scope,
 				 unsigned lwidth,
-				 unsigned long rise,
-				 unsigned long fall,
-				 unsigned long decay) const;
+				 const NetExpr* rise,
+				 const NetExpr* fall,
+				 const NetExpr* decay) const;
      NetNet* elaborate_net_log_(Design*des, NetScope*scope,
 				 unsigned lwidth,
-				 unsigned long rise,
-				 unsigned long fall,
-				 unsigned long decay) const;
+				 const NetExpr* rise,
+				 const NetExpr* fall,
+				 const NetExpr* decay) const;
      NetNet* elaborate_net_mul_(Design*des, NetScope*scope,
 				 unsigned lwidth,
-				 unsigned long rise,
-				 unsigned long fall,
-				 unsigned long decay) const;
+				 const NetExpr* rise,
+				 const NetExpr* fall,
+				 const NetExpr* decay) const;
      NetNet* elaborate_net_shift_(Design*des, NetScope*scope,
 				   unsigned lwidth,
-				   unsigned long rise,
-				   unsigned long fall,
-				   unsigned long decay) const;
+				   const NetExpr* rise,
+				   const NetExpr* fall,
+				   const NetExpr* decay) const;
 };

 /*
@@ -452,15 +511,15 @@ class PETernary : public PExpr {
      virtual void dump(ostream&out) const;
      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned width,
-				    unsigned long rise,
-				    unsigned long fall,
-				    unsigned long decay,
+				    const NetExpr* rise,
+				    const NetExpr* fall,
+				    const NetExpr* decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
      virtual NetETernary*elaborate_expr(Design*des, NetScope*,
-					 bool sys_task_arg =false) const;
+					 int expr_width, bool sys_task_arg) const;
      virtual NetETernary*elaborate_pexpr(Design*des, NetScope*sc) const;
-      virtual verinum* eval_const(const Design*des, const NetScope*sc) const;
+      virtual verinum* eval_const(const Design*des, NetScope*sc) const;

    private:
      PExpr*expr_;
@@ -482,13 +541,13 @@ class PECallFunction : public PExpr {
      virtual void dump(ostream &) const;
      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned width,
-				    unsigned long rise,
-				    unsigned long fall,
-				    unsigned long decay,
+				    const NetExpr* rise,
+				    const NetExpr* fall,
+				    const NetExpr* decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
-				     bool sys_task_arg =false) const;
+				     int expr_wid, bool sys_task_arg) const;

    private:
      hname_t path_;
@@ -497,10 +556,95 @@ class PECallFunction : public PExpr {
      bool check_call_matches_definition_(Design*des, NetScope*dscope) const;

      NetExpr* elaborate_sfunc_(Design*des, NetScope*scope) const;
+      NetNet* elaborate_net_sfunc_(Design*des, NetScope*scope,
+				   unsigned width,
+				   const NetExpr* rise,
+				   const NetExpr* fall,
+				   const NetExpr* decay,
+				   Link::strength_t drive0,
+				   Link::strength_t drive1) const;
 };

 /*
 * $Log: PExpr.h,v $
+ * Revision 1.83  2006/06/18 04:15:50  steve
+ *  Add support for system functions in continuous assignments.
+ *
+ * Revision 1.82  2006/06/02 04:48:49  steve
+ *  Make elaborate_expr methods aware of the width that the context
+ *  requires of it. In the process, fix sizing of the width of unary
+ *  minus is context determined sizes.
+ *
+ * Revision 1.81  2006/04/28 04:28:35  steve
+ *  Allow concatenations as arguments to inout ports.
+ *
+ * Revision 1.80  2006/04/16 00:54:04  steve
+ *  Cleanup lval part select handling.
+ *
+ * Revision 1.79  2006/04/16 00:15:43  steve
+ *  Fix part selects in l-values.
+ *
+ * Revision 1.78  2006/03/25 02:36:26  steve
+ *  Get rid of excess PESTring:: prefix within class declaration.
+ *
+ * Revision 1.77  2006/02/02 02:43:57  steve
+ *  Allow part selects of memory words in l-values.
+ *
+ * Revision 1.76  2006/01/02 05:33:19  steve
+ *  Node delays can be more general expressions in structural contexts.
+ *
+ * Revision 1.75  2005/12/07 04:04:23  steve
+ *  Allow constant concat expressions.
+ *
+ * Revision 1.74  2005/11/27 17:01:56  steve
+ *  Fix for stubborn compiler.
+ *
+ * Revision 1.73  2005/11/27 05:56:20  steve
+ *  Handle bit select of parameter with ranges.
+ *
+ * Revision 1.72  2005/11/10 13:28:11  steve
+ *  Reorganize signal part select handling, and add support for
+ *  indexed part selects.
+ *
+ *  Expand expression constant propagation to eliminate extra
+ *  sums in certain cases.
+ *
+ * Revision 1.71  2005/10/04 04:09:25  steve
+ *  Add support for indexed select attached to parameters.
+ *
+ * Revision 1.70  2005/08/06 17:58:16  steve
+ *  Implement bi-directional part selects.
+ *
+ * Revision 1.69  2005/07/07 16:22:49  steve
+ *  Generalize signals to carry types.
+ *
+ * Revision 1.68  2005/01/09 20:16:00  steve
+ *  Use PartSelect/PV and VP to handle part selects through ports.
+ *
+ * Revision 1.67  2004/12/29 23:55:43  steve
+ *  Unify elaboration of l-values for all proceedural assignments,
+ *  including assing, cassign and force.
+ *
+ *  Generate NetConcat devices for gate outputs that feed into a
+ *  vector results. Use this to hande gate arrays. Also let gate
+ *  arrays handle vectors of gates when the outputs allow for it.
+ *
+ * Revision 1.66  2004/10/04 01:10:51  steve
+ *  Clean up spurious trailing white space.
+ *
+ * Revision 1.65  2003/02/08 19:49:21  steve
+ *  Calculate delay statement delays using elaborated
+ *  expressions instead of pre-elaborated expression
+ *  trees.
+ *
+ *  Remove the eval_pexpr methods from PExpr.
+ *
+ * Revision 1.64  2003/01/30 16:23:07  steve
+ *  Spelling fixes.
+ *
+ * Revision 1.63  2002/11/09 19:20:48  steve
+ *  Port expressions for output ports are lnets, not nets.
+ *
 * Revision 1.62  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -17,16 +17,17 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PFunction.cc,v 1.6 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PFunction.cc,v 1.7 2004/05/31 23:34:36 steve Exp $"
 #endif

 # include "config.h"

 #include "PTask.h"

-PFunction::PFunction()
-: out_(0), ports_(0), statement_(0)
+PFunction::PFunction(perm_string name)
+: name_(name), ports_(0), statement_(0)
 {
+      return_type_.type = PTF_NONE;
 }

 PFunction::~PFunction()
@@ -46,14 +47,18 @@ void PFunction::set_statement(Statement*s)
      statement_ = s;
 }

-void PFunction::set_output(PWire*o)
+void PFunction::set_return(PTaskFuncArg t)
 {
-      assert(out_ == 0);
-      out_ = o;
+      return_type_ = t;
 }

 /*
 * $Log: PFunction.cc,v $
+ * Revision 1.7  2004/05/31 23:34:36  steve
+ *  Rewire/generalize parsing an elaboration of
+ *  function return values to allow for better
+ *  speed and more type support.
+ *
 * Revision 1.6  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2000 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2004 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PGate.cc,v 1.14 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PGate.cc,v 1.18 2006/01/03 05:22:14 steve Exp $"
 #endif

 # include "config.h"
@@ -27,7 +27,7 @@
 # include  "verinum.h"
 # include  <assert.h>

-PGate::PGate(const string&name,
+PGate::PGate(perm_string name,
 	     svector<PExpr*>*pins,
 	     const svector<PExpr*>*del)
 : name_(name), pins_(pins)
@@ -37,7 +37,7 @@ PGate::PGate(const string&name,
      str1_ = STRONG;
 }

-PGate::PGate(const string&name,
+PGate::PGate(perm_string name,
 	     svector<PExpr*>*pins,
 	     PExpr*del)
 : name_(name), pins_(pins)
@@ -47,7 +47,7 @@ PGate::PGate(const string&name,
      str1_ = STRONG;
 }

-PGate::PGate(const string&name, svector<PExpr*>*pins)
+PGate::PGate(perm_string name, svector<PExpr*>*pins)
 : name_(name), pins_(pins)
 {
      str0_ = STRONG;
@@ -90,22 +90,79 @@ void PGate::elaborate_scope(Design*, NetScope*) const
 * parameters. This method understands how to handle the different
 * numbers of expressions.
 */
+
+void PGate::eval_delays(Design*des, NetScope*scope,
+			NetExpr*&rise_expr,
+			NetExpr*&fall_expr,
+			NetExpr*&decay_expr,
+			bool as_net_flag) const
+{
+      delay_.eval_delays(des, scope,
+			 rise_expr, fall_expr, decay_expr,
+			 as_net_flag);
+}
+
 void PGate::eval_delays(Design*des, NetScope*scope,
 			unsigned long&rise_time,
 			unsigned long&fall_time,
 			unsigned long&decay_time) const
 {
-      delay_.eval_delays(des, scope, rise_time, fall_time, decay_time);
+      NetExpr*rise_expr, *fall_expr, *decay_expr;
+      delay_.eval_delays(des, scope, rise_expr, fall_expr, decay_expr);
+
+      if (rise_expr == 0) {
+	    rise_time = 0;
+	    fall_time = 0;
+	    decay_time = 0;
+      }
+
+      if (NetEConst*tmp = dynamic_cast<NetEConst*> (rise_expr)) {
+	    rise_time = tmp->value().as_ulong();
+
+      } else {
+	    cerr << get_line() << ": error: Delay expressions must be "
+		 << "constant here." << endl;
+	    cerr << get_line() << ":      : Cannot calculate "
+		 << *rise_expr << endl;
+	    des->errors += 1;
+	    rise_time = 0;
+      }
+
+      if (NetEConst*tmp = dynamic_cast<NetEConst*> (fall_expr)) {
+	    fall_time = tmp->value().as_ulong();
+
+      } else {
+	    if (fall_expr != rise_expr) {
+		  cerr << get_line() << ": error: Delay expressions must be "
+		       << "constant here." << endl;
+		  cerr << get_line() << ":      : Cannot calculate "
+		       << *rise_expr << endl;
+	    }
+	    des->errors += 1;
+	    fall_time = 0;
+      }
+
+      if (NetEConst*tmp = dynamic_cast<NetEConst*> (decay_expr)) {
+	    decay_time = tmp->value().as_ulong();
+
+      } else {
+	    cerr << get_line() << ": error: Delay expressions must be "
+		 << "constant here." << endl;
+	    cerr << get_line() << ":      : Cannot calculate "
+		 << *rise_expr << endl;
+	    des->errors += 1;
+	    decay_time = 0;
+      }
 }

 PGAssign::PGAssign(svector<PExpr*>*pins)
-: PGate("", pins)
+: PGate(perm_string(), pins)
 {
      assert(pins->count() == 2);
 }

 PGAssign::PGAssign(svector<PExpr*>*pins, svector<PExpr*>*dels)
-: PGate("", pins, dels)
+: PGate(perm_string(), pins, dels)
 {
      assert(pins->count() == 2);
 }
@@ -114,14 +171,14 @@ PGAssign::~PGAssign()
 {
 }

-PGBuiltin::PGBuiltin(Type t, const string&name,
+PGBuiltin::PGBuiltin(Type t, perm_string name,
 		     svector<PExpr*>*pins,
 		     svector<PExpr*>*del)
 : PGate(name, pins, del), type_(t), msb_(0), lsb_(0)
 {
 }

-PGBuiltin::PGBuiltin(Type t, const string&name,
+PGBuiltin::PGBuiltin(Type t, perm_string name,
 		     svector<PExpr*>*pins,
 		     PExpr*del)
 : PGate(name, pins, del), type_(t), msb_(0), lsb_(0)
@@ -142,24 +199,23 @@ void PGBuiltin::set_range(PExpr*msb, PExpr*lsb)
      lsb_ = lsb;
 }

-PGModule::PGModule(const char*type, const string&name, svector<PExpr*>*pins)
+PGModule::PGModule(perm_string type, perm_string name, svector<PExpr*>*pins)
 : PGate(name, pins), overrides_(0), pins_(0),
  npins_(0), parms_(0), nparms_(0), msb_(0), lsb_(0)
 {
-      type_ = strdup(type);
+      type_ = type;
 }

-PGModule::PGModule(const char*type, const string&name,
+PGModule::PGModule(perm_string type, perm_string name,
 		   named<PExpr*>*pins, unsigned npins)
 : PGate(name, 0), overrides_(0), pins_(pins),
  npins_(npins), parms_(0), nparms_(0), msb_(0), lsb_(0)
 {
-      type_ = strdup(type);
+      type_ = type;
 }

 PGModule::~PGModule()
 {
-      free(type_);
 }

 void PGModule::set_parameters(svector<PExpr*>*o)
@@ -185,13 +241,25 @@ void PGModule::set_range(PExpr*msb, PExpr*lsb)
      lsb_ = lsb;
 }

-const char* PGModule::get_type()
+perm_string PGModule::get_type()
 {
      return type_;
 }

 /*
 * $Log: PGate.cc,v $
+ * Revision 1.18  2006/01/03 05:22:14  steve
+ *  Handle complex net node delays.
+ *
+ * Revision 1.17  2006/01/02 05:33:19  steve
+ *  Node delays can be more general expressions in structural contexts.
+ *
+ * Revision 1.16  2004/02/18 17:11:54  steve
+ *  Use perm_strings for named langiage items.
+ *
+ * Revision 1.15  2003/03/06 04:37:12  steve
+ *  lex_strings.add module names earlier.
+ *
 * Revision 1.14  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -1,7 +1,7 @@
 #ifndef __PGate_H
 #define __PGate_H
 /*
- * Copyright (c) 1998-2000 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2004 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,10 +19,11 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PGate.h,v 1.24 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PGate.h,v 1.32 2006/04/10 00:37:42 steve Exp $"
 #endif

 # include  "svector.h"
+# include  "StringHeap.h"
 # include  "named.h"
 # include  "LineInfo.h"
 # include  "PDelays.h"
@@ -49,27 +50,39 @@ class Module;
 * strength of the 1 drive.
 */
 class PGate : public LineInfo {
-      
+
    public:
      enum strength_t { HIGHZ, WEAK, PULL, STRONG, SUPPLY };

-      explicit PGate(const string&name, svector<PExpr*>*pins,
+      explicit PGate(perm_string name, svector<PExpr*>*pins,
 		     const svector<PExpr*>*del);

-      explicit PGate(const string&name, svector<PExpr*>*pins,
+      explicit PGate(perm_string name, svector<PExpr*>*pins,
 		     PExpr*del);

-      explicit PGate(const string&name, svector<PExpr*>*pins);
+      explicit PGate(perm_string name, svector<PExpr*>*pins);

      virtual ~PGate();

-      const string& get_name() const { return name_; }
+      perm_string get_name() const { return name_; }

+	// This method evaluates the delays all the way to an
+	// integer. If the delay is non-constant, then set the times
+	// to 0, print an error message and mark an error to the
+	// design.
      void eval_delays(Design*des, NetScope*scope,
 		       unsigned long&rise_time,
 		       unsigned long&fall_time,
 		       unsigned long&decay_time) const;

+	// This evaluates the delays as far as possible, but returns
+	// an expression, and do not signal errors.
+      void eval_delays(Design*des, NetScope*scope,
+		       NetExpr*&rise_time,
+		       NetExpr*&fall_time,
+		       NetExpr*&decay_time,
+		       bool as_net_flag =false) const;
+
      unsigned pin_count() const { return pins_? pins_->count() : 0; }
      const PExpr*pin(unsigned idx) const { return (*pins_)[idx]; }

@@ -79,21 +92,21 @@ class PGate : public LineInfo {
      void strength0(strength_t);
      void strength1(strength_t);

-      map<string,PExpr*> attributes;
+      map<perm_string,PExpr*> attributes;

-      virtual void dump(ostream&out) const;
+      virtual void dump(ostream&out, unsigned ind =4) const;
      virtual void elaborate(Design*des, NetScope*scope) const;
      virtual void elaborate_scope(Design*des, NetScope*sc) const;
      virtual bool elaborate_sig(Design*des, NetScope*scope) const;

    protected:
-      const svector<PExpr*>* get_pins() const { return pins_; }
+      const svector<PExpr*>& get_pins() const { return *pins_; }

      void dump_pins(ostream&out) const;
      void dump_delays(ostream&out) const;

    private:
-      const string name_;
+      perm_string name_;
      PDelays delay_;
      svector<PExpr*>*pins_;

@@ -115,7 +128,7 @@ class PGAssign  : public PGate {
      explicit PGAssign(svector<PExpr*>*pins, svector<PExpr*>*dels);
      ~PGAssign();

-      void dump(ostream&out) const;
+      void dump(ostream&out, unsigned ind =4) const;
      virtual void elaborate(Design*des, NetScope*scope) const;

    private:
@@ -141,10 +154,10 @@ class PGBuiltin  : public PGate {
 		  TRANIF1, RTRANIF0, RTRANIF1 };

    public:
-      explicit PGBuiltin(Type t, const string&name,
+      explicit PGBuiltin(Type t, perm_string name,
 			 svector<PExpr*>*pins,
 			 svector<PExpr*>*del);
-      explicit PGBuiltin(Type t, const string&name,
+      explicit PGBuiltin(Type t, perm_string name,
 			 svector<PExpr*>*pins,
 			 PExpr*del);
      ~PGBuiltin();
@@ -152,7 +165,7 @@ class PGBuiltin  : public PGate {
      Type type() const { return type_; }
      void set_range(PExpr*msb, PExpr*lsb);

-      virtual void dump(ostream&out) const;
+      virtual void dump(ostream&out, unsigned ind =4) const;
      virtual void elaborate(Design*, NetScope*scope) const;

    private:
@@ -171,14 +184,16 @@ class PGBuiltin  : public PGate {
 class PGModule  : public PGate {

    public:
+	// The name is the *instance* name of the gate.
+
 	// If the binding of ports is by position, this constructor
 	// builds everything all at once.
-      explicit PGModule(const char*type, const string&name,
+      explicit PGModule(perm_string type, perm_string name,
 			svector<PExpr*>*pins);

 	// If the binding of ports is by name, this constructor takes
 	// the bindings and stores them for later elaboration.
-      explicit PGModule(const char*type, const string&name,
+      explicit PGModule(perm_string type, perm_string name,
 			named<PExpr*>*pins, unsigned npins);


@@ -193,15 +208,17 @@ class PGModule  : public PGate {
 	// method to pass the range to the pform.
      void set_range(PExpr*msb, PExpr*lsb);

-      virtual void dump(ostream&out) const;
+      virtual void dump(ostream&out, unsigned ind =4) const;
      virtual void elaborate(Design*, NetScope*scope) const;
      virtual void elaborate_scope(Design*des, NetScope*sc) const;
      virtual bool elaborate_sig(Design*des, NetScope*scope) const;

-      const char* get_type();
+	// This returns the module name of this module. It is a
+	// permallocated string.
+      perm_string get_type();

    private:
-      char* type_;
+      perm_string type_;
      svector<PExpr*>*overrides_;
      named<PExpr*>*pins_;
      unsigned npins_;
@@ -222,6 +239,30 @@ class PGModule  : public PGate {

 /*
 * $Log: PGate.h,v $
+ * Revision 1.32  2006/04/10 00:37:42  steve
+ *  Add support for generate loops w/ wires and gates.
+ *
+ * Revision 1.31  2006/01/03 05:22:14  steve
+ *  Handle complex net node delays.
+ *
+ * Revision 1.30  2006/01/02 05:33:19  steve
+ *  Node delays can be more general expressions in structural contexts.
+ *
+ * Revision 1.29  2004/10/04 01:10:52  steve
+ *  Clean up spurious trailing white space.
+ *
+ * Revision 1.28  2004/03/08 00:47:44  steve
+ *  primitive ports can bind bi name.
+ *
+ * Revision 1.27  2004/02/20 18:53:33  steve
+ *  Addtrbute keys are perm_strings.
+ *
+ * Revision 1.26  2004/02/18 17:11:54  steve
+ *  Use perm_strings for named langiage items.
+ *
+ * Revision 1.25  2003/03/06 04:37:12  steve
+ *  lex_strings.add module names earlier.
+ *
 * Revision 1.24  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PGenerate.cc,v 1.1 2006/04/10 02:40:18 steve Exp $"
+#endif
+
+# include  "PGenerate.h"
+# include  "PWire.h"
+
+PGenerate::PGenerate(unsigned id)
+: id_number(id)
+{
+}
+
+PGenerate::~PGenerate()
+{
+}
+
+PWire* PGenerate::add_wire(PWire*wire)
+{
+      PWire*&ep = wires[wire->path()];
+      if (ep) return ep;
+
+      assert(ep == 0);
+      ep = wire;
+      return wire;
+}
+
+PWire* PGenerate::get_wire(const hname_t&name) const
+{
+      map<hname_t,PWire*>::const_iterator obj = wires.find(name);
+      if (obj == wires.end())
+	    return 0;
+      else
+	    return (*obj).second;
+}
+
+void PGenerate::add_gate(PGate*gate)
+{
+      gates.push_back(gate);
+}
@@ -0,0 +1,92 @@
+#ifndef __PGenerate_H
+#define __PGenerate_H
+/*
+ * Copyright (c) 2006 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PGenerate.h,v 1.1 2006/04/10 02:40:18 steve Exp $"
+#endif
+
+# include  "LineInfo.h"
+# include  "StringHeap.h"
+# include  "HName.h"
+# include  <list>
+# include  <map>
+
+class Design;
+class NetScope;
+class PExpr;
+class PGate;
+class PWire;
+
+/*
+ * This represents a generate scheme.
+ */
+class PGenerate : public LineInfo {
+
+    public:
+      PGenerate(unsigned id_number);
+      ~PGenerate();
+
+	// Generate schemes have an ID number, for when the scope is
+	// implicit.
+      const unsigned id_number;
+      perm_string scope_name;
+
+      enum scheme_t {GS_NONE, GS_LOOP, GS_CONDIT};
+      scheme_t scheme_type;
+
+	// generate loops have an index variable and three
+	// expressions: for (index = <init>; <test>; index=<step>)
+      perm_string loop_index;
+      PExpr*loop_init;
+      PExpr*loop_test;
+      PExpr*loop_step;
+
+      map<hname_t,PWire*>wires;
+      PWire* add_wire(PWire*);
+      PWire* get_wire(const hname_t&name) const;
+
+      list<PGate*> gates;
+      void add_gate(PGate*);
+
+	// This method is called by the elaboration of a module to
+	// generate scopes. the container is the scope that is to
+	// contain the generated scope.
+      bool generate_scope(Design*des, NetScope*container);
+
+      bool elaborate_sig(Design*des) const;
+      bool elaborate(Design*des) const;
+
+      void dump(ostream&out) const;
+
+    private:
+      bool generate_scope_loop_(Design*des, NetScope*container);
+
+	// These are the scopes created by generate_scope.
+      list<NetScope*>scope_list_;
+	// internal function called on each scope generated by this scheme.
+      bool elaborate_sig_(Design*des, NetScope*scope) const;
+      bool elaborate_(Design*des, NetScope*scope) const;
+
+    private: // not implemented
+      PGenerate(const PGenerate&);
+      PGenerate& operator= (const PGenerate&);
+};
+
+#endif
@@ -19,16 +19,32 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PTask.h,v 1.12 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PTask.h,v 1.13 2004/05/31 23:34:36 steve Exp $"
 #endif

 # include  "LineInfo.h"
 # include  "svector.h"
+# include  "StringHeap.h"
 # include  <string>
 class Design;
 class NetScope;
 class PWire;
 class Statement;
+class PExpr;
+
+enum PTaskFuncEnum {
+      PTF_NONE,
+      PTF_REG,
+      PTF_INTEGER,
+      PTF_REAL,
+      PTF_REALTIME,
+      PTF_TIME
+};
+
+struct PTaskFuncArg {
+      PTaskFuncEnum type;
+      svector<PExpr*>*range;
+};

 /*
 * The PTask holds the parsed definitions of a task.
@@ -69,16 +85,18 @@ class PTask  : public LineInfo {
 * The function is similar to a task (in this context) but there is a
 * single output port and a set of input ports. The output port is the
 * function return value.
+ *
+ * The output value is not elaborated until elaborate_sig.
 */
 class PFunction : public LineInfo {

    public:
-      explicit PFunction();
+      explicit PFunction(perm_string name);
      ~PFunction();

      void set_ports(svector<PWire *>*p);
      void set_statement(Statement *s);
-      void set_output(PWire*);
+      void set_return(PTaskFuncArg t);

      void elaborate_scope(Design*des, NetScope*scope) const;

@@ -91,13 +109,19 @@ class PFunction : public LineInfo {
      void dump(ostream&, unsigned) const;

    private:
-      PWire*out_;
+      perm_string name_;
+      PTaskFuncArg return_type_;
      svector<PWire *> *ports_;
      Statement *statement_;
 };

 /*
 * $Log: PTask.h,v $
+ * Revision 1.13  2004/05/31 23:34:36  steve
+ *  Rewire/generalize parsing an elaboration of
+ *  function return values to allow for better
+ *  speed and more type support.
+ *
 * Revision 1.12  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2003-2004 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PUdp.cc,v 1.3 2004/03/08 00:47:44 steve Exp $"
+#endif
+
+# include  "PUdp.h"
+
+PUdp::PUdp(perm_string n, unsigned nports)
+: ports(nports), sequential(false), initial(verinum::Vx), name_(n)
+{
+}
+
+unsigned PUdp::find_port(const char*name)
+{
+      for (unsigned idx = 0 ;  idx < ports.count() ;  idx += 1) {
+
+	    if (ports[idx] == name)
+		  return idx;
+      }
+
+      return ports.count();
+}
+
+/*
+ * $Log: PUdp.cc,v $
+ * Revision 1.3  2004/03/08 00:47:44  steve
+ *  primitive ports can bind bi name.
+ *
+ * Revision 1.2  2004/02/18 17:11:54  steve
+ *  Use perm_strings for named langiage items.
+ *
+ * Revision 1.1  2003/07/15 05:07:13  steve
+ *  Move PUdp constructor into compiled file.
+ *
+ */
+
@@ -1,7 +1,7 @@
 #ifndef __PUdp_H
 #define __PUdp_H
 /*
- * Copyright (c) 1998-2000 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2004 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,26 +19,21 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PUdp.h,v 1.7 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PUdp.h,v 1.12 2004/03/08 00:47:44 steve Exp $"
 #endif

 # include  <map>
+# include  "StringHeap.h"
 # include  "svector.h"
-# include  <string>
 # include  "verinum.h"

 class PExpr;

-svector<string>::svector<string>(unsigned size)
-: nitems_(size), items_(new string[size])
-{
-}
-
 /*
 * This class represents a parsed UDP. This is a much simpler object
 * then a module or macromodule.
 *
- *   - all ports are scaler,
+ *   - all ports are scalar,
 *   - pin 0 (the first port) is always output,
 *     and the remaining pins are input.
 *
@@ -53,15 +48,16 @@ svector<string>::svector<string>(unsigned size)
 * the current output.
 *
 * If the UDP is sequential, the "initial" member is taken to be the
- * intial value assigned in the source, or 'x' if none is given.
+ * initial value assigned in the source, or 'x' if none is given.
 */
 class PUdp {

    public:
-      explicit PUdp(const string&n, unsigned nports)
-      : ports(nports), sequential(false), initial(verinum::Vx), name_(n) { }
+      explicit PUdp(perm_string n, unsigned nports);

      svector<string>ports;
+      unsigned find_port(const char*name);
+
      bool sequential;

      svector<string>tinput;
@@ -74,7 +70,7 @@ class PUdp {

      void dump(ostream&out) const;

-      const string name_;
+      perm_string name_;
    private:

    private: // Not implemented
@@ -84,6 +80,21 @@ class PUdp {

 /*
 * $Log: PUdp.h,v $
+ * Revision 1.12  2004/03/08 00:47:44  steve
+ *  primitive ports can bind bi name.
+ *
+ * Revision 1.11  2004/02/18 17:11:54  steve
+ *  Use perm_strings for named langiage items.
+ *
+ * Revision 1.10  2003/07/15 05:07:13  steve
+ *  Move PUdp constructor into compiled file.
+ *
+ * Revision 1.9  2003/07/15 03:49:22  steve
+ *  Spelling fixes.
+ *
+ * Revision 1.8  2003/01/30 16:23:07  steve
+ *  Spelling fixes.
+ *
 * Revision 1.7  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2005 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,15 +17,19 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PWire.cc,v 1.10 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PWire.cc,v 1.11 2005/07/07 16:22:49 steve Exp $"
 #endif

 # include "config.h"
 # include  "PWire.h"
 # include  <assert.h>

-PWire::PWire(const hname_t&n, NetNet::Type t, NetNet::PortType pt)
-: hname_(n), type_(t), port_type_(pt), signed_(false), isint_(false),
+PWire::PWire(const hname_t&n,
+	     NetNet::Type t,
+	     NetNet::PortType pt,
+	     ivl_variable_type_t dt)
+: hname_(n), type_(t), port_type_(pt), data_type_(dt),
+  signed_(false), isint_(false),
 lidx_(0), ridx_(0)
 {
      if (t == NetNet::INTEGER) {
@@ -35,8 +39,12 @@ lidx_(0), ridx_(0)
      }
 }

-PWire::PWire(char*n, NetNet::Type t, NetNet::PortType pt)
-: hname_(n), type_(t), port_type_(pt), signed_(false), isint_(false),
+PWire::PWire(char*n,
+	     NetNet::Type t,
+	     NetNet::PortType pt,
+	     ivl_variable_type_t dt)
+: hname_(n), type_(t), port_type_(pt), data_type_(dt),
+  signed_(false), isint_(false),
 lidx_(0), ridx_(0)
 {
      if (t == NetNet::INTEGER) {
@@ -108,6 +116,19 @@ bool PWire::set_port_type(NetNet::PortType pt)
      }
 }

+bool PWire::set_data_type(ivl_variable_type_t dt)
+{
+      if (data_type_ != IVL_VT_NO_TYPE)
+	    if (data_type_ != dt)
+		  return false;
+	    else
+		  return true;
+
+      assert(data_type_ == IVL_VT_NO_TYPE);
+      data_type_ = dt;
+      return true;
+}
+
 void PWire::set_signed(bool flag)
 {
      signed_ = flag;
@@ -140,6 +161,9 @@ void PWire::set_memory_idx(PExpr*ldx, PExpr*rdx)

 /*
 * $Log: PWire.cc,v $
+ * Revision 1.11  2005/07/07 16:22:49  steve
+ *  Generalize signals to carry types.
+ *
 * Revision 1.10  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -19,7 +19,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: PWire.h,v 1.14 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: PWire.h,v 1.19 2006/04/10 00:37:42 steve Exp $"
 #endif

 # include  "netlist.h"
@@ -38,7 +38,7 @@ class Design;

 /*
 * Wires include nets, registers and ports. A net or register becomes
- * a port by declaration, so ports are not seperate. The module
+ * a port by declaration, so ports are not separate. The module
 * identifies a port by keeping it in its port list.
 *
 * The hname parameter to the constructor is a hierarchical name. It
@@ -49,11 +49,16 @@ class Design;
 class PWire : public LineInfo {

    public:
-      PWire(const hname_t&hname, NetNet::Type t, NetNet::PortType pt);
-      PWire(char*name, NetNet::Type t, NetNet::PortType pt);
+      PWire(const hname_t&hname,
+	    NetNet::Type t,
+	    NetNet::PortType pt,
+	    ivl_variable_type_t dt);
+      PWire(char*name,
+	    NetNet::Type t,
+	    NetNet::PortType pt,
+	    ivl_variable_type_t dt);

 	// Return a hierarchical name.
-	//const string name() const;
      const hname_t&path() const;

      NetNet::Type get_wire_type() const;
@@ -66,14 +71,17 @@ class PWire : public LineInfo {
      bool get_signed() const;
      bool get_isint() const;

+      bool set_data_type(ivl_variable_type_t dt);
+      ivl_variable_type_t get_data_type() const;
+
      void set_range(PExpr*msb, PExpr*lsb);

      void set_memory_idx(PExpr*ldx, PExpr*rdx);

-      map<string,PExpr*> attributes;
+      map<perm_string,PExpr*> attributes;

 	// Write myself to the specified stream.
-      void dump(ostream&out) const;
+      void dump(ostream&out, unsigned ind=4) const;

      void elaborate_sig(Design*, NetScope*scope) const;

@@ -81,6 +89,7 @@ class PWire : public LineInfo {
      hname_t hname_;
      NetNet::Type type_;
      NetNet::PortType port_type_;
+      ivl_variable_type_t data_type_;
      bool signed_;
      bool isint_;		// original type of integer

@@ -101,6 +110,22 @@ class PWire : public LineInfo {

 /*
 * $Log: PWire.h,v $
+ * Revision 1.19  2006/04/10 00:37:42  steve
+ *  Add support for generate loops w/ wires and gates.
+ *
+ * Revision 1.18  2005/07/07 16:22:49  steve
+ *  Generalize signals to carry types.
+ *
+ * Revision 1.17  2004/02/20 18:53:33  steve
+ *  Addtrbute keys are perm_strings.
+ *
+ * Revision 1.16  2003/01/30 16:23:07  steve
+ *  Spelling fixes.
+ *
+ * Revision 1.15  2003/01/26 21:15:58  steve
+ *  Rework expression parsing and elaboration to
+ *  accommodate real/realtime values and expressions.
+ *
 * Revision 1.14  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -16,8 +16,8 @@ execute even the most trivial design. For the purposes of simulation,
 we use as our example *the* most trivial simulation:

  module main;
- 
-  initial 
+
+  initial
    begin
      $display("Hello, World");
      $finish ;
@@ -79,5 +79,5 @@ Verilog packages from the main Debian software site.

 * Install From Source

-In this case, see the readme and other documentation that comes with
+In this case, see README.txt and other documentation that comes with
 the source.
@@ -1,5 +1,5 @@
-		THE ICARUS VERILOG COMPILATION SYSTEM 
-			   September 17, 2000	
+		THE ICARUS VERILOG COMPILATION SYSTEM
+		Copyright 2000-2004 Stephen Williams


 1.0 What is ICARUS Verilog?
@@ -9,11 +9,11 @@ described in the IEEE-1364 standard. Of course, it's not quite there
 yet. It does currently handle a mix of structural and behavioral
 constructs. For a view of the current state of Icarus Verilog, see its
 home page at <http://www.icarus.com/eda/verilog>.
- 
+
 Icarus Verilog is not aimed at being a simulator in the traditional
 sense, but a compiler that generates code employed by back-end
 tools. These back-end tools currently include a simulator engine
-called VVP, an XNF (Xilinx Netlist Format) generator and an EDIF fpga
+called VVP, an XNF (Xilinx Netlist Format) generator and an EDIF FPGA
 netlist generator. In the future, backends are expected for EDIF/LPM,
 structural Verilog, VHDL, etc.

@@ -59,6 +59,22 @@ on a UNIX-like system:
 	  A version problem with this program is the most common cause
 	  of difficulty. See the Icarus Verilog FAQ.

+	- readline 4.2
+	  On Linux systems, this usually means the readline-devel
+	  rpm. In any case, it is the development headers of readline
+	  that are needed.
+
+	- termcap
+	  The readline library in turn uses termcap.
+
+If you are building from CVS, you will also need software to generate
+the configure scripts.
+
+	- autoconf 2.53
+	  This generates configure scripts from configure.in. The 2.53
+	  or later versions are known to work, autoconf 2.13 is
+	  reported to *not* work.
+
 2.2 Compilation

 Unpack the tar-ball and cd into the verilog-######### directory
@@ -68,7 +84,7 @@ with the commands:
  ./configure
  make

-Normally, this command automatically figures out every thing it needs
+Normally, this command automatically figures out everything it needs
 to know. It generally works pretty well. There are a few flags to the
 configure script that modify its behavior:

@@ -86,6 +102,28 @@ configure script that modify its behavior:
 	    common to use --prefix=/opt.  You can configure for a non-root
 	    install with --prefix=$HOME.

+	--enable-vvp32 (experimental)
+	    If compiling on AMD64 systems, this enables the
+	    compilation of 32bit compatible vvp (vvp32) and the vpi
+	    modules that match.
+
+2.2.1 Special AMD64 Instructions
+
+(The Icarus Verilog RPM for x86_64 is build using these instructions.)
+
+If you are building for Linux/AMD64 (a.k.a x86_64) then to get the
+most out of your install, first make sure you have both 64bit and
+32bit development libraries installed. Then configure with this
+somewhat more complicated command:
+
+  ./configure libdir64='$(prefix)/lib64' vpidir1=vpi64 vpidir2=. --enable-vvp32
+
+This reflects the convention on AMD64 systems that 64bit libraries go
+into lib64 directories. The "--enable-vvp32" also turns on 32bit
+compatibility files. A 32bit version of vvp (vvp32) will be created,
+as well as 32bit versions of the development libraries and bundled VPI
+libraries.
+
 2.3 (Optional) Testing

 To run a simple test before installation, execute
@@ -130,14 +168,14 @@ only sees a single input file. See ivlpp/ivlpp.txt for details.
 3.2 Parse

 The Verilog compiler starts by parsing the Verilog source file. The
-output of the parse in a list of Module objects in PFORM. The pform
+output of the parse is a list of Module objects in "pform". The pform
 (see pform.h) is mostly a direct reflection of the compilation
 step. There may be dangling references, and it is not yet clear which
 module is the root.

-One can see a human readable version of the final PFORM by using the
+One can see a human readable version of the final pform by using the
 ``-P <path>'' flag to the compiler. This will cause iverilog to dump
-the PFORM into the file named <path>.
+the pform into the file named <path>.

 3.3 Elaboration

@@ -258,8 +296,8 @@ Example: Compiling "hello.vl"

 ------------------------ hello.vl ----------------------------
 module main();
- 
-initial 
+
+initial
  begin
    $display("Hi there");
    $finish ;
@@ -269,7 +307,7 @@ endmodule

 --------------------------------------------------------------

-Ensure that "iverilog" is on your search path, and the vpi library 
+Ensure that "iverilog" is on your search path, and the vpi library
 is available.

 To compile the program:
@@ -296,12 +334,8 @@ Verilog web page for the current state of support for Verilog, and in
 particular, browse the bug report database for reported unsupported
 constructs.

-  - real data types not supported. This includes real and
-    realtime. However, floating point constants in delay expressions
-    are supported so that `timescale works properly.
-
-  - System functions are supported, but the compiler presumes that
-    they return 32 bits. This is the typical case.
+  - System functions are supported, but the return value is a little
+    tricky. See SYSTEM FUNCTION TABLE FILES in the iverilog man page.

  - Specify blocks are parsed but ignored in general.

@@ -310,9 +344,6 @@ constructs.
  - tran primitives, i.e. tran, tranif1, tranif0, rtran, rtranif1
    and rtranif0 are not supported.

-  - Module instance arrays are not supported, although gate instance
-    arrays do work.
-
  - Net delays, of the form "wire #N foo;" do not work. Delays in
    every other context do work properly, including the V2001 form
    "wire #5 foo = bar;"
@@ -320,10 +351,6 @@ constructs.
  - Event controls inside non-blocking assignments are not supported.
    i.e.: a <= @(posedge clk) b;

-  - Lists of named events of the form @(event_1 or event_2) are not
-    supported. Named events are otherwise supported, and lists of
-    other kinds of events are also supported.
-
  - Macro arguments are not supported. `define macros are supported,
    but they cannot take arguments.

@@ -332,7 +359,13 @@ constructs.
 Icarus Verilog includes some features that are not part of the
 IEEE1364 standard, but have well defined meaning, and also sometimes
 gives nonstandard (but extended) meanings to some features of the
-language that are defined.
+language that are defined. See the "extensions.txt" documentation for
+more details.
+
+    $is_signed(<expr>)
+	This system function returns 1 if the expression contained is
+	signed, or 0 otherwise. This is mostly of use for compiler
+	regression tests.

    $sizeof(<expr>)
    $bits(<expr>)
@@ -344,13 +377,34 @@ language that are defined.
 	The $sizeof function is deprecated in favor of $bits, which is
 	the same thing, but included in the SystemVerilog definition.

+    $simtime
+	The $simtime system function returns as a 64bit value the
+	simulation time, unscaled by the time units of local
+	scope. This is different from the $time and $stime functions
+	which return the scaled times. This function is added for
+	regression testing of the compiler and run time, but can be
+	used by applications who really want the simulation time.
+
+	Note that the simulation time can be confusing if there are
+	lots of different `timescales within a design. It is not in
+	general possible to predict what the simulation precision will
+	turn out to be.
+
+    $mti_random()
+    $mti_dist_uniform
+	These functions are similar to the IEEE1364 standard $random
+	functions, but they use the Mersenne Twister (MT19937)
+	algorithm. This is considered an excellent random number
+	generator, but does not generate the same sequence as the
+	standardized $random.
+
    Builtin system functions

 	Certain of the system functions have well defined meanings, so
 	can theoretically be evaluated at compile time, instead of
 	using runtime VPI code. Doing so means that VPI cannot
 	override the definitions of functions handled in this
-	manner. On the other hand, this makes them synthesizeable, and
+	manner. On the other hand, this makes them synthesizable, and
 	also allows for more aggressive constant propagation. The
 	functions handled in this manner are:

@@ -390,91 +444,53 @@ language that are defined.
 	completely specify the format.

 	Icarus Verilog allows the programmer to specify the field
-	with. The "%t" format in Icarus Verilog works exactly as it
+	width. The "%t" format in Icarus Verilog works exactly as it
 	does in standard Verilog. However, if the programmer chooses
 	to specify a minimum width (i.e., "%5t"), then for that display
 	Icarus Verilog will override the $timeformat minimum width and
 	use the explicit minimum width.

+    vpiScope iterator on vpiScope objects.
+
+	In the VPI, the normal way to iterate over vpiScope objects
+	contained within a vpiScope object, is the vpiInternalScope
+	iterator. Icarus Verilog adds support for the vpiScope
+	iterator of a vpiScope object, that iterates over *everything*
+	the is contained in the current scope. This is useful in cases
+	where one wants to iterate over all the objects in a scope
+	without iterating over all the contained types explicitly.
+
+    time 0 race resolution.
+
+	Combinational logic is routinely modeled using always
+	blocks. However, this can lead to race conditions if the
+	inputs to the combinational block are initialized in initial
+	statements. Icarus Verilog slightly modifies time 0 scheduling
+	by arranging for always statements with ANYEDGE sensitivity
+	lists to be scheduled before any other threads. This causes
+	combinational always blocks to be triggered when the values in
+	the sensitivity list are initialized by initial threads.
+
+    Nets with Types
+
+	Icarus Verilog support an extension syntax that allows nets
+	and regs to be explicitly typed. The currently supported types
+	are logic, bool and real. This implies that "logic" and "bool"
+	are new keywords. Typical syntax is:
+
+	wire real foo = 1.0;
+	reg logic bar, bat;
+
+	... and so forth. The syntax can be turned off by using the
+	-g2 flag to iverilog, and turned on explicitly with the -g2x
+	flag to iverilog.
+
 6.0 CREDITS

 Except where otherwise noted, Icarus Verilog, ivl and ivlpp are
 Copyright Stephen Williams. The proper notices are in the head of each
 file. However, I have early on received aid in the form of fixes,
-Verilog guidance, and especially testing from many people, including
-(in alphabetical order):
-
-	Eric Aardoom <[email protected]>
-	Stephan I. Boettcher <[email protected]>
-	Ed Carter <[email protected]>
-	Larry Doolittle <[email protected]>
-	Guy Hutchison <[email protected]>
-	Ales Hvezda <[email protected]>
-	Venkat Iyer <[email protected]>
-	Yasuhisa Kato <[email protected]>
-        James Lee <[email protected]>
-	Peter Monta <[email protected]>
-	Daniel H. Nelsen <[email protected]>
-	Stefan Petersen <[email protected]>
-	Michael Ruff <[email protected]>
-	Mike Runyan <[email protected]>
-	Jason Schonberg <[email protected]>
-	Stuart Sutherland <[email protected]>
-	Stephen Tell <[email protected]>
-        Stefan Theide <[email protected]>
-	Tom Verbeure
-	Steve Wilson <[email protected]>
-
-and others. Testers in particular include a larger community of people
-interested in a GPL Verilog for Linux. Special thanks to Steve Wilson
-for collecting and organizing the test suite code for all those testers.
-
-
-6.1 PORT MAINTAINERS
-
-This is a list of people who have created ports and precompiled
-packages for various operating systems. These folks have graciously
-taken on the task of building Icarus Verilog on their systems and
-bundled it into neat packages.(+) If you want to be added to the list (or
-removed from the list) send e-mail to me.
-
-      FreeBSD/{Intel,alpha}
-	Ying-Chieh Liao <[email protected]>
-
-      Linux/{alpha,Intel} (RPMS)
-	Stephen Williams <[email protected]>
-
-      Linux/* (.debs)
-	Hamish Moffatt <[email protected]>
-
-      Macintosh -- MacO/S
-	Yasuhisa Kato <[email protected]>
-
-      Mac O/S X
-        Timothy J. Wood <[email protected]>
-
-      NetBSD/*
-	Dan McMahill <[email protected]>
-
-      Solaris/SPARC packages (.pkg)
-	Dan McMahill <[email protected]>
-
-      Cygwin32/*
-        Venkat Iyer <[email protected]>
-
-      Mingw32
-        Venkat Iyer <[email protected]>
-
-(+) These are not the only systems where Icarus Verilog has been run,
-just the systems where precompiled binaries are publicly available.
-
-
-6.2 TEST SUITE MANAGER
-
-Steve Wilson <[email protected]> has taken on the large task of managing
-the test suite. He has maintained the regression test scripts, the
-driver list, received submissions from myself and others, and has
-written a great many tests on his own. Any compiler writer, for any
-language, will tell you that the test suite is at least as important
-as the compiler code itself.
+Verilog guidance, and especially testing from many people. Testers in
+particular include a larger community of people interested in a GPL
+Verilog for Linux.

@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: Statement.cc,v 1.28 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: Statement.cc,v 1.29 2004/02/18 17:11:54 steve Exp $"
 #endif

 # include "config.h"
@@ -86,7 +86,7 @@ PAssignNB::~PAssignNB()
 {
 }

-PBlock::PBlock(const string&n, BL_TYPE t, const svector<Statement*>&st)
+PBlock::PBlock(perm_string n, BL_TYPE t, const svector<Statement*>&st)
 : name_(n), bl_type_(t), list_(st)
 {
 }
@@ -295,6 +295,9 @@ PWhile::~PWhile()

 /*
 * $Log: Statement.cc,v $
+ * Revision 1.29  2004/02/18 17:11:54  steve
+ *  Use perm_strings for named langiage items.
+ *
 * Revision 1.28  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -19,11 +19,12 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: Statement.h,v 1.36 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: Statement.h,v 1.42 2005/12/05 21:21:18 steve Exp $"
 #endif

 # include  <string>
 # include  "svector.h"
+# include  "StringHeap.h"
 # include  "PDelays.h"
 # include  "PExpr.h"
 # include  "HName.h"
@@ -35,6 +36,7 @@ class Design;
 class NetAssign_;
 class NetCAssign;
 class NetDeassign;
+class NetForce;
 class NetScope;

 /*
@@ -56,7 +58,7 @@ class PProcess : public LineInfo {
      Type type() const { return type_; }
      Statement*statement() { return statement_; }

-      map<string,PExpr*> attributes;
+      map<perm_string,PExpr*> attributes;

      virtual void dump(ostream&out, unsigned ind) const;

@@ -148,7 +150,7 @@ class PBlock  : public Statement {
    public:
      enum BL_TYPE { BL_SEQ, BL_PAR };

-      explicit PBlock(const string&n, BL_TYPE t, const svector<Statement*>&st);
+      explicit PBlock(perm_string n, BL_TYPE t, const svector<Statement*>&st);
      explicit PBlock(BL_TYPE t, const svector<Statement*>&st);
      explicit PBlock(BL_TYPE t);
      ~PBlock();
@@ -161,7 +163,7 @@ class PBlock  : public Statement {
      virtual void elaborate_scope(Design*des, NetScope*scope) const;

    private:
-      string name_;
+      perm_string name_;
      const BL_TYPE bl_type_;
      svector<Statement*>list_;
 };
@@ -287,7 +289,7 @@ class PDelayStatement  : public Statement {


 /*
- * This represends the parsing of a disable <scope> statement.
+ * This represents the parsing of a disable <scope> statement.
 */
 class PDisable  : public Statement {

@@ -331,6 +333,8 @@ class PEventStatement  : public Statement {
 	// elaborated statement to the event.
      NetProc* elaborate_st(Design*des, NetScope*scope, NetProc*st) const;

+      NetProc* elaborate_wait(Design*des, NetScope*scope, NetProc*st) const;
+
    private:
      svector<PEEvent*>expr_;
      Statement*statement_;
@@ -342,7 +346,7 @@ class PForce  : public Statement {
      explicit PForce(PExpr*l, PExpr*r);
      ~PForce();

-      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
+      virtual NetForce* elaborate(Design*des, NetScope*scope) const;
      virtual void dump(ostream&out, unsigned ind) const;

    private:
@@ -390,6 +394,7 @@ class PNoop  : public Statement {

    public:
      PNoop() { }
+      ~PNoop() { }
 };

 class PRepeat : public Statement {
@@ -453,6 +458,26 @@ class PWhile  : public Statement {

 /*
 * $Log: Statement.h,v $
+ * Revision 1.42  2005/12/05 21:21:18  steve
+ *  Fixes for stubborn compilers.
+ *
+ * Revision 1.41  2004/12/11 02:31:25  steve
+ *  Rework of internals to carry vectors through nexus instead
+ *  of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ *  down this path.
+ *
+ * Revision 1.40  2004/02/20 18:53:33  steve
+ *  Addtrbute keys are perm_strings.
+ *
+ * Revision 1.39  2004/02/18 17:11:54  steve
+ *  Use perm_strings for named langiage items.
+ *
+ * Revision 1.38  2003/05/19 02:50:58  steve
+ *  Implement the wait statement behaviorally instead of as nets.
+ *
+ * Revision 1.37  2003/01/30 16:23:07  steve
+ *  Spelling fixes.
+ *
 * Revision 1.36  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2002 Stephen Williams ([email protected])
+ * Copyright (c) 2002-2004 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -15,15 +15,9 @@
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- *  ---
- *    You should also have recieved a copy of the Picture Elements
- *    Binary Software License offer along with the source. This offer
- *    allows you to obtain the right to redistribute the software in
- *    binary (compiled) form. If you have not received it, contact
- *    Picture Elements, Inc., 777 Panoramic Way, Berkeley, CA 94704.
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: StringHeap.cc,v 1.2 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: StringHeap.cc,v 1.6 2004/02/18 17:11:54 steve Exp $"
 #endif

 # include  "StringHeap.h"
@@ -38,11 +32,12 @@ StringHeap::StringHeap()
 {
      cell_base_ = 0;
      cell_ptr_ = HEAPCELL;
+      cell_count_ = 0;
 }

 StringHeap::~StringHeap()
 {
-	// This is a planned memory leak. The string heap is indended
+	// This is a planned memory leak. The string heap is intended
 	// to hold permanently-allocated strings.
 }

@@ -55,6 +50,8 @@ const char* StringHeap::add(const char*text)
      if (rem < (len+1)) {
 	    cell_base_ = (char*)malloc(HEAPCELL);
 	    cell_ptr_ = 0;
+	    cell_count_ += 1;
+	    assert(cell_base_ != 0);
      }

      char*res = cell_base_ + cell_ptr_;
@@ -62,11 +59,143 @@ const char* StringHeap::add(const char*text)
      cell_ptr_ += len;
      cell_base_[cell_ptr_++] = 0;

+      assert(cell_ptr_ <= HEAPCELL);
+
      return res;
 }

+perm_string StringHeap::make(const char*text)
+{
+      return perm_string(add(text));
+}
+
+
+StringHeapLex::StringHeapLex()
+{
+      hit_count_ = 0;
+      add_count_ = 0;
+
+      for (unsigned idx = 0 ;  idx < HASH_SIZE ;  idx += 1)
+	    hash_table_[idx] = 0;
+}
+
+StringHeapLex::~StringHeapLex()
+{
+}
+
+unsigned StringHeapLex::add_hit_count() const
+{
+      return hit_count_;
+}
+
+unsigned StringHeapLex::add_count() const
+{
+      return add_count_;
+}
+
+static unsigned hash_string(const char*text)
+{
+      unsigned h = 0;
+
+      while (*text) {
+	    h = (h << 4) ^ (h >> 28) ^ *text;
+	    text += 1;
+      }
+      return h;
+}
+
+const char* StringHeapLex::add(const char*text)
+{
+      unsigned hash_value = hash_string(text) % HASH_SIZE;
+
+	/* If we easily find the string in the hash table, then return
+	   that and be done. */
+      if (hash_table_[hash_value]
+	  && (strcmp(hash_table_[hash_value], text) == 0)) {
+	    hit_count_ += 1;
+	    return hash_table_[hash_value];
+      }
+
+	/* The existing hash entry is not a match. Replace it with the
+	   newly allocated value, and return the new pointer as the
+	   result to the add. */
+      const char*res = StringHeap::add(text);
+      hash_table_[hash_value] = res;
+      add_count_ += 1;
+
+      return res;
+}
+
+perm_string StringHeapLex::make(const char*text)
+{
+      return perm_string(add(text));
+}
+
+perm_string StringHeapLex::make(const string&text)
+{
+      return perm_string(add(text.c_str()));
+}
+
+bool operator == (perm_string a, const char*b)
+{
+      if (a.str() == b)
+	    return true;
+
+      if (! (a.str() && b))
+	    return false;
+
+      if (strcmp(a.str(), b) == 0)
+	    return true;
+
+      return false;
+}
+
+bool operator == (perm_string a, perm_string b)
+{
+      return a == b.str();
+}
+
+bool operator != (perm_string a, const char*b)
+{
+      return ! (a == b);
+}
+
+bool operator != (perm_string a, perm_string b)
+{
+      return ! (a == b);
+}
+
+bool operator < (perm_string a, perm_string b)
+{
+      if (b.str() && !a.str())
+	    return true;
+
+      if (b.str() == a.str())
+	    return false;
+
+      if (strcmp(a.str(), b.str()) < 0)
+	    return true;
+
+      return false;
+}
+
 /*
 * $Log: StringHeap.cc,v $
+ * Revision 1.6  2004/02/18 17:11:54  steve
+ *  Use perm_strings for named langiage items.
+ *
+ * Revision 1.5  2003/03/01 06:25:30  steve
+ *  Add the lex_strings string handler, and put
+ *  scope names and system task/function names
+ *  into this table. Also, permallocate event
+ *  names from the beginning.
+ *
+ * Revision 1.4  2003/01/27 05:09:17  steve
+ *  Spelling fixes.
+ *
+ * Revision 1.3  2003/01/16 21:44:46  steve
+ *  Keep some debugging status.
+ *
 * Revision 1.2  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -1,7 +1,7 @@
 #ifndef __StringHeap_H
 #define __StringHeap_H
 /*
- * Copyright (c) 2002 Stephen Williams ([email protected])
+ * Copyright (c) 2002-2004 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,9 +19,55 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: StringHeap.h,v 1.2 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: StringHeap.h,v 1.6 2005/06/14 19:13:43 steve Exp $"
 #endif

+# include  "config.h"
+# include  <string>
+
+using namespace std;
+
+class perm_string {
+
+    public:
+      perm_string() : text_(0) { }
+      perm_string(const perm_string&that) : text_(that.text_) { }
+      ~perm_string() { }
+
+      perm_string& operator = (const perm_string&that)
+      { text_ = that.text_; return *this; }
+
+      const char*str() const { return text_; }
+      operator const char* () const { return str(); }
+
+	// This is an escape for making perm_string objects out of
+	// literals. For example, per_string::literal("Label"); Please
+	// do *not* cheat and pass arbitrary const char* items here.
+      static perm_string literal(const char*t) { return perm_string(t); }
+
+    private:
+      friend class StringHeap;
+      friend class StringHeapLex;
+      perm_string(const char*t) : text_(t) { };
+
+    private:
+      const char*text_;
+};
+
+extern bool operator == (perm_string a, perm_string b);
+extern bool operator == (perm_string a, const char* b);
+extern bool operator != (perm_string a, perm_string b);
+extern bool operator != (perm_string a, const char* b);
+extern bool operator >  (perm_string a, perm_string b);
+extern bool operator <  (perm_string a, perm_string b);
+extern bool operator >= (perm_string a, perm_string b);
+extern bool operator <= (perm_string a, perm_string b);
+
+/*
+ * The string heap is a way to permanently allocate strings
+ * efficiently. They only take up the space of the string characters
+ * and the terminating nul, there is no malloc overhead.
+ */
 class StringHeap {

    public:
@@ -29,20 +75,68 @@ class StringHeap {
      ~StringHeap();

      const char*add(const char*);
+      perm_string make(const char*);

    private:
      enum { HEAPCELL = 0x10000 };

      char*cell_base_;
      unsigned cell_ptr_;
+      unsigned cell_count_;

    private: // not implemented
      StringHeap(const StringHeap&);
      StringHeap& operator= (const StringHeap&);
 };

+/*
+ * A lexical string heap is a string heap that makes an effort to
+ * return the same pointer for identical strings. This saves further
+ * space by not allocating duplicate strings, so in a system with lots
+ * of identifiers, this can theoretically save more space.
+ */
+class StringHeapLex  : private StringHeap {
+
+    public:
+      StringHeapLex();
+      ~StringHeapLex();
+
+      const char*add(const char*);
+      perm_string make(const char*);
+      perm_string make(const string&);
+
+      unsigned add_count() const;
+      unsigned add_hit_count() const;
+
+    private:
+      enum { HASH_SIZE = 4096 };
+      const char*hash_table_[HASH_SIZE];
+
+      unsigned add_count_;
+      unsigned hit_count_;
+
+    private: // not implemented
+      StringHeapLex(const StringHeapLex&);
+      StringHeapLex& operator= (const StringHeapLex&);
+};
+
 /*
 * $Log: StringHeap.h,v $
+ * Revision 1.6  2005/06/14 19:13:43  steve
+ *  gcc3/4 compile errors.
+ *
+ * Revision 1.5  2004/02/18 17:11:54  steve
+ *  Use perm_strings for named langiage items.
+ *
+ * Revision 1.4  2003/03/01 06:25:30  steve
+ *  Add the lex_strings string handler, and put
+ *  scope names and system task/function names
+ *  into this table. Also, permallocate event
+ *  names from the beginning.
+ *
+ * Revision 1.3  2003/01/16 21:44:46  steve
+ *  Keep some debugging status.
+ *
 * Revision 1.2  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -0,0 +1,126 @@
+#ifndef PLI_TYPES
+#define PLI_TYPES
+/*
+ * Copyright (c) 2003 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: _pli_types.h.in,v 1.7 2003/11/12 02:38:44 steve Exp $"
+#endif
+
+# undef HAVE_INTTYPES_H
+
+#ifdef HAVE_INTTYPES_H
+
+/*
+ * If the host environment has the stdint.h header file,
+ * then use that to size our PLI types.
+ */
+#ifndef __STDC_FORMAT_MACROS
+# define __STDC_FORMAT_MACROS
+#endif
+
+# include  <inttypes.h>
+typedef uint64_t PLI_UINT64;
+typedef int64_t  PLI_INT64;
+typedef uint32_t PLI_UINT32;
+typedef int32_t  PLI_INT32;
+
+typedef signed short   PLI_INT16;
+typedef unsigned short PLI_UINT16;
+typedef signed char    PLI_BYTE8;
+typedef unsigned char  PLI_UBYTE8;
+
+# define PLI_UINT64_FMT PRIu64
+
+#else
+
+/*
+ * If we do not have the c99 stdint.h header file, then use
+ * configure detection to guess the pli types ourselves.
+ */
+
+# define SIZEOF_UNSIGNED_LONG_LONG 8
+# define SIZEOF_UNSIGNED_LONG 8
+# define SIZEOF_UNSIGNED 4
+
+#if SIZEOF_UNSIGNED >= 8
+typedef unsigned PLI_UINT64;
+typedef int      PLI_INT64;
+# define PLI_UINT64_FMT "u"
+#else
+# if SIZEOF_UNSIGNED_LONG >= 8
+typedef unsigned long PLI_UINT64;
+typedef          long PLI_INT64;
+#  define PLI_UINT64_FMT "lu"
+# else
+#  if SIZEOF_UNSIGNED_LONG_LONG > SIZEOF_UNSIGNED_LONG
+typedef unsigned long long PLI_UINT64;
+typedef          long long PLI_INT64;
+#   define PLI_UINT64_FMT "llu"
+#  else
+typedef unsigned long PLI_UINT64;
+typedef          long PLI_INT64;
+#   define PLI_UINT64_FMT "lu"
+#  endif
+# endif
+#endif
+
+typedef signed int     PLI_INT32;
+typedef unsigned int   PLI_UINT32;
+typedef signed short   PLI_INT16;
+typedef unsigned short PLI_UINT16;
+typedef signed char    PLI_BYTE8;
+typedef unsigned char  PLI_UBYTE8;
+#endif
+
+/*
+ * $Log: _pli_types.h.in,v $
+ * Revision 1.7  2003/11/12 02:38:44  steve
+ *  Clean up manual definitions of PLI_UINT64_FMT.
+ *
+ * Revision 1.6  2003/11/08 20:06:21  steve
+ *  Spelling fixes in comments.
+ *
+ * Revision 1.5  2003/10/29 03:28:27  steve
+ *  Add the PLU_UINT64_FMT string for formatting output.
+ *
+ * Revision 1.4  2003/10/29 03:23:12  steve
+ *  Portably handle time format of VCD prints.
+ *
+ * Revision 1.3  2003/10/02 21:30:06  steve
+ *  Use configured TIME_FMT in vcd dump printf.
+ *
+ * Revision 1.2  2003/10/02 19:33:44  steve
+ *  Put libraries in libdir64.
+ *
+ * Revision 1.1  2003/09/30 01:33:13  steve
+ *  Add PLI_UINT64 to _pli_types.h.
+ *
+ * Revision 1.2  2003/05/26 04:39:16  steve
+ *  Typo type name.
+ *
+ * Revision 1.1  2003/02/17 06:39:47  steve
+ *  Add at least minimal implementations for several
+ *  acc_ functions. Add support for standard ACC
+ *  string handling.
+ *
+ *  Add the _pli_types.h header file to carry the
+ *  IEEE1364-2001 standard PLI type declarations.
+ *
+ */
+#endif
@@ -19,7 +19,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: acc_user.h,v 1.6 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: acc_user.h,v 1.20 2003/12/17 15:45:07 steve Exp $"
 #endif

 /*
@@ -31,6 +31,7 @@
 * implemented using VPI routines.
 */

+
 #ifdef __cplusplus
 # define EXTERN_C_START extern "C" {
 # define EXTERN_C_END }
@@ -42,16 +43,36 @@

 EXTERN_C_START

+# include  "_pli_types.h"
+
 /*
 * This is a declaration of the "handle" type that is compatible with
- * the vpiHandle from vpi_user.h.
+ * the vpiHandle from vpi_user.h. The libveriuser library implements
+ * the acc handle type as a vpiHandle, to prevent useless indirection.
 */
 typedef struct __vpiHandle *handle;

 /* OBJECT TYPES */
-#define accScope   21
-#define accScalar  300
-#define accVector  302
+#define accModule    20
+#define accScope     21
+#define accNet       25
+#define accReg       30
+#define accIntegerParam   200
+#define accRealParam 202
+#define accStringParam 204
+#define accParameter   220
+#define accTopModule      224
+#define accModuleInstance 226
+#define accWire        260
+#define accNamedEvent  280
+#define accIntegerVar  281
+#define accRealVar   282
+#define accTimeVar   283
+#define accIntVar    accIntegerVar
+#define accScalar    300
+#define accVector    302
+#define accUnknown   412
+#define accConstant  600

 /* type VALUES FOR t_setval_delay STRUCTURE */
 #define accNoDelay  0
@@ -72,11 +93,44 @@ typedef struct __vpiHandle *handle;
 #define accStringVal 8
 #define accVectorVal 9

+/* Scalar values */
+#define acc0 0
+#define acc1 1
+#define accX 2
+#define accZ 3
+
 /* type VALUES FOR t_acc_time STRUCTURE */
 #define accTime 1
 #define accSimTime 2
 #define accRealTime 3

+/* reason codes */
+#define logic_value_change     1
+#define strength_value_change  2
+#define real_value_change      3
+#define vector_value_change    4
+#define event_value_change     5
+#define integer_value_change   6
+#define time_value_change      7
+#define sregister_value_change 8
+#define vregister_value_change 9
+#define realtime_value_change 10
+
+/* VCL strength values */
+#define vclSupply  7
+#define vclStrong  6
+#define vclPull    5
+#define vclLarge   4
+#define vclWeak    3
+#define vclMedium  2
+#define vclSmall   1
+#define vclHighZ   0
+
+/* Constants used by acc_vcl_add */
+#define vcl_verilog_logic 2
+#define VCL_VERILOG_LOGIC vcl_verilog_logic
+#define vcl_verilog_strength 3
+#define VCL_VERILOG_STRENGTH vcl_verilog_strength

 typedef struct t_acc_time {
      int type;
@@ -105,37 +159,178 @@ typedef struct t_setval_value {
      } value;
 } s_setval_value, *p_setval_value, s_acc_value, *p_acc_value;

+typedef struct t_strengths {
+      PLI_UBYTE8 logic_value;
+      PLI_UBYTE8 strength1;
+      PLI_UBYTE8 strength2;
+} s_strengths, *p_strengths;
+
+typedef struct t_vc_record {
+      PLI_INT32 vc_reason;
+      PLI_INT32 vc_hightime;
+      PLI_INT32 vc_lowtime;
+      void*     user_data;
+      union {
+	    PLI_UBYTE8 logic_value;
+	    double real_value;
+	    handle vector_handle;
+	    s_strengths strengths_s;
+      } out_value;
+} s_vc_record, *p_vc_record;
+
+
+typedef struct t_location {
+      PLI_INT32 line_no;
+      const char*filename;
+} s_location, *p_location;
+
 extern int acc_error_flag;

 extern int acc_initialize(void);

 extern void acc_close(void);

+/*
+ * This is the acc_configure command, and the config_param
+ * codes that are accepted.
+ */
+extern int   acc_configure(PLI_INT32 config_param, const char*value);
+#define accEnableArgs          6
+#define accDevelopmentVersion 11
+
 extern int   acc_fetch_argc(void);
 extern char**acc_fetch_argv(void);

+extern PLI_INT32 acc_fetch_direction(handle obj);
+/* XXXX FIXME: Values returned by acc_fetch_direction */
+# define accInout 2
+
 extern char* acc_fetch_fullname(handle obj);

-extern int   acc_fetch_tfarg_int(int n);
-extern char* acc_fetch_tfarg_str(int n);
+extern int   acc_fetch_location(p_location loc, handle obj);
+
+extern char* acc_fetch_name(handle obj);
+extern char* acc_fetch_defname(handle obj);
+
+extern double acc_fetch_paramval(handle obj);
+
+extern double    acc_fetch_tfarg(PLI_INT32);
+extern double    acc_fetch_itfarg(PLI_INT32, handle);
+extern PLI_INT32 acc_fetch_tfarg_int(PLI_INT32);
+extern PLI_INT32 acc_fetch_itfarg_int(PLI_INT32, handle);
+extern char*     acc_fetch_tfarg_str(PLI_INT32);
+extern char*     acc_fetch_itfarg_str(PLI_INT32, handle);
+
+typedef struct t_timescale_info {
+      PLI_INT16 unit;
+      PLI_INT16 precision;
+} s_timescale_info, *p_timescale_info;
+extern void acc_fetch_timescale_info(handle obj, p_timescale_info info);
+
+extern PLI_INT32 acc_fetch_size(handle obj);
+
+extern PLI_INT32 acc_fetch_type(handle obj);
+extern PLI_INT32 acc_fetch_fulltype(handle obj);
+extern PLI_INT32 acc_fetch_range(handle object, int *msb, int *lsb);
+extern char*     acc_fetch_type_str(PLI_INT32 type);
+
+extern char* acc_fetch_value(handle obj, const char*fmt, s_acc_value*value);
+
+extern handle acc_handle_by_name(const char*name, handle scope);
+extern handle acc_handle_hiconn(handle port_ref_handle);
+extern handle acc_handle_object(const char*name);
+extern handle acc_handle_parent(handle obj);
+extern handle acc_handle_scope(handle obj);
+extern handle acc_handle_simulated_net(handle net);

 extern handle acc_handle_tfarg(int n);
+extern handle acc_handle_tfinst(void);

+extern PLI_INT32 acc_compare_handles(handle, handle);
+
+extern handle acc_next(PLI_INT32 *, handle, handle);
+extern handle acc_next_bit(handle ref, handle bit);
+extern handle acc_next_port(handle ref, handle bit);
+extern handle acc_next_scope(handle, handle);
 extern handle acc_next_topmod(handle prev_topmod);

-extern int acc_object_of_type(handle object, int type);
+extern int acc_object_in_typelist(handle object, PLI_INT32*typelist);
+extern int acc_object_of_type(handle object, PLI_INT32 type);

 extern char*acc_product_version(void);

+extern char*acc_set_scope(handle ref, ...);
+
 extern int acc_set_value(handle obj, p_setval_value value,
 			 p_setval_delay delay);

+extern void acc_vcl_add(handle obj, PLI_INT32(*consumer)(p_vc_record),
+			void*data, PLI_INT32 vcl_flag);
+extern  void acc_vcl_delete(handle obj, PLI_INT32(*consumer)(p_vc_record),
+			    void*data, PLI_INT32 vcl_flag);
+
 extern char* acc_version(void);

 EXTERN_C_END

 /*
 * $Log: acc_user.h,v $
+ * Revision 1.20  2003/12/17 15:45:07  steve
+ *  Add acc_set_scope function.
+ *
+ * Revision 1.19  2003/10/10 02:57:45  steve
+ *  Some PLI1 stubs.
+ *
+ * Revision 1.18  2003/06/13 19:23:41  steve
+ *  Add a bunch more PLI1 routines.
+ *
+ * Revision 1.17  2003/06/04 01:56:20  steve
+ * 1) Adds configure logic to clean up compiler warnings
+ * 2) adds acc_compare_handle, acc_fetch_range, acc_next_scope and
+ *    tf_isetrealdelay, acc_handle_scope
+ * 3) makes acc_next reentrant
+ * 4) adds basic vpiWire type support
+ * 5) fills in some acc_object_of_type() and acc_fetch_{full}type()
+ * 6) add vpiLeftRange/RigthRange to signals
+ *
+ * Revision 1.16  2003/05/30 04:18:31  steve
+ *  Add acc_next function.
+ *
+ * Revision 1.15  2003/05/29 02:35:41  steve
+ *  acc_fetch_type supports module.
+ *
+ * Revision 1.14  2003/05/29 02:21:45  steve
+ *  Implement acc_fetch_defname and its infrastructure in vvp.
+ *
+ * Revision 1.13  2003/05/24 03:02:04  steve
+ *  Add implementation of acc_handle_by_name.
+ *
+ * Revision 1.12  2003/05/18 00:16:35  steve
+ *  Add PLI_TRACE tracing of PLI1 modules.
+ *
+ *  Add tf_isetdelay and friends, and add
+ *  callback return values for acc_vcl support.
+ *
+ * Revision 1.11  2003/04/24 18:57:05  steve
+ *  Add acc_fetch_fulltype function.
+ *
+ * Revision 1.10  2003/04/20 02:48:39  steve
+ *  Support value change callbacks.
+ *
+ * Revision 1.9  2003/04/12 18:57:13  steve
+ *  More acc_ function stubs.
+ *
+ * Revision 1.8  2003/03/13 04:35:09  steve
+ *  Add a bunch of new acc_ and tf_ functions.
+ *
+ * Revision 1.7  2003/02/17 06:39:47  steve
+ *  Add at least minimal implementations for several
+ *  acc_ functions. Add support for standard ACC
+ *  string handling.
+ *
+ *  Add the _pli_types.h header file to carry the
+ *  IEEE1364-2001 standard PLI type declarations.
+ *
 * Revision 1.6  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -0,0 +1,207 @@
+# AX_CPP_IDENT
+# ------------
+# Check if the C compiler supports #ident
+# Define and substitute ident_support if so.
+#
+# It would be simpler and more consistent with the rest of the autoconf
+# structure to AC_DEFINE(HAVE_CPP_IDENT) instead of
+# ident_support='-DHAVE_CVS_IDENT=1' and AC_SUBST(ident_support), but that
+# change would require all C files in the icarus top level directory to
+# put #include <config.h> before the #ifdef HAVE_CVS_IDENT (and change
+# HAVE_CVS_IDENT to HAVE_CPP_IDENT).   That would also remove all special
+# ident_support handling from the Makefile.  Manyana.
+#
+AC_DEFUN([AX_CPP_IDENT],
+[AC_CACHE_CHECK([for ident support in C compiler], ax_cv_cpp_ident,
+[AC_TRY_COMPILE([
+#ident "$Id: aclocal.m4,v 1.6 2004/10/04 01:10:52 steve Exp $"
+],[while (0) {}],
+[AS_VAR_SET(ax_cv_cpp_ident, yes)],
+[AS_VAR_SET(ax_cv_cpp_ident, no)])])
+if test $ax_cv_cpp_ident = yes; then
+  ident_support='-DHAVE_CVS_IDENT=1'
+fi
+AC_SUBST(ident_support)
+])# AC_CPP_IDENT
+
+
+# _AX_C_UNDERSCORES_MATCH_IFELSE(PATTERN, ACTION-IF-MATCH, ACTION-IF-NOMATCH)
+# ------------------------------
+# Sub-macro for AX_C_UNDERSCORES_LEADING and AX_C_UNDERSCORES_TRAILING.
+# Unwarranted assumptions:
+#   - the object file produced by AC_COMPILE_IFELSE is called "conftest.$ac_objext"
+#   - the nm(1) utility is available, and its name is "nm".
+AC_DEFUN([_AX_C_UNDERSCORES_MATCH_IF],
+[AC_COMPILE_IFELSE([void underscore(void){}],
+[AS_IF([nm conftest.$ac_objext|grep $1 >/dev/null 2>/dev/null],[$2],[$3])],
+[AC_MSG_ERROR([underscore test crashed])]
+)])
+
+
+# AX_C_UNDERSCORES_LEADING
+# ---------------------------------
+# Check if symbol names in object files produced by C compiler have
+# leading underscores. Define NEED_LU if so.
+AC_DEFUN([AX_C_UNDERSCORES_LEADING],
+[AC_CACHE_CHECK([for leading underscores], ax_cv_c_underscores_leading,
+[_AX_C_UNDERSCORES_MATCH_IF([_underscore],
+[AS_VAR_SET(ax_cv_c_underscores_leading, yes)],
+[AS_VAR_SET(ax_cv_c_underscores_leading, no)])])
+if test $ax_cv_c_underscores_leading = yes -a "$CYGWIN" != "yes" -a "$MINGW32" != "yes"; then
+ AC_DEFINE(NEED_LU)
+fi
+])# AX_C_UNDERSCORES_LEADING
+
+
+# AX_C_UNDERSCORES_TRAILING
+# ---------------------------------
+# Check if symbol names in object files produced by C compiler have
+# trailing underscores.  Define NEED_TU if so.
+AC_DEFUN([AX_C_UNDERSCORES_TRAILING],
+[AC_CACHE_CHECK([for trailing underscores], ax_cv_c_underscores_trailing,
+[_AX_C_UNDERSCORES_MATCH_IF([underscore_],
+[AS_VAR_SET(ax_cv_c_underscores_trailing, yes)],
+[AS_VAR_SET(ax_cv_c_underscores_trailing, no)])])
+if test $ax_cv_c_underscores_trailing = yes; then
+ AC_DEFINE(NEED_TU)
+fi
+])# AX_C_UNDERSCORES_TRAILING
+
+# AX_WIN32
+# --------
+# Combined check for several flavors of Microsoft Windows so
+# their "issues" can be dealt with
+AC_DEFUN([AX_WIN32],
+[AC_CYGWIN
+AC_MINGW32
+WIN32=no
+AC_MSG_CHECKING([for Microsoft Windows])
+if test "$CYGWIN" = "yes" -o "$MINGW32" = "yes"
+then
+    WIN32=yes
+fi
+AC_SUBST(MINGW32)
+AC_SUBST(WIN32)
+AC_MSG_RESULT($WIN32)
+])# AX_WIN32
+
+# AX_LD_EXTRALIBS
+# ---------------
+# mingw needs to link with libiberty.a, but cygwin alone can't tolerate it
+AC_DEFUN([AX_LD_EXTRALIBS],
+[AC_MSG_CHECKING([for extra libs needed])
+EXTRALIBS=
+case "${host}" in
+     *-*-cygwin* )
+        if test "$MINGW32" = "yes"; then
+            EXTRALIBS="-liberty"
+        fi
+        ;;
+esac
+AC_SUBST(EXTRALIBS)
+AC_MSG_RESULT($EXTRALIBS)
+])# AX_LD_EXTRALIBS
+
+# AX_LD_SHAREDLIB_OPTS
+# --------------------
+# linker options when building a shared library
+AC_DEFUN([AX_LD_SHAREDLIB_OPTS],
+[AC_MSG_CHECKING([for shared library link flag])
+shared=-shared
+case "${host}" in
+     *-*-cygwin*)
+        shared="-shared -Wl,--enable-auto-image-base"
+        ;;
+
+     *-*-hpux*)
+        shared="-b"
+        ;;
+
+     *-*-darwin1.[0123])
+        shared="-bundle -undefined suppress"
+        ;;
+
+     *-*-darwin*)
+        shared="-bundle -undefined suppress -flat_namespace"
+        ;;
+esac
+AC_SUBST(shared)
+AC_MSG_RESULT($shared)
+])# AX_LD_SHAREDLIB_OPTS
+
+# AX_C_PICFLAG
+# ------------
+# The -fPIC flag is used to tell the compiler to make position
+# independent code. It is needed when making shared objects.
+AC_DEFUN([AX_C_PICFLAG],
+[AC_MSG_CHECKING([for flag to make position independent code])
+PICFLAG=-fPIC
+case "${host}" in
+
+     *-*-cygwin*)
+        PICFLAG=
+        ;;
+
+     *-*-hpux*)
+        PICFLAG=+z
+        ;;
+
+esac
+AC_SUBST(PICFLAG)
+AC_MSG_RESULT($PICFLAG)
+])# AX_C_PICFLAG
+
+# AX_LD_RDYNAMIC
+# --------------
+# The -rdynamic flag is used by iverilog when compiling the target,
+# to know how to export symbols of the main program to loadable modules
+# that are brought in by -ldl
+AC_DEFUN([AX_LD_RDYNAMIC],
+[AC_MSG_CHECKING([for -rdynamic compiler flag])
+rdynamic=-rdynamic
+case "${host}" in
+
+    *-*-netbsd*)
+        rdynamic="-Wl,--export-dynamic"
+        ;;
+
+    *-*-openbsd*)
+        rdynamic="-Wl,--export-dynamic"
+        ;;
+
+    *-*-solaris*)
+        rdynamic=""
+        ;;
+
+    *-*-cygwin*)
+        rdynamic=""
+        ;;
+
+    *-*-hpux*)
+        rdynamic="-E"
+        ;;
+
+    *-*-darwin*)
+        rdynamic="-Wl,-all_load"
+        strip_dynamic="-SX"
+        ;;
+
+esac
+AC_SUBST(rdynamic)
+AC_MSG_RESULT($rdynamic)
+AC_SUBST(strip_dynamic)
+# since we didn't tell them we're "checking", no good place to tell the answer
+# AC_MSG_RESULT($strip_dynamic)
+])# AX_LD_RDYNAMIC
+
+# AX_CPP_PRECOMP
+# --------------
+AC_DEFUN([AX_CPP_PRECOMP],
+[# Darwin requires -no-cpp-precomp
+case "${host}" in
+    *-*-darwin*)
+        CPPFLAGS="-no-cpp-precomp $CPPFLAGS"
+        CFLAGS="-no-cpp-precomp $CFLAGS"
+        ;;
+esac
+])# AX_CPP_PRECOMP
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: async.cc,v 1.4 2002/08/18 22:07:16 steve Exp $"
+#ident "$Id: async.cc,v 1.7 2004/01/18 23:26:54 steve Exp $"
 #endif

 # include "config.h"
@@ -36,11 +36,22 @@ bool NetCondit::is_asynchronous()
      return false;
 }

+/*
+ * NetEvWait statements come from statements of the form @(...) in the
+ * Verilog source. These event waits are considered asynchronous if
+ * all of the events in the list are ANYEDGE, and all the inputs to
+ * the statement are included in the sensitivity list. If any of the
+ * events are posedge or negedge, the statement is synchronous
+ * (i.e. an edge-triggered flip-flop) and if any of the inputs are
+ * unaccounted for in the sensitivity list then the statement is a
+ * latch.
+ */
 bool NetEvWait::is_asynchronous()
 {
 	/* The "sense" set contains the set of Nexa that are in the
-	   sensitivity list. We also presume here that the list is
-	   only LEVEL sensitive. */
+	   sensitivity list. We also require that the events are all
+	   level sensitive, but the nex_async_ method takes care of
+	   that test. */
      NexusSet*sense = new NexusSet;
      for (unsigned idx = 0 ;  idx < nevents_ ;  idx += 1) {
 	    NexusSet*tmp = event(idx)->nex_async_();
@@ -63,6 +74,9 @@ bool NetEvWait::is_asynchronous()

      delete sense;
      delete inputs;
+
+	/* If it passes all the other tests, then this statement is
+	   asynchronous. */
      return true;
 }

@@ -81,6 +95,15 @@ bool NetProcTop::is_asynchronous()

 /*
 * $Log: async.cc,v $
+ * Revision 1.7  2004/01/18 23:26:54  steve
+ *  The is_combinational function really need not recurse.
+ *
+ * Revision 1.6  2003/12/20 00:33:39  steve
+ *  More thorough check that NetEvWait is asynchronous.
+ *
+ * Revision 1.5  2003/09/04 20:28:05  steve
+ *  Support time0 resolution of combinational threads.
+ *
 * Revision 1.4  2002/08/18 22:07:16  steve
 *  Detect temporaries in sequential block synthesis.
 *
@@ -1,4 +1,13 @@

+ATTRIBUTE NAMING CONVENTIONS
+
+Attributes that are specific to Icarus Verilog, and are intended to be
+of use to programmers, start with the prefix "ivl_".
+
+Attributes with the "_ivl_" prefix are set aside for internal
+use. They may be generated internally by the compiler. They need not
+be documented here.
+
 ATTRIBUTES TO CONTROL SYNTHESIS

 The following is a summary of Verilog attributes that Icarus Verilog
@@ -28,22 +37,49 @@ warning.)
 (* ivl_synthesis_on *)

    This attribute tells the compiler that the marked always statement
-    is synthesizeable. The compiler will attempt to synthesize the
+    is synthesizable. The compiler will attempt to synthesize the
    code in the marked "always" statement. If it cannot in any way
    synthesize it, then it will report an error.

 (* ivl_synthesis_off *)

    If this value is attached to an "always" statement, then the
-    compiler will *not* synthesize the "always" statment. This can be
+    compiler will *not* synthesize the "always" statement. This can be
    used, for example, to mark embedded test bench code.


+* Attributes for modules
+
+(* ivl_synthesis_cell *)
+
+    If this value is attached to a module during synthesis, that
+    module will be considered a target architecture primitive, and
+    its interior will not be synthesized further.  The module can
+    therefore hold a model for simulation purposes.
+
+
 * Attributes for signals (wire/reg/integer/tri/etc.)

-[ none defined yet ]
+(* PAD = "<pad assignment list>" *)

+    If this attribute is attached to a signal that happens to be a
+    root module port, then targets that support it will use the string
+    value as a list of pin assignments for the port/signal. The format
+    is a comma separated list of location tokens, with the format of
+    the token itself defined by the back-end tools in use.

 * Other Attributes

 [ none defined yet ]
+
+
+MISC
+
+(* _ivl_schedule_push *)
+
+    If this attribute is attached to a thread object (always or
+    initial statement) then the vvp code generator will generate code
+    that causes the scheduler to push this thread at compile time. The
+    compiler may internally add this attribute to always statements if
+    it detects that it is combinational. This helps resolve time-0
+    races.
@@ -9,10 +9,10 @@
 echo "Autoconf in root..."
 autoconf

-for dir in vpip vvp tgt-vvp tgt-fpga libveriuser
+for dir in vpip vpi vvp tgt-vvp tgt-fpga tgt-stub libveriuser cadpli
 do
    echo "Autoconf in $dir..."
-    ( cd ./$dir ; autoconf )
+    ( cd ./$dir ; autoconf --include=.. )
 done

 echo "Precompiling lexor_keyword.gperf"
@@ -0,0 +1,7 @@
+Makefile
+cadpli.vpl
+dep
+configure
+config.log
+config.status
+autom4te.cache
@@ -0,0 +1,107 @@
+#
+#    This source code is free software; you can redistribute it
+#    and/or modify it in source code form under the terms of the GNU
+#    Library General Public License as published by the Free Software
+#    Foundation; either version 2 of the License, or (at your option)
+#    any later version.
+#
+#    This program is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU Library General Public License for more details.
+#
+#    You should have received a copy of the GNU Library General Public
+#    License along with this program; if not, write to the Free
+#    Software Foundation, Inc.,
+#    59 Temple Place - Suite 330
+#    Boston, MA 02111-1307, USA
+#
+#ident "$Id: Makefile.in,v 1.12 2006/02/15 18:42:42 steve Exp $"
+#
+#
+SHELL = /bin/sh
+
+VERSION = 0.0
+
+prefix = @prefix@
+exec_prefix = @exec_prefix@
+srcdir = @srcdir@
+
+VPATH = $(srcdir)
+
+bindir = @bindir@
+libdir = @libdir@
+includedir = $(prefix)/include
+
+vpidir = @libdir@/ivl/@vpidir1@
+
+strip_dynamic=@strip_dynamic@
+
+CC = @CC@
+INSTALL = @INSTALL@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_DATA = @INSTALL_DATA@
+
+CPPFLAGS = @ident_support@ -I$(srcdir) -I$(srcdir)/.. -I.. @CPPFLAGS@ @DEFS@ @PICFLAG@
+CFLAGS = -Wall @CFLAGS@
+LDFLAGS = @LDFLAGS@
+STRIP = @STRIP@
+
+SHARED = @shared@
+
+all:
+
+ifeq (@enable_vvp32@,yes)
+vpidir32 = $(libdir)/ivl/@vpidir2@
+ALL32 = all32
+INSTALL32 = install32
+UNINSTALL32 = uninstall32
+include $(srcdir)/enable_vvp32.mk
+endif
+
+all: dep cadpli.vpl $(ALL32)
+
+# No specific check operations.
+check: all
+
+dep:
+	mkdir dep
+
+%.o: %.c
+	$(CC) $(CPPFLAGS) $(CFLAGS) -MD -c $<
+	mv $*.d dep
+
+O = cadpli.o
+
+SYSTEM_VPI_LDFLAGS = -L../vvp -lvpi
+ifeq (@WIN32@,yes)
+    SYSTEM_VPI_LDFLAGS += @EXTRALIBS@
+endif
+
+cadpli.vpl: $O ../vvp/libvpi.a ../libveriuser/libveriuser.o
+	$(CC) @shared@ -o $@ $O ../libveriuser/libveriuser.o $(SYSTEM_VPI_LDFLAGS)
+
+clean:
+	rm -rf *.o dep cadpli.vpl bin32
+
+distclean: clean
+	rm -f Makefile config.status config.log config.cache
+
+install: all installdirs $(vpidir)/cadpli.vpl $(INSTALL32)
+
+$(vpidir)/cadpli.vpl: ./cadpli.vpl
+	$(INSTALL_PROGRAM) ./cadpli.vpl $(vpidir)/cadpli.vpl
+
+installdirs: ../mkinstalldirs
+	$(srcdir)/../mkinstalldirs $(vpidir)
+
+uninstall: $(UNINSTALL32)
+	rm -f $(vpidir)/cadpli.vpl
+
+uninstall32:
+
+ifeq (@enable_vvp32@,yes)
+include $(srcdir)/enable_vvp32.mk
+endif
+
+-include $(patsubst %.o, dep/%.d, $O)
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2003 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: cadpli.c,v 1.7 2004/09/10 00:15:45 steve Exp $"
+#endif
+
+# include  <vpi_user.h>
+# include  <veriuser.h>
+# include  <stdlib.h>
+#ifdef HAVE_MALLOC_H
+# include  <malloc.h>
+#endif
+# include  <string.h>
+# include  <assert.h>
+# include  "ivl_dlfcn.h"
+
+typedef void* (*funcvp)(void);
+
+static void thunker_register(void)
+{
+      struct t_vpi_vlog_info vlog_info;
+      void*mod;
+      void*boot;
+      struct t_tfcell*tf;
+      int idx;
+
+      vpi_get_vlog_info(&vlog_info);
+
+      for (idx = 0 ;  idx < vlog_info.argc ;  idx += 1) {
+	    char*module, *cp, *bp;
+	    if (strncmp("-cadpli=", vlog_info.argv[idx], 8) != 0)
+		  continue;
+
+	    cp = vlog_info.argv[idx] + 8;
+	    assert(cp);
+
+	    bp = strchr(cp, ':');
+	    assert(bp);
+
+	    module = malloc(bp-cp+1);
+	    strncpy(module, cp, bp-cp);
+	    module[bp-cp] = 0;
+
+	    mod = ivl_dlopen(module);
+	    if (mod == 0) {
+		  vpi_printf("%s link: %s\n", vlog_info.argv[idx], dlerror());
+		  free(module);
+		  continue;
+	    }
+
+	    bp += 1;
+	    boot = ivl_dlsym(mod, bp);
+	    if (boot == 0) {
+		  vpi_printf("%s: Symbol %s not found.\n",
+			     vlog_info.argv[idx], bp);
+		  free(module);
+		  continue;
+	    }
+
+	    free(module);
+	    assert(boot);
+
+	    tf = (*((funcvp)boot))();
+	    assert(tf);
+
+	    veriusertfs_register_table(tf);
+      }
+}
+
+void (*vlog_startup_routines[])() = {
+      thunker_register,
+      0
+};
+
+
+/*
+ * $Log: cadpli.c,v $
+ * Revision 1.7  2004/09/10 00:15:45  steve
+ *  Remove bad casts.
+ *
+ * Revision 1.6  2004/09/05 21:19:51  steve
+ *  Better type safety.
+ *
+ * Revision 1.5  2003/08/26 16:26:02  steve
+ *  ifdef idents correctly.
+ *
+ * Revision 1.4  2003/04/30 01:28:06  steve
+ *  Remove veriusertfs stuf.
+ *
+ * Revision 1.3  2003/02/22 04:04:38  steve
+ *  Only include malloc.h if it is present.
+ *
+ * Revision 1.2  2003/02/17 00:01:25  steve
+ *  Use a variant of ivl_dlfcn to do dynamic loading
+ *  from within the cadpli module.
+ *
+ *  Change the +cadpli flag to -cadpli, to keep the
+ *  plusargs namespace clear.
+ *
+ * Revision 1.1  2003/02/16 02:23:54  steve
+ *  Add the cadpli interface module.
+ *
+ */
+
@@ -0,0 +1,48 @@
+
+CADENCE PLI1 MODULES
+
+   Copyright 2003 Stephen Williams
+   $Id: cadpli.txt,v 1.2 2003/02/17 00:01:25 steve Exp $
+
+With the cadpli module, Icarus Verilog is able to load PLI1
+applications that were compiled and linked to be dynamic loaded by
+Verilog-XL or NC-Verilog. This allows Icarus Verilog users to run
+third-party modules that were compiled to interface with XL or
+NC. Obviously, this only works on the operating system that the PLI
+application was compiled to run on. For example, a Linux module can
+only be loaded and run under Linux.
+
+Icarus Verilog uses an interface module, the "cadpli" module, to
+connect the worlds. This module is installed with Icarus Verilog, and
+is invoked by the usual -m flag to iverilog or vvp. This module in
+turn scans the extended arguments, looking for +cadpli= arguments. The
+latter specify the share object and bootstrap function for running the
+module. For example, to run the module product.so, that has the
+bootstrap function "my_boot":
+
+    vvp -mcadpli a.out -cadpli=./product.so:my_boot
+
+The "-mcadpli" argument causes vvp to load the cadpli.vpl library
+module. This activates the -cadpli= argument interpreter. The
+-cadpli=<module>:<boot_func> argument, then, causes vvp, through the
+cadpli module, to load the loadable PLI application, invoke the
+my_boot function to get a veriusertfs table, and scan that table to
+register the system tasks and functions exported by that object. The
+format of the -cadpli= extended argument is essentially the same as
+the +loadpli1= argument to Verilog-XL.
+
+The integration from this point is seamless. The PLI application
+hardly knows that it is being invoked by Icarus Verilog instead of
+Verilog-XL, so operates as it would otherwise.
+
+$Log: cadpli.txt,v $
+Revision 1.2  2003/02/17 00:01:25  steve
+ Use a variant of ivl_dlfcn to do dynamic loading
+ from within the cadpli module.
+
+ Change the +cadpli flag to -cadpli, to keep the
+ plusargs namespace clear.
+
+Revision 1.1  2003/02/16 02:44:47  steve
+ Add the cadpli HOWTO.
+
@@ -0,0 +1,76 @@
+AC_INIT(Makefile.in)
+
+AC_PROG_CC
+AC_PROG_CXX
+AC_CHECK_TOOL(STRIP, strip, true)
+
+AC_EXEEXT
+AC_SUBST(EXEEXT)
+
+# Combined check for Microsoft-related bogosities; sets WIN32 if found
+AX_WIN32
+
+AC_PROG_INSTALL
+
+# vvp32 is by default disabled
+#enable_vvp32=no
+AC_SUBST(enable_vvp32)
+
+AC_CHECK_HEADERS(malloc.h)
+
+AC_CHECK_SIZEOF(unsigned long long)
+AC_CHECK_SIZEOF(unsigned long)
+AC_CHECK_SIZEOF(unsigned)
+
+# --
+# Look for a dl library to use. First look for the standard dlopen
+# functions, and failing that look for the HP specific shl_load function.
+
+AC_CHECK_HEADERS(dlfcn.h dl.h, break)
+
+DLLIB=''
+AC_CHECK_LIB(dl,dlopen,[DLLIB=-ldl])
+if test -z "$DLLIB" ; then
+AC_CHECK_LIB(dld,shl_load,[DLLIB=-ldld])
+fi
+AC_SUBST(DLLIB)
+
+AX_CPP_PRECOMP
+
+# Compiler option for position independent code, needed whan making shared objects.
+AX_C_PICFLAG
+
+# Linker option used when compiling the target
+AX_LD_RDYNAMIC
+
+# linker options when building a shared library
+AX_LD_SHAREDLIB_OPTS
+
+AX_LD_EXTRALIBS
+
+#######################
+## test for underscores. The vpi module loader in vvm needs to know this
+## in order to know the name of the start symbol for the .vpi module.
+#######################
+
+AX_C_UNDERSCORES_LEADING
+AX_C_UNDERSCORES_TRAILING
+
+#######################
+## end of test for underscores
+#######################
+
+AX_CPP_IDENT
+
+# where to put vpi subdirectories
+AC_MSG_CHECKING(for VPI subdirectories)
+if test x${vpidir1} = x
+then
+	vpidir1="."
+fi
+
+AC_SUBST(vpidir1)
+AC_SUBST(vpidir2)
+AC_MSG_RESULT(${vpidir1} ${vpidir2})
+
+AC_OUTPUT(Makefile)
@@ -0,0 +1,39 @@
+#
+#    This source code is free software; you can redistribute it
+#    and/or modify it in source code form under the terms of the GNU
+#    Library General Public License as published by the Free Software
+#    Foundation; either version 2 of the License, or (at your option)
+#    any later version.
+#
+#    This program is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU Library General Public License for more details.
+#
+#    You should have received a copy of the GNU Library General Public
+#    License along with this program; if not, write to the Free
+#    Software Foundation, Inc.,
+#    59 Temple Place - Suite 330
+#    Boston, MA 02111-1307, USA
+#
+#ident "$Id: enable_vvp32.mk,v 1.1 2003/10/09 01:07:20 steve Exp $"
+#
+
+all32: bin32 bin32/cadpli.vpl
+
+bin32:
+	mkdir bin32
+
+bin32/%.o: %.c
+	$(CC) -m32 -Wall -I$(srcdir) -I$(srcdir)/.. $(CPPFLAGS) $(CFLAGS) -MD -c $< -o $@
+
+bin32/cadpli.vpl: $(addprefix bin32/,$O) ../vvp/bin32/libvpi.a ../libveriuser/bin32/libveriuser.o
+	$(CC) $(SHARED) -m32 -o $@ $(addprefix bin32/,$O) ../libveriuser/bin32/libveriuser.o ../vvp/bin32/libvpi.a
+
+install32: all32 $(vpidir32)/cadpli.vpl
+
+$(vpidir32)/cadpli.vpl: bin32/cadpli.vpl
+	$(INSTALL_PROGRAM) bin32/cadpli.vpl $(vpidir32)/cadpli.vpl
+
+uninstall32:
+	rm -f $(vpidir32)/cadpli.vpl
@@ -19,7 +19,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: ivl_dlfcn.h,v 1.5 2002/08/12 01:35:06 steve Exp $"
+#ident "$Id: ivl_dlfcn.h,v 1.3 2004/10/04 01:10:56 steve Exp $"
 #endif

 #if defined(__MINGW32__)
@@ -45,14 +45,33 @@ inline void ivl_dlclose(ivl_dll_t dll)
 { (void)FreeLibrary((HINSTANCE)dll);}

 inline const char *dlerror(void)
-{ static char s[30]; sprintf(s,"DLError:%ld", GetLastError()); return s;}
+{
+  static char msg[256];
+  unsigned long err = GetLastError();
+  FormatMessage(
+		FORMAT_MESSAGE_FROM_SYSTEM | FORMAT_MESSAGE_IGNORE_INSERTS,
+		NULL,
+		err,
+		MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT), // Default language
+		(LPTSTR) &msg,
+		sizeof(msg) - 1,
+		NULL
+		);
+  return msg;
+}

 #elif defined(HAVE_DLFCN_H)
 inline ivl_dll_t ivl_dlopen(const char*name)
 { return dlopen(name,RTLD_LAZY); }

 inline void* ivl_dlsym(ivl_dll_t dll, const char*nm)
-{ return dlsym(dll, nm); }
+{
+      void*sym = dlsym(dll, nm);
+	/* Not found? try without the leading _ */
+      if (sym == 0 && nm[0] == '_')
+	    sym = dlsym(dll, nm+1);
+      return sym;
+}

 inline void ivl_dlclose(ivl_dll_t dll)
 { dlclose(dll); }
@@ -77,24 +96,18 @@ inline const char*dlerror(void)

 /*
 * $Log: ivl_dlfcn.h,v $
- * Revision 1.5  2002/08/12 01:35:06  steve
- *  conditional ident string using autoconfig.
+ * Revision 1.3  2004/10/04 01:10:56  steve
+ *  Clean up spurious trailing white space.
 *
- * Revision 1.4  2002/01/23 04:54:38  steve
- *  Load modules with RTLD_LAZY
+ * Revision 1.2  2003/12/12 05:43:08  steve
+ *  Some systems dlsym requires leading _ or not on whim.
 *
- * Revision 1.3  2001/05/22 02:14:47  steve
- *  Update the mingw build to not require cygwin files.
+ * Revision 1.1  2003/02/17 00:01:25  steve
+ *  Use a variant of ivl_dlfcn to do dynamic loading
+ *  from within the cadpli module.
 *
- * Revision 1.2  2001/05/20 15:09:40  steve
- *  Mingw32 support (Venkat Iyer)
- *
- * Revision 1.1  2001/03/16 01:44:34  steve
- *  Add structures for VPI support, and all the %vpi_call
- *  instruction. Get linking of VPI modules to work.
- *
- * Revision 1.1  2001/01/14 17:12:59  steve
- *  possible HP/UX portability support.
+ *  Change the +cadpli flag to -cadpli, to keep the
+ *  plusargs namespace clear.
 *
 */
 #endif
@@ -1,9 +1,4 @@
-
-# The make check target uses this to check the compilation of the
-# compiler.
-
-[-tvvm-check]
-<ivl>./ivl %W %[s-s%s] %[N-N%N] %[T-T%T] -tvvm -Fcprop -Fnodangle -fVPI_MODULE_PATH=vpi %f %m -o%o.cc -- -
-
-[-tvvp-check]
-<ivl>./ivl %W %[s-s%s] %[N-N%N] %[T-T%T] -tdll -fDLL=./tgt-vvp/vvp.tgt -Fcprop -Fnodangle -fVPI_MODULE_PATH=vpi %f %m -o%o -- -
+functor:cprop
+functor:nodangle
+-t:dll
+flag:DLL=tgt-vvp/vvp.tgt
@@ -1,7 +1,7 @@
 #ifndef __compiler_H
 #define __compiler_H
 /*
- * Copyright (c) 1999-2000 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2004 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,10 +19,13 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: compiler.h,v 1.13 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: compiler.h,v 1.30 2005/07/11 16:56:50 steve Exp $"
 #endif

 # include  <list>
+# include  <map>
+# include  "netlist.h"
+# include  "StringHeap.h"

 /*
 * This defines constants and defaults for the compiler in general.
@@ -61,62 +64,134 @@

 /*
 * These are flags to enable various sorts of warnings. By default all
- * the warnings are of, the -W<list> parameter arranges for each to be
- * enabled. 
+ * the warnings are off, the -W<list> parameter arranges for each to be
+ * enabled.
 */

 /* Implicit definitions of wires. */
 extern bool warn_implicit;
 extern bool error_implicit;

-/* inherit timescales accross files. */
+/* inherit timescales across files. */
 extern bool warn_timescale;

+/* Warn about legal but questionable module port bindings. */
+extern bool warn_portbinding;
+
 /* This is true if verbose output is requested. */
 extern bool verbose_flag;

-/* This is an ordered list of library suffixxes to search. */
+extern bool debug_scopes;
+extern bool debug_eval_tree;
+extern bool debug_elaborate;
+extern bool debug_synth2;
+
+/* Path to a directory useful for finding subcomponents. */
+extern const char*basedir;
+
+/* This is an ordered list of library suffixes to search. */
 extern list<const char*>library_suff;
 extern int build_library_index(const char*path, bool key_case_sensitive);

 /* This is the generation of Verilog that the compiler is asked to
-   support. */
+   support. Then there are also more detailed controls for more
+   specific language features. */
 enum generation_t {
      GN_VER1995  = 1,
      GN_VER2001  = 2,
-      GN_SYSVER30 = 3,
+      GN_VER2001X = 3,
      GN_DEFAULT  = 3
 };

 extern generation_t generation_flag;
+extern bool gn_cadence_types_flag;
+
+/* These functions test that specific features are enabled. */
+inline bool gn_cadence_types_enabled()
+{ return gn_cadence_types_flag && generation_flag==GN_VER2001X; }

  /* This is the string to use to invoke the preprocessor. */
 extern char*ivlpp_string;

+extern map<perm_string,unsigned> missing_modules;
+
+/*
+ * the lex_strings are perm_strings made up of tokens from the source
+ * file. Identifiers are so likely to be used many times that it makes
+ * much sense to use a StringHeapLex to hold them.
+ */
+extern StringHeapLex lex_strings;
+
+
+/*
+ * system task/function listings.
+ */
+/*
+ * This table describes all the return values of various system
+ * functions. This table is used to elaborate expressions that are
+ * system function calls.
+ */
+struct sfunc_return_type {
+      const char*   name;
+      ivl_variable_type_t type;
+      unsigned      wid;
+      int           signed_flag;
+};
+
+extern const struct sfunc_return_type* lookup_sys_func(const char*name);
+extern int load_sys_func_table(const char*path);
+
 /*
 * $Log: compiler.h,v $
- * Revision 1.13  2002/08/12 01:34:58  steve
- *  conditional ident string using autoconfig.
+ * Revision 1.30  2005/07/11 16:56:50  steve
+ *  Remove NetVariable and ivl_variable_t structures.
 *
- * Revision 1.12  2002/05/28 20:40:37  steve
- *  ivl indexes the search path for libraries, and
- *  supports case insensitive module-to-file lookup.
+ * Revision 1.29  2005/07/07 16:22:49  steve
+ *  Generalize signals to carry types.
 *
- * Revision 1.11  2002/05/28 00:50:39  steve
- *  Add the ivl -C flag for bulk configuration
- *  from the driver, and use that to run library
- *  modules through the preprocessor.
+ * Revision 1.28  2005/06/28 04:25:55  steve
+ *  Remove reference to SystemVerilog.
 *
- * Revision 1.10  2002/05/24 01:13:00  steve
- *  Support language generation flag -g.
+ * Revision 1.27  2005/04/24 23:44:01  steve
+ *  Update DFF support to new data flow.
 *
- * Revision 1.9  2002/04/22 00:53:39  steve
- *  Do not allow implicit wires in sensitivity lists.
+ * Revision 1.26  2004/10/04 01:10:52  steve
+ *  Clean up spurious trailing white space.
 *
- * Revision 1.8  2002/04/15 00:04:22  steve
- *  Timescale warnings.
+ * Revision 1.25  2004/09/25 01:58:44  steve
+ *  Add a debug_elaborate flag
 *
- * Revision 1.7  2001/11/16 05:07:19  steve
- *  Add support for +libext+ in command files.
+ * Revision 1.24  2004/09/10 23:51:42  steve
+ *  Fix the evaluation of constant ternary expressions.
+ *
+ * Revision 1.23  2004/09/05 17:44:41  steve
+ *  Add support for module instance arrays.
+ *
+ * Revision 1.22  2004/03/10 04:51:24  steve
+ *  Add support for system function table files.
+ *
+ * Revision 1.21  2004/03/09 04:29:42  steve
+ *  Separate out the lookup_sys_func table, for eventual
+ *  support for function type tables.
+ *
+ *  Remove ipal compile flags.
+ *
+ * Revision 1.20  2004/02/18 17:11:54  steve
+ *  Use perm_strings for named langiage items.
+ *
+ * Revision 1.19  2003/11/13 05:55:33  steve
+ *  Move the DLL= flag to target config files.
+ *
+ * Revision 1.18  2003/11/08 20:06:21  steve
+ *  Spelling fixes in comments.
+ *
+ * Revision 1.17  2003/09/25 00:25:14  steve
+ *  Summary list of missing modules.
+ *
+ * Revision 1.16  2003/03/01 06:25:30  steve
+ *  Add the lex_strings string handler, and put
+ *  scope names and system task/function names
+ *  into this table. Also, permallocate event
+ *  names from the beginning.
 */
 #endif
@@ -18,8 +18,8 @@
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
-#if !defined(WINNT)
-#ident "$Id: config.h.in,v 1.5 2002/08/11 23:39:33 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: config.h.in,v 1.11 2004/10/04 01:10:52 steve Exp $"
 #endif

 #if defined(__cplusplus)
@@ -31,21 +31,43 @@
 #endif

 # undef NEED_LU
-# undef NEED_TU  
+# undef NEED_TU
 # undef WLU
 # undef WTU
 # undef HAVE_TIMES
 # undef HAVE_IOSFWD
 # undef HAVE_GETOPT_H
+# undef HAVE_LIBIBERTY_H
 # undef HAVE_MALLOC_H
 # undef HAVE_DLFCN_H
 # undef HAVE_DL_H
 # undef HAVE_FCHMOD
 # undef HAVE_LIBREADLINE
+# undef HAVE_LIBZ
+# undef HAVE_LIBBZ2
 # undef HAVE_SYS_WAIT_H
+# undef WORDS_BIGENDIAN

 /*
 * $Log: config.h.in,v $
+ * Revision 1.11  2004/10/04 01:10:52  steve
+ *  Clean up spurious trailing white space.
+ *
+ * Revision 1.10  2003/08/26 16:26:01  steve
+ *  ifdef idents correctly.
+ *
+ * Revision 1.9  2003/07/03 16:29:55  steve
+ *  spemm WORDS_BIGENDIAN correctly.
+ *
+ * Revision 1.8  2003/03/07 02:44:33  steve
+ *  Implement $realtobits.
+ *
+ * Revision 1.7  2003/02/20 00:49:24  steve
+ *  detect -lz and -lbz2 libraries.
+ *
+ * Revision 1.6  2003/01/10 19:01:04  steve
+ *  Only use libiberty.h if available.
+ *
 * Revision 1.5  2002/08/11 23:39:33  steve
 *  Remove VVM option.
 *
@@ -1,8 +1,10 @@
 #! /bin/sh
-# Configuration validation subroutine script, version 1.1.
-#   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
-#   Free Software Foundation, Inc.
-#
+# Configuration validation subroutine script.
+#   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+#   2000, 2001, 2002 Free Software Foundation, Inc.
+
+timestamp='2002-07-03'
+
 # This file is (in principle) common to ALL GNU software.
 # The presence of a machine in this file suggests that SOME GNU software
 # can handle that machine.  It does not imply ALL GNU software can.
@@ -27,8 +29,8 @@
 # configuration script generated by Autoconf, you may include it under
 # the same distribution terms that you use for the rest of that program.

-# Written by Per Bothner <[email protected]>.
-# Please send patches to <[email protected]>.
+# Please send patches to <[email protected]>.  Submit a context
+# diff and a properly formatted ChangeLog entry.
 #
 # Configuration subroutine to validate and canonicalize a configuration type.
 # Supply the specified configuration type as an argument.
@@ -50,30 +52,73 @@
 #	CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM
 # It is wrong to echo any other type of specification.

-if [ x$1 = x ]
-then
-	echo Configuration name missing. 1>&2
-	echo "Usage: $0 CPU-MFR-OPSYS" 1>&2
-	echo "or     $0 ALIAS" 1>&2
-	echo where ALIAS is a recognized configuration type. 1>&2
-	exit 1
-fi
+me=`echo "$0" | sed -e 's,.*/,,'`

-# First pass through any local machine types.
-case $1 in
-	*local*)
-		echo $1
-		exit 0
-		;;
-	*)
-	;;
+usage="\
+Usage: $0 [OPTION] CPU-MFR-OPSYS
+       $0 [OPTION] ALIAS
+
+Canonicalize a configuration name.
+
+Operation modes:
+  -h, --help         print this help, then exit
+  -t, --time-stamp   print date of last modification, then exit
+  -v, --version      print version number, then exit
+
+Report bugs and patches to <[email protected]>."
+
+version="\
+GNU config.sub ($timestamp)
+
+Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
+Free Software Foundation, Inc.
+
+This is free software; see the source for copying conditions.  There is NO
+warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
+
+help="
+Try \`$me --help' for more information."
+
+# Parse command line
+while test $# -gt 0 ; do
+  case $1 in
+    --time-stamp | --time* | -t )
+       echo "$timestamp" ; exit 0 ;;
+    --version | -v )
+       echo "$version" ; exit 0 ;;
+    --help | --h* | -h )
+       echo "$usage"; exit 0 ;;
+    -- )     # Stop option processing
+       shift; break ;;
+    - )	# Use stdin as input.
+       break ;;
+    -* )
+       echo "$me: invalid option $1$help"
+       exit 1 ;;
+
+    *local*)
+       # First pass through any local machine types.
+       echo $1
+       exit 0;;
+
+    * )
+       break ;;
+  esac
+done
+
+case $# in
+ 0) echo "$me: missing argument$help" >&2
+    exit 1;;
+ 1) ;;
+ *) echo "$me: too many arguments$help" >&2
+    exit 1;;
 esac

 # Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any).
 # Here we must recognize all the valid KERNEL-OS combinations.
 maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
 case $maybe_os in
-  nto-qnx* | linux-gnu*)
+  nto-qnx* | linux-gnu* | freebsd*-gnu* | storm-chaos* | os2-emx* | windows32-* | rtmk-nova*)
    os=-$maybe_os
    basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`
    ;;
@@ -99,7 +144,7 @@ case $os in
 	-convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\
 	-c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \
 	-harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \
-	-apple)
+	-apple | -axis)
 		os=
 		basic_machine=$1
 		;;
@@ -113,6 +158,14 @@ case $os in
 		os=-vxworks
 		basic_machine=$1
 		;;
+	-chorusos*)
+		os=-chorusos
+		basic_machine=$1
+		;;
+ 	-chorusrdb)
+ 		os=-chorusrdb
+		basic_machine=$1
+ 		;;
 	-hiux*)
 		os=-hiuxwe2
 		;;
@@ -171,30 +224,58 @@ esac
 case $basic_machine in
 	# Recognize the basic CPU types without company name.
 	# Some are omitted here because they have special meanings below.
-	tahoe | i860 | ia64 | m32r | m68k | m68000 | m88k | ns32k | arc | arm \
-		| arme[lb] | pyramid | mn10200 | mn10300 | tron | a29k \
-		| 580 | i960 | h8300 \
-		| x86 | ppcbe | mipsbe | mipsle | shbe | shle | armbe | armle \
-		| hppa | hppa1.0 | hppa1.1 | hppa2.0 | hppa2.0w | hppa2.0n \
-		| hppa64 \
-		| alpha | alphaev[4-8] | alphaev56 | alphapca5[67] \
-		| alphaev6[78] \
-		| we32k | ns16k | clipper | i370 | sh | powerpc | powerpcle \
-		| 1750a | dsp16xx | pdp11 | mips16 | mips64 | mipsel | mips64el \
-		| mips64orion | mips64orionel | mipstx39 | mipstx39el \
-		| mips64vr4300 | mips64vr4300el | mips64vr4100 | mips64vr4100el \
-		| mips64vr5000 | miprs64vr5000el | mcore \
-		| sparc | sparclet | sparclite | sparc64 | sparcv9 | v850 | c4x \
-		| thumb | d10v | fr30 | avr)
+	1750a | 580 \
+	| a29k \
+	| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \
+	| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
+	| arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr \
+	| c4x | clipper \
+	| d10v | d30v | dlx | dsp16xx \
+	| fr30 | frv \
+	| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
+	| i370 | i860 | i960 | ia64 \
+	| ip2k \
+	| m32r | m68000 | m68k | m88k | mcore \
+	| mips | mipsbe | mipseb | mipsel | mipsle \
+	| mips16 \
+	| mips64 | mips64el \
+	| mips64orion | mips64orionel \
+	| mips64vr4100 | mips64vr4100el \
+	| mips64vr4300 | mips64vr4300el \
+	| mips64vr5000 | mips64vr5000el \
+	| mipsisa32 | mipsisa32el \
+	| mipsisa64 | mipsisa64el \
+	| mipsisa64sb1 | mipsisa64sb1el \
+	| mipstx39 | mipstx39el \
+	| mn10200 | mn10300 \
+	| ns16k | ns32k \
+	| openrisc | or32 \
+	| pdp10 | pdp11 | pj | pjl \
+	| powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \
+	| pyramid \
+	| sh | sh[1234] | sh3e | sh[34]eb | shbe | shle | sh[1234]le | sh3ele \
+	| sh64 | sh64le \
+	| sparc | sparc64 | sparc86x | sparclet | sparclite | sparcv9 | sparcv9b \
+	| strongarm \
+	| tahoe | thumb | tic80 | tron \
+	| v850 | v850e \
+	| we32k \
+	| x86 | xscale | xstormy16 | xtensa \
+	| z8k)
 		basic_machine=$basic_machine-unknown
 		;;
-	m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | z8k | v70 | h8500 | w65 | pj | pjl)
+	m6811 | m68hc11 | m6812 | m68hc12)
+		# Motorola 68HC11/12.
+		basic_machine=$basic_machine-unknown
+		os=-none
+		;;
+	m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k)
 		;;

 	# We use `pc' rather than `unknown'
 	# because (1) that's what they normally are, and
 	# (2) the word "unknown" tends to confuse beginning users.
-	i[34567]86)
+	i*86 | x86_64)
 	  basic_machine=$basic_machine-pc
 	  ;;
 	# Object if more than one company name word.
@@ -203,28 +284,54 @@ case $basic_machine in
 		exit 1
 		;;
 	# Recognize the basic CPU types with company name.
-	# FIXME: clean up the formatting here.
-	vax-* | tahoe-* | i[34567]86-* | i860-* | ia64-* | m32r-* | m68k-* | m68000-* \
-	      | m88k-* | sparc-* | ns32k-* | fx80-* | arc-* | arm-* | c[123]* \
-	      | mips-* | pyramid-* | tron-* | a29k-* | romp-* | rs6000-* \
-	      | power-* | none-* | 580-* | cray2-* | h8300-* | h8500-* | i960-* \
-	      | xmp-* | ymp-* \
-	      | x86-* | ppcbe-* | mipsbe-* | mipsle-* | shbe-* | shle-* | armbe-* | armle-* \
-	      | hppa-* | hppa1.0-* | hppa1.1-* | hppa2.0-* | hppa2.0w-* \
-	      | hppa2.0n-* | hppa64-* \
-	      | alpha-* | alphaev[4-8]-* | alphaev56-* | alphapca5[67]-* \
-	      | alphaev6[78]-* \
-	      | we32k-* | cydra-* | ns16k-* | pn-* | np1-* | xps100-* \
-	      | clipper-* | orion-* \
-	      | sparclite-* | pdp11-* | sh-* | powerpc-* | powerpcle-* \
-	      | sparc64-* | sparcv9-* | sparc86x-* | mips16-* | mips64-* | mipsel-* \
-	      | mips64el-* | mips64orion-* | mips64orionel-* \
-	      | mips64vr4100-* | mips64vr4100el-* | mips64vr4300-* | mips64vr4300el-* \
-	      | mipstx39-* | mipstx39el-* | mcore-* \
-	      | f301-* | armv*-* | s390-* | sv1-* | t3e-* \
-	      | m88110-* | m680[01234]0-* | m683?2-* | m68360-* | z8k-* | d10v-* \
-	      | thumb-* | v850-* | d30v-* | tic30-* | c30-* | fr30-* \
-	      | bs2000-*)
+	580-* \
+	| a29k-* \
+	| alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \
+	| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \
+	| alphapca5[67]-* | alpha64pca5[67]-* | arc-* \
+	| arm-*  | armbe-* | armle-* | armeb-* | armv*-* \
+	| avr-* \
+	| bs2000-* \
+	| c[123]* | c30-* | [cjt]90-* | c54x-* \
+	| clipper-* | cydra-* \
+	| d10v-* | d30v-* | dlx-* \
+	| elxsi-* \
+	| f30[01]-* | f700-* | fr30-* | frv-* | fx80-* \
+	| h8300-* | h8500-* \
+	| hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \
+	| i*86-* | i860-* | i960-* | ia64-* \
+	| ip2k-* \
+	| m32r-* \
+	| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
+	| m88110-* | m88k-* | mcore-* \
+	| mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
+	| mips16-* \
+	| mips64-* | mips64el-* \
+	| mips64orion-* | mips64orionel-* \
+	| mips64vr4100-* | mips64vr4100el-* \
+	| mips64vr4300-* | mips64vr4300el-* \
+	| mips64vr5000-* | mips64vr5000el-* \
+	| mipsisa32-* | mipsisa32el-* \
+	| mipsisa64-* | mipsisa64el-* \
+	| mipsisa64sb1-* | mipsisa64sb1el-* \
+	| mipstx39 | mipstx39el \
+	| none-* | np1-* | ns16k-* | ns32k-* \
+	| orion-* \
+	| pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
+	| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \
+	| pyramid-* \
+	| romp-* | rs6000-* \
+	| sh-* | sh[1234]-* | sh3e-* | sh[34]eb-* | shbe-* \
+	| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
+	| sparc-* | sparc64-* | sparc86x-* | sparclet-* | sparclite-* \
+	| sparcv9-* | sparcv9b-* | strongarm-* | sv1-* | sx?-* \
+	| tahoe-* | thumb-* | tic30-* | tic54x-* | tic80-* | tron-* \
+	| v850-* | v850e-* | vax-* \
+	| we32k-* \
+	| x86-* | x86_64-* | xps100-* | xscale-* | xstormy16-* \
+	| xtensa-* \
+	| ymp-* \
+	| z8k-*)
 		;;
 	# Recognize the various machine names and aliases which stand
 	# for a CPU type and a company and sometimes even an OS.
@@ -261,14 +368,14 @@ case $basic_machine in
 		os=-sysv
 		;;
 	amiga | amiga-*)
-		basic_machine=m68k-cbm
+		basic_machine=m68k-unknown
 		;;
 	amigaos | amigados)
-		basic_machine=m68k-cbm
+		basic_machine=m68k-unknown
 		os=-amigaos
 		;;
 	amigaunix | amix)
-		basic_machine=m68k-cbm
+		basic_machine=m68k-unknown
 		os=-sysv4
 		;;
 	apollo68)
@@ -287,6 +394,10 @@ case $basic_machine in
 		basic_machine=ns32k-sequent
 		os=-dynix
 		;;
+	c90)
+		basic_machine=c90-cray
+		os=-unicos
+		;;
 	convex-c1)
 		basic_machine=c1-convex
 		os=-bsd
@@ -307,27 +418,30 @@ case $basic_machine in
 		basic_machine=c38-convex
 		os=-bsd
 		;;
-	cray | ymp)
-		basic_machine=ymp-cray
-		os=-unicos
-		;;
-	cray2)
-		basic_machine=cray2-cray
-		os=-unicos
-		;;
-	[ctj]90-cray)
-		basic_machine=c90-cray
+	cray | j90)
+		basic_machine=j90-cray
 		os=-unicos
 		;;
 	crds | unos)
 		basic_machine=m68k-crds
 		;;
+	cris | cris-* | etrax*)
+		basic_machine=cris-axis
+		;;
 	da30 | da30-*)
 		basic_machine=m68k-da30
 		;;
 	decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn)
 		basic_machine=mips-dec
 		;;
+	decsystem10* | dec10*)
+		basic_machine=pdp10-dec
+		os=-tops10
+		;;
+	decsystem20* | dec20*)
+		basic_machine=pdp10-dec
+		os=-tops20
+		;;
 	delta | 3300 | motorola-3300 | motorola-delta \
 	      | 3300-motorola | delta-motorola)
 		basic_machine=m68k-motorola
@@ -369,6 +483,10 @@ case $basic_machine in
 		basic_machine=tron-gmicro
 		os=-sysv
 		;;
+	go32)
+		basic_machine=i386-pc
+		os=-go32
+		;;
 	h3050r* | hiux*)
 		basic_machine=hppa1.1-hitachi
 		os=-hiuxwe2
@@ -444,19 +562,19 @@ case $basic_machine in
 		basic_machine=i370-ibm
 		;;
 # I'm not sure what "Sysv32" means.  Should this be sysv3.2?
-	i[34567]86v32)
+	i*86v32)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
 		os=-sysv32
 		;;
-	i[34567]86v4*)
+	i*86v4*)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
 		os=-sysv4
 		;;
-	i[34567]86v)
+	i*86v)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
 		os=-sysv
 		;;
-	i[34567]86sol2)
+	i*86sol2)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
 		os=-solaris2
 		;;
@@ -468,14 +586,6 @@ case $basic_machine in
 		basic_machine=i386-unknown
 		os=-vsta
 		;;
-	i386-go32 | go32)
-		basic_machine=i386-unknown
-		os=-go32
-		;;
-	i386-mingw32 | mingw32)
-		basic_machine=i386-unknown
-		os=-mingw32
-		;;
 	iris | iris4d)
 		basic_machine=mips-sgi
 		case $os in
@@ -501,6 +611,10 @@ case $basic_machine in
 		basic_machine=ns32k-utek
 		os=-sysv
 		;;
+	mingw32)
+		basic_machine=i386-pc
+		os=-mingw32
+		;;
 	miniframe)
 		basic_machine=m68000-convergent
 		;;
@@ -508,14 +622,6 @@ case $basic_machine in
 		basic_machine=m68k-atari
 		os=-mint
 		;;
-	mipsel*-linux*)
-		basic_machine=mipsel-unknown
-		os=-linux-gnu
-		;;
-	mips*-linux*)
-		basic_machine=mips-unknown
-		os=-linux-gnu
-		;;
 	mips3*-*)
 		basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
 		;;
@@ -530,8 +636,12 @@ case $basic_machine in
 		basic_machine=m68k-rom68k
 		os=-coff
 		;;
+	morphos)
+		basic_machine=powerpc-unknown
+		os=-morphos
+		;;
 	msdos)
-		basic_machine=i386-unknown
+		basic_machine=i386-pc
 		os=-msdos
 		;;
 	mvs)
@@ -595,6 +705,10 @@ case $basic_machine in
 		basic_machine=i960-intel
 		os=-mon960
 		;;
+	nonstopux)
+		basic_machine=mips-compaq
+		os=-nonstopux
+		;;
 	np1)
 		basic_machine=np1-gould
 		;;
@@ -605,6 +719,10 @@ case $basic_machine in
 		basic_machine=hppa1.1-oki
 		os=-proelf
 		;;
+	or32 | or32-*)
+		basic_machine=or32-unknown
+		os=-coff
+		;;
 	OSE68000 | ose68000)
 		basic_machine=m68000-ericsson
 		os=-ose
@@ -630,28 +748,28 @@ case $basic_machine in
        pc532 | pc532-*)
 		basic_machine=ns32k-pc532
 		;;
-	pentium | p5 | k5 | k6 | nexen)
+	pentium | p5 | k5 | k6 | nexgen | viac3)
 		basic_machine=i586-pc
 		;;
-	pentiumpro | p6 | 6x86)
+	pentiumpro | p6 | 6x86 | athlon)
 		basic_machine=i686-pc
 		;;
 	pentiumii | pentium2)
-		basic_machine=i786-pc
+		basic_machine=i686-pc
 		;;
-	pentium-* | p5-* | k5-* | k6-* | nexen-*)
+	pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*)
 		basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'`
 		;;
-	pentiumpro-* | p6-* | 6x86-*)
+	pentiumpro-* | p6-* | 6x86-* | athlon-*)
 		basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'`
 		;;
 	pentiumii-* | pentium2-*)
-		basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'`
+		basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'`
 		;;
 	pn)
 		basic_machine=pn-gould
 		;;
-	power)	basic_machine=rs6000-ibm
+	power)	basic_machine=power-ibm
 		;;
 	ppc)	basic_machine=powerpc-unknown
 	        ;;
@@ -663,9 +781,23 @@ case $basic_machine in
 	ppcle-* | powerpclittle-*)
 		basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'`
 		;;
+	ppc64)	basic_machine=powerpc64-unknown
+	        ;;
+	ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	ppc64le | powerpc64little | ppc64-le | powerpc64-little)
+		basic_machine=powerpc64le-unknown
+	        ;;
+	ppc64le-* | powerpc64little-*)
+		basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
 	ps2)
 		basic_machine=i386-ibm
 		;;
+	pw32)
+		basic_machine=i586-unknown
+		os=-pw32
+		;;
 	rom68k)
 		basic_machine=m68k-rom68k
 		os=-coff
@@ -676,6 +808,12 @@ case $basic_machine in
 	rtpc | rtpc-*)
 		basic_machine=romp-ibm
 		;;
+	s390 | s390-*)
+		basic_machine=s390-ibm
+		;;
+	s390x | s390x-*)
+		basic_machine=s390x-ibm
+		;;
 	sa29200)
 		basic_machine=a29k-amd
 		os=-udi
@@ -687,7 +825,7 @@ case $basic_machine in
 		basic_machine=sh-hitachi
 		os=-hms
 		;;
-	sparclite-wrs)
+	sparclite-wrs | simso-wrs)
 		basic_machine=sparclite-wrs
 		os=-vxworks
 		;;
@@ -745,7 +883,7 @@ case $basic_machine in
 	sun386 | sun386i | roadrunner)
 		basic_machine=i386-sun
 		;;
-	sv1)
+        sv1)
 		basic_machine=sv1-cray
 		os=-unicos
 		;;
@@ -753,16 +891,32 @@ case $basic_machine in
 		basic_machine=i386-sequent
 		os=-dynix
 		;;
-	t3e)
-		basic_machine=t3e-cray
+	t3d)
+		basic_machine=alpha-cray
 		os=-unicos
 		;;
+	t3e)
+		basic_machine=alphaev5-cray
+		os=-unicos
+		;;
+	t90)
+		basic_machine=t90-cray
+		os=-unicos
+		;;
+	tic54x | c54x*)
+		basic_machine=tic54x-unknown
+		os=-coff
+		;;
 	tx39)
 		basic_machine=mipstx39-unknown
 		;;
 	tx39el)
 		basic_machine=mipstx39el-unknown
 		;;
+	toad1)
+		basic_machine=pdp10-xkl
+		os=-tops20
+		;;
 	tower | tower-32)
 		basic_machine=m68k-ncr
 		;;
@@ -809,13 +963,17 @@ case $basic_machine in
 		basic_machine=hppa1.1-winbond
 		os=-proelf
 		;;
-	xmp)
-		basic_machine=xmp-cray
-		os=-unicos
+	windows32)
+		basic_machine=i386-pc
+		os=-windows32-msvcrt
 		;;
        xps | xps100)
 		basic_machine=xps100-honeywell
 		;;
+	ymp)
+		basic_machine=ymp-cray
+		os=-unicos
+		;;
 	z8k-*-coff)
 		basic_machine=z8k-unknown
 		os=-sim
@@ -836,13 +994,6 @@ case $basic_machine in
 	op60c)
 		basic_machine=hppa1.1-oki
 		;;
-	mips)
-		if [ x$os = x-linux-gnu ]; then
-			basic_machine=mips-unknown
-		else
-			basic_machine=mips-mips
-		fi
-		;;
 	romp)
 		basic_machine=romp-ibm
 		;;
@@ -852,13 +1003,23 @@ case $basic_machine in
 	vax)
 		basic_machine=vax-dec
 		;;
+	pdp10)
+		# there are many clones, so DEC is not a safe bet
+		basic_machine=pdp10-unknown
+		;;
 	pdp11)
 		basic_machine=pdp11-dec
 		;;
 	we32k)
 		basic_machine=we32k-att
 		;;
-	sparc | sparcv9)
+	sh3 | sh4 | sh3eb | sh4eb | sh[1234]le | sh3ele)
+		basic_machine=sh-unknown
+		;;
+	sh64)
+		basic_machine=sh64-unknown
+		;;
+	sparc | sparcv9 | sparcv9b)
 		basic_machine=sparc-sun
 		;;
        cydra)
@@ -880,6 +1041,9 @@ case $basic_machine in
 		basic_machine=c4x-none
 		os=-coff
 		;;
+	*-unknown)
+		# Make sure to match an already-canonicalized machine name.
+		;;
 	*)
 		echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2
 		exit 1
@@ -936,15 +1100,19 @@ case $os in
 	      | -lynxos* | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \
 	      | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \
 	      | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
+	      | -chorusos* | -chorusrdb* \
 	      | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
-	      | -mingw32* | -linux-gnu* | -uxpv* | -beos* | -mpeix* | -udk* \
+	      | -mingw32* | -linux* | -uxpv* | -beos* | -mpeix* | -udk* \
 	      | -interix* | -uwin* | -rhapsody* | -darwin* | -opened* \
-	      | -openstep* | -oskit*)
+	      | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \
+	      | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \
+	      | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \
+	      | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* | -powermax*)
 	# Remember, each alternative MUST END IN *, to match a version number.
 		;;
 	-qnx*)
 		case $basic_machine in
-		    x86-* | i[34567]86-*)
+		    x86-* | i*86-*)
 			;;
 		    *)
 			os=-nto$os
@@ -961,9 +1129,6 @@ case $os in
 	-mac*)
 		os=`echo $os | sed -e 's|mac|macos|'`
 		;;
-	-linux*)
-		os=`echo $os | sed -e 's|linux|linux-gnu|'`
-		;;
 	-sunos5*)
 		os=`echo $os | sed -e 's|sunos5|solaris2|'`
 		;;
@@ -991,16 +1156,22 @@ case $os in
 	-acis*)
 		os=-aos
 		;;
+	-atheos*)
+		os=-atheos
+		;;
 	-386bsd)
 		os=-bsd
 		;;
 	-ctix* | -uts*)
 		os=-sysv
 		;;
+	-nova*)
+		os=-rtmk-nova
+		;;
 	-ns2 )
 	        os=-nextstep2
 		;;
-	-nsk)
+	-nsk*)
 		os=-nsk
 		;;
 	# Preserve the version number of sinix5.
@@ -1037,7 +1208,7 @@ case $os in
 	-xenix)
 		os=-xenix
 		;;
-        -*mint | -*MiNT)
+        -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*)
 	        os=-mint
 		;;
 	-none)
@@ -1071,6 +1242,10 @@ case $basic_machine in
 	arm*-semi)
 		os=-aout
 		;;
+	# This must come before the *-dec entry.
+	pdp10-*)
+		os=-tops20
+		;;
        pdp11-*)
 		os=-none
 		;;
@@ -1098,6 +1273,9 @@ case $basic_machine in
 	mips*-*)
 		os=-elf
 		;;
+	or32-*)
+		os=-coff
+		;;
 	*-tti)	# must be before sparc entry or we get the wrong os.
 		os=-sysv3
 		;;
@@ -1179,7 +1357,7 @@ case $basic_machine in
 	*-masscomp)
 		os=-rtu
 		;;
-	f301-fujitsu)
+	f30[01]-fujitsu | f700-fujitsu)
 		os=-uxpv
 		;;
 	*-rom68k)
@@ -1245,7 +1423,7 @@ case $basic_machine in
 			-ptx*)
 				vendor=sequent
 				;;
-			-vxsim* | -vxworks*)
+			-vxsim* | -vxworks* | -windiss*)
 				vendor=wrs
 				;;
 			-aux*)
@@ -1257,12 +1435,23 @@ case $basic_machine in
 			-mpw* | -macos*)
 				vendor=apple
 				;;
-			-*mint | -*MiNT)
+			-*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*)
 				vendor=atari
 				;;
+			-vos*)
+				vendor=stratus
+				;;
 		esac
 		basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"`
 		;;
 esac

 echo $basic_machine$os
+exit 0
+
+# Local variables:
+# eval: (add-hook 'write-file-hooks 'time-stamp)
+# time-stamp-start: "timestamp='"
+# time-stamp-format: "%:y-%02m-%02d"
+# time-stamp-end: "'"
+# End:
@@ -1,7 +1,9 @@
 dnl Process this file with autoconf to produce a configure script.
 AC_INIT(netlist.h)
 AC_CONFIG_HEADER(config.h)
+AC_CONFIG_HEADER(_pli_types.h)

+AC_CANONICAL_HOST
 dnl Checks for programs.
 AC_PROG_CC
 AC_PROG_CXX
@@ -9,9 +11,13 @@ AC_CHECK_TOOL(STRIP, strip, true)
 AC_CHECK_PROGS(XGPERF,gperf,none)
 if test "$XGPERF" = "none"
 then
-        echo "*** Error: No suitable gperf found. ***"
-        echo "    Please install the 'gperf' package."
-        exit 1
+	echo ""
+        echo "*** Warning: No suitable gperf found. ***"
+	echo "    The gperf package is essential for building ivl from"
+	echo "    CVS sources, or modifying the parse engine of ivl itself."
+	echo "    You can get away without it when simply building from"
+	echo "    snapshots or major releases."
+	echo ""
 fi

 AC_CHECK_PROGS(LEX,flex,none)
@@ -30,9 +36,29 @@ then
        exit 1
 fi

+AC_EXEEXT
+AC_SUBST(EXEEXT)
+
+# Combined check for Microsoft-related bogosities; sets WIN32 if found
+AX_WIN32
+
+# vvp32 is by default disabled
+#enable_vvp32=no
+AC_SUBST(enable_vvp32)
+
+
 AC_LANG_CPLUSPLUS

-AC_CHECK_HEADERS(getopt.h malloc.h iosfwd sys/wait.h)
+AC_CHECK_HEADERS(getopt.h malloc.h inttypes.h libiberty.h iosfwd sys/wait.h)
+
+AC_CHECK_LIB(z, gzwrite)
+AC_CHECK_LIB(z, gzwrite, HAVE_LIBZ=yes, HAVE_LIBZ=no)
+AC_SUBST(HAVE_LIBZ)
+if test "$WIN32" = "yes"; then
+AC_CHECK_LIB(bz2, main)
+else
+AC_CHECK_LIB(bz2, BZ2_bzdopen)
+fi

 AC_MSG_CHECKING(for sys/times)
 AC_TRY_LINK(
@@ -45,16 +71,6 @@ do_times=no
 )
 AC_MSG_RESULT($do_times)

-AC_CHECK_HEADER(ipal.h, HAVE_IPAL=yes, HAVE_IPAL=)
-AC_ARG_WITH(ipal,
-    [  --with-ipal             enable PAL target],
-if test "$with_ipal" = no; then
-       echo Disabling ipal support
-       HAVE_IPAL=
-fi
-)
-AC_SUBST(HAVE_IPAL)
-
 # --
 # Look for a dl library to use. First look for the standard dlopen
 # functions, and failing that look for the HP specific shl_load function.
@@ -71,188 +87,61 @@ AC_SUBST(DLLIB)
 AC_PROG_INSTALL

 AC_LANG_C
+AC_C_BIGENDIAN

-AC_CANONICAL_HOST
 # $host

-# The -fPIC flag is used to tell the compiler to make position
-# independent code. It is needed when making shared objects.
+AX_LD_EXTRALIBS

-AC_MSG_CHECKING("for flag to make position independent code")
-PICFLAG=-fPIC
-case "${host}" in
+# Compiler option for position independent code, needed whan making shared objects.
+# CFLAGS inherited by cadpli/Makefile?
+AX_C_PICFLAG

-     *-*-cygwin*)
-	PICFLAG=
-	;;
+# may modify CPPFLAGS and CFLAGS
+AX_CPP_PRECOMP

-     *-*-hpux*)
-	PICFLAG=+z
-	;;
+# Linker option used when compiling the target
+AX_LD_RDYNAMIC

-esac
-AC_SUBST(PICFLAG)
-AC_MSG_RESULT($PICFLAG)
-
-
-# mingw needs to link with libiberty.a, cygwin can tolerate it
-
-AC_MSG_CHECKING("for extra libs needed")
-EXTRALIBS=
-case "${host}" in
-     *-*-cygwin*)
-	EXTRALIBS="-liberty"
-	;;
-esac
-AC_SUBST(EXTRALIBS)
-AC_MSG_RESULT($EXTRALIBS)
-   
-# Darwin requires -no-cpp-precomp
-case "${host}" in
-    *-*-darwin*)
-	CPPFLAGS="-no-cpp-precomp"
-	CFLAGS="-no-cpp-precomp"
-	;;
-esac
-
-# The -rdynamic flag is used by iverilog when compiling the target,
-# to know how to export symbols of the main program to loadable modules
-# that are brought in by -ldl
-AC_MSG_CHECKING("for -rdynamic compiler flag")
-
-rdynamic=-rdynamic
-case "${host}" in
-
-    *-*-netbsd*)
-	rdynamic="-Wl,--export-dynamic"
-	;;
-
-    *-*-solaris*)
-	rdynamic=""
-	;;
-
-    *-*-cygwin*)
-	rdynamic=""
-	;;
-
-    *-*-hpux*)
-	rdynamic="-E"
-	;;
-
-    *-*-darwin*)
-	rdynamic="-Wl,-all_load"
-	strip_dynamic="-SX"
-	;;
-
-esac
-AC_SUBST(rdynamic)
-AC_MSG_RESULT($rdynamic)
-AC_SUBST(strip_dynamic)
-AC_MSG_RESULT($strip_dynamic)
-
-AC_MSG_CHECKING("for shared library link flag")
-shared=-shared
-case "${host}" in
-
-     *-*-cygwin*)
-        shared="-shared -Wl,--enable-auto-image-base"
-	;;
-
-     *-*-hpux*)
-	shared="-b"
-	;;
-
-     *-*-darwin1.[0123])
-	shared="-bundle -undefined suppress"
-	;;
-
-     *-*-darwin*)
-	shared="-bundle -undefined suppress -flat_namespace"
-	;;
-esac
-
-AC_SUBST(shared)
-AC_MSG_RESULT($shared)
+# linker options when building a shared library
+AX_LD_SHAREDLIB_OPTS

 #######################
 ## test for underscores. The vpi module loader needs to know this
 ## in order to know the name of the start symbol for the .vpi module.
 #######################

-AC_CYGWIN
-AC_EXEEXT
-AC_MINGW32
-
-
-WIN32=no
-AC_MSG_CHECKING("Checking for windows")
-if test "$CYGWIN" = "yes" -o "$MINGW32" = "yes"
-then
-    WIN32=yes
-fi
-AC_SUBST(WIN32)
-AC_MSG_RESULT($WIN32)
-AC_SUBST(EXEEXT)
-
-
-AC_MSG_CHECKING("for leading and/or trailing underscores")
-cat << EOF > underscore.c
-       void underscore(void){}
-EOF
-
-$CC $shared -c underscore.c > /dev/null 2>&1
-
-CC_LEADING_UNDERSCORE=no
-CC_TRAILING_UNDERSCORE=no
-
-output=`nm underscore.o|grep _underscore 2>&1`
-if test ! -z "$output" -o $WIN32 = "yes"; then
-  CC_LEADING_UNDERSCORE=yes
-  AC_DEFINE(NEED_LU)
-fi
-
-output=`nm underscore.o|grep underscore_ 2>&1`
-if test ! -z "$output"; then
-  CC_TRAILING_UNDERSCORE=yes
-  AC_DEFINE(NEED_TU)
-fi
-
-if test "$CC_LEADING_UNDERSCORE" = yes; then
-  AC_DEFINE(WLU)
-fi
-if test "$CC_TRAILING_UNDERSCORE" = yes; then
-  AC_DEFINE(WTU)
-fi
-
-rm underscore.c underscore.o
-
-AC_MSG_RESULT("$CC_LEADING_UNDERSCORE $CC_TRAILING_UNDERSCORE")
+AX_C_UNDERSCORES_LEADING
+AX_C_UNDERSCORES_TRAILING

 #######################
 ## end of test for underscores
 #######################

-AC_MSG_CHECKING("for ident support in C compiler")
-ident_support='-DHAVE_CVS_IDENT=1'
-case "${host}" in
+AX_CPP_IDENT

-     *-*-cygwin*)
-	ident_support=
-	;;
+# If not otherwise specified, set the libdir64 variable
+# to the same as libdir.
+AC_MSG_CHECKING(for libdir64 path)
+if test x${libdir64} = x
+then
+	libdir64="${libdir}"
+fi
+AC_SUBST(libdir64)
+AC_MSG_RESULT(${libdir64})

-     *-*-darwin*)
-	ident_support=
-	;;
+# where to put vpi subdirectories
+AC_MSG_CHECKING(for VPI subdirectories)
+if test x${vpidir1} = x
+then
+	vpidir1="."
+fi

-     *-*-machten*)
-	ident_support=
-	;;
-esac
+AC_SUBST(vpidir1)
+AC_SUBST(vpidir2)
+AC_MSG_RESULT(${vpidir1} ${vpidir2})

-AC_SUBST(ident_support)
-AC_MSG_RESULT($ident_support)
+# XXX disable tgt-fpga for the moment
+AC_CONFIG_SUBDIRS(vvp vpi tgt-stub tgt-null tgt-vvp libveriuser cadpli)

-
-AC_CONFIG_SUBDIRS(vvp tgt-vvp tgt-fpga libveriuser)
-
-AC_OUTPUT(Makefile vpi/Makefile ivlpp/Makefile driver/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-verilog/Makefile tgt-pal/Makefile)
+AC_OUTPUT(Makefile ivlpp/Makefile driver/Makefile driver-vpi/Makefile tgt-null/Makefile tgt-verilog/Makefile tgt-pal/Makefile)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2000 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2005 Stephen Williams ([email protected])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: cprop.cc,v 1.39 2002/08/20 04:12:22 steve Exp $"
+#ident "$Id: cprop.cc,v 1.55 2006/05/24 04:32:57 steve Exp $"
 #endif

 # include "config.h"
@@ -30,7 +30,7 @@


 /*
- * The cprop function below invokes constant propogation where
+ * The cprop function below invokes constant propagation where
 * possible. The elaboration generates NetConst objects. I can remove
 * these and replace the gates connected to it with simpler ones. I
 * may even be able to replace nets with a new constant.
@@ -55,86 +55,6 @@ void cprop_functor::signal(Design*des, NetNet*obj)

 void cprop_functor::lpm_add_sub(Design*des, NetAddSub*obj)
 {
-	// For now, only additions are handled.
-      if (obj->attribute("LPM_Direction") != verinum("ADD"))
-	    return;
-
-	// If the low bit on the A side is 0, then eliminate it from
-	// the adder, and pass the B side directly to the
-	// result. Don't reduce the adder smaller then a 1-bit
-	// adder. These will be eliminated later.
-      while ((obj->width() > 1)
-	     && obj->pin_DataA(0).nexus()->drivers_constant()
-	     && (obj->pin_DataA(0).nexus()->driven_value() == verinum::V0)) {
-
-	    NetAddSub*tmp = 0;
-	    tmp = new NetAddSub(obj->scope(), obj->name(), obj->width()-1);
-	      //connect(tmp->pin_Aclr(), obj->pin_Aclr());
-	      //connect(tmp->pin_Add_Sub(), obj->pin_Add_Sub());
-	      //connect(tmp->pin_Clock(), obj->pin_Clock());
-	      //connect(tmp->pin_Cin(), obj->pin_Cin());
-	    connect(tmp->pin_Cout(), obj->pin_Cout());
-	      //connect(tmp->pin_Overflow(), obj->pin_Overflow());
-	    for (unsigned idx = 0 ;  idx < tmp->width() ;  idx += 1) {
-		  connect(tmp->pin_DataA(idx), obj->pin_DataA(idx+1));
-		  connect(tmp->pin_DataB(idx), obj->pin_DataB(idx+1));
-		  connect(tmp->pin_Result(idx), obj->pin_Result(idx+1));
-	    }
-	    connect(obj->pin_Result(0), obj->pin_DataB(0));
-	    delete obj;
-	    des->add_node(tmp);
-	    obj = tmp;
-	    count += 1;
-      }
-
-	// Now do the same thing on the B side.
-      while ((obj->width() > 1)
-	     && obj->pin_DataB(0).nexus()->drivers_constant()
-	     && (obj->pin_DataB(0).nexus()->driven_value() == verinum::V0)) {
-
-	    NetAddSub*tmp = 0;
-	    tmp = new NetAddSub(obj->scope(), obj->name(), obj->width()-1);
-	      //connect(tmp->pin_Aclr(), obj->pin_Aclr());
-	      //connect(tmp->pin_Add_Sub(), obj->pin_Add_Sub());
-	      //connect(tmp->pin_Clock(), obj->pin_Clock());
-	      //connect(tmp->pin_Cin(), obj->pin_Cin());
-	    connect(tmp->pin_Cout(), obj->pin_Cout());
-	      //connect(tmp->pin_Overflow(), obj->pin_Overflow());
-	    for (unsigned idx = 0 ;  idx < tmp->width() ;  idx += 1) {
-		  connect(tmp->pin_DataA(idx), obj->pin_DataA(idx+1));
-		  connect(tmp->pin_DataB(idx), obj->pin_DataB(idx+1));
-		  connect(tmp->pin_Result(idx), obj->pin_Result(idx+1));
-	    }
-	    connect(obj->pin_Result(0), obj->pin_DataA(0));
-	    delete obj;
-	    des->add_node(tmp);
-	    obj = tmp;
-	    count += 1;
-      }
-
-	// If the adder is only 1 bit wide, then replace it with the
-	// simple logic gate.
-      if (obj->width() == 1) {
-	    NetLogic*tmp;
-	    if (obj->pin_Cout().is_linked()) {
-		  tmp = new NetLogic(obj->scope(),
-				     des->local_symbol(obj->name()), 3,
-				     NetLogic::AND);
-		  connect(tmp->pin(0), obj->pin_Cout());
-		  connect(tmp->pin(1), obj->pin_DataA(0));
-		  connect(tmp->pin(2), obj->pin_DataB(0));
-		  des->add_node(tmp);
-	    }
-	    tmp = new NetLogic(obj->scope(), obj->name(), 3, NetLogic::XOR);
-	    connect(tmp->pin(0), obj->pin_Result(0));
-	    connect(tmp->pin(1), obj->pin_DataA(0));
-	    connect(tmp->pin(2), obj->pin_DataB(0));
-	    delete obj;
-	    des->add_node(tmp);
-	    count += 1;
-	    return;
-      }
-
 }

 void cprop_functor::lpm_compare(Design*des, NetCompare*obj)
@@ -153,8 +73,13 @@ void cprop_functor::lpm_compare(Design*des, NetCompare*obj)

 void cprop_functor::lpm_compare_eq_(Design*des, NetCompare*obj)
 {
+#if 0
+	/* XXXX Need to reimplement this code to account for vectors. */
      NetScope*scope = obj->scope();

+      unsigned const_count = 0;
+      bool unknown_flag = false;
+
 	/* First, look for the case where constant bits on matching A
 	   and B inputs are different. This this is so, the device can
 	   be completely eliminated and replaced with a constant 0. */
@@ -164,8 +89,21 @@ void cprop_functor::lpm_compare_eq_(Design*des, NetCompare*obj)
 		  continue;
 	    if (! obj->pin_DataB(idx).nexus()->drivers_constant())
 		  continue;
-	    if (obj->pin_DataA(idx).nexus()->driven_value() ==
-		obj->pin_DataB(idx).nexus()->driven_value())
+
+	    const_count += 1;
+
+	    verinum::V abit = obj->pin_DataA(idx).nexus()->driven_value();
+	    verinum::V bbit = obj->pin_DataB(idx).nexus()->driven_value();
+
+	    if ((abit == verinum::V0) && (bbit == verinum::V0))
+		  continue;
+	    if ((abit == verinum::V1) && (bbit == verinum::V1))
+		  continue;
+
+	    unknown_flag = true;
+	    if ((abit == verinum::Vz) || (abit == verinum::Vx))
+		  continue;
+	    if ((bbit == verinum::Vz) || (bbit == verinum::Vx))
 		  continue;

 	    NetConst*zero = new NetConst(scope, obj->name(), verinum::V0);
@@ -176,6 +114,21 @@ void cprop_functor::lpm_compare_eq_(Design*des, NetCompare*obj)
 	    return;
      }

+	/* If all the inputs are constant, then at this point the
+	   result is either V1 or Vx. */
+      if (const_count == obj->width()) {
+
+	    NetConst*val = new NetConst(scope, obj->name(),
+					unknown_flag
+					  ? verinum::Vx
+					  : verinum::V1);
+	    connect(val->pin(0), obj->pin_AEB());
+	    delete obj;
+	    des->add_node(val);
+	    count += 1;
+	    return;
+      }
+
 	/* Still may need the gate. Run through the inputs again, and
 	   look for pairs of constants. Those inputs can be removed. */

@@ -217,7 +170,7 @@ void cprop_functor::lpm_compare_eq_(Design*des, NetCompare*obj)
 	   with a simple XOR gate. */
      if (top == 1) {
 	    NetLogic*tmp = new NetLogic(scope, obj->name(), 3,
-					NetLogic::XNOR);
+					NetLogic::XNOR, 1);
 	    connect(tmp->pin(0), obj->pin_AEB());
 	    connect(tmp->pin(1), obj->pin_DataA(0));
 	    connect(tmp->pin(2), obj->pin_DataB(0));
@@ -240,57 +193,23 @@ void cprop_functor::lpm_compare_eq_(Design*des, NetCompare*obj)
      delete obj;
      des->add_node(tmp);
      count += 1;
+#endif
 }

 void cprop_functor::lpm_ff(Design*des, NetFF*obj)
 {
 	// Look for and count unlinked FF outputs. Note that if the
 	// Data and Q pins are connected together, they can be removed
-	// from the circuit.
-      unsigned unlinked_count = 0;
-      for (unsigned idx = 0 ;  idx < obj->width() ;  idx += 1) {
-	    if (connected(obj->pin_Data(idx), obj->pin_Q(idx))) {
-		  obj->pin_Data(idx).unlink();
-		  obj->pin_Q(idx).unlink();
-	    }
-	    if (! obj->pin_Q(idx).is_linked())
-		  unlinked_count += 1;
-      }
+	// from the circuit, since it doesn't do anything.

-	// If the entire FF is unlinked, remove the whole thing.
-      if (unlinked_count == obj->width()) {
+      if (connected(obj->pin_Data(), obj->pin_Q())
+	  && (! obj->pin_Sclr().is_linked())
+	  && (! obj->pin_Sset().is_linked())
+	  && (! obj->pin_Aclr().is_linked())
+	  && (! obj->pin_Aset().is_linked())) {
+	    obj->pin_Data().unlink();
+	    obj->pin_Q().unlink();
 	    delete obj;
-	    count += 1;
-	    return;
-      }
-
-	// If some of the FFs are unconnected, make a new FF array
-	// that does not include the useless FF devices.
-      if (unlinked_count > 0) {
-	    NetFF*tmp = new NetFF(obj->scope(), obj->name(),
-				  obj->width()-unlinked_count);
-	    connect(tmp->pin_Clock(), obj->pin_Clock());
-	    connect(tmp->pin_Enable(), obj->pin_Enable());
-	    connect(tmp->pin_Aload(), obj->pin_Aload());
-	    connect(tmp->pin_Aset(), obj->pin_Aset());
-	    connect(tmp->pin_Aclr(), obj->pin_Aclr());
-	    connect(tmp->pin_Sload(), obj->pin_Sload());
-	    connect(tmp->pin_Sset(), obj->pin_Sset());
-	    connect(tmp->pin_Sclr(), obj->pin_Sclr());
-
-	    unsigned tidx = 0;
-	    for (unsigned idx = 0 ;  idx < obj->width() ;  idx += 1)
-		  if (obj->pin_Q(idx).is_linked()) {
-			connect(tmp->pin_Data(tidx), obj->pin_Data(idx));
-			connect(tmp->pin_Q(tidx), obj->pin_Q(idx));
-			tidx += 1;
-		  }
-
-	    assert(tidx == obj->width() - unlinked_count);
-	    delete obj;
-	    des->add_node(tmp);
-	    count += 1;
-	    return;
      }
 }

@@ -299,7 +218,11 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
      NetScope*scope = obj->scope();

      switch (obj->type()) {
-
+#if 0
+	      /* XXXX This old code assumed that the individual bit
+		 slices could be replaced with different gates. They
+		 cannot when the device takes atomic vectors, so this
+		 needs to be rewritten. XXXX */
 	  case NetLogic::NAND:
 	  case NetLogic::AND: {
 		unsigned top = obj->pin_count();
@@ -414,12 +337,12 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 			  case NetLogic::AND:
 			    tmp = new NetLogic(scope,
 					       obj->name(), 2,
-					       NetLogic::BUF);
+					       NetLogic::BUF, 1);
 			    break;
 			  case NetLogic::NAND:
 			    tmp = new NetLogic(scope,
 					       obj->name(), 2,
-					       NetLogic::NOT);
+					       NetLogic::NOT, 1);
 			    break;
 			  default:
 			    assert(0);
@@ -445,7 +368,7 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		if (top < obj->pin_count()) {
 		      NetLogic*tmp = new NetLogic(scope,
 						  obj->name(), top,
-						  obj->type());
+						  obj->type(), 1);
 		      tmp->rise_time(obj->rise_time());
 		      tmp->fall_time(obj->fall_time());
 		      tmp->decay_time(obj->decay_time());
@@ -462,7 +385,12 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		}
 		break;
 	  }
-
+#endif
+#if 0
+	      /* XXXX This old code assumed that the individual bit
+		 slices could be replaced with different gates. They
+		 cannot when the device takes atomic vectors, so this
+		 needs to be rewritten. XXXX */

 	  case NetLogic::NOR:
 	  case NetLogic::OR: {
@@ -562,12 +490,12 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 			  case NetLogic::OR:
 			    tmp = new NetLogic(scope,
 					       obj->name(), 2,
-					       NetLogic::BUF);
+					       NetLogic::BUF, 1);
 			    break;
 			  case NetLogic::NOR:
 			    tmp = new NetLogic(scope,
 					       obj->name(), 2,
-					       NetLogic::NOT);
+					       NetLogic::NOT, 1);
 			    break;
 			  default:
 			    assert(0);
@@ -584,7 +512,7 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		      delete obj;
 		      count += 1;
 		      return;
-		}
+v		}

 		  /* Finally, this cleans up the gate by creating a
 		     new [N]OR gate that has the right number of
@@ -592,7 +520,7 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		if (top < obj->pin_count()) {
 		      NetLogic*tmp = new NetLogic(scope,
 						  obj->name(), top,
-						  obj->type());
+						  obj->type(), 1);
 		      tmp->rise_time(obj->rise_time());
 		      tmp->fall_time(obj->fall_time());
 		      tmp->decay_time(obj->decay_time());
@@ -609,7 +537,12 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		}
 		break;
 	  }
-
+#endif
+#if 0
+	      /* XXXX This old code assumed that the individual bit
+		 slices could be replaced with different gates. They
+		 cannot when the device takes atomic vectors, so this
+		 needs to be rewritten. XXXX */
 	  case NetLogic::XNOR:
 	  case NetLogic::XOR: {
 		unsigned top = obj->pin_count();
@@ -731,11 +664,11 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		      if (obj->type() == NetLogic::XOR)
 			    tmp = new NetLogic(scope,
 					       obj->name(), 2,
-					       NetLogic::NOT);
+					       NetLogic::NOT, 1);
 		      else
 			    tmp = new NetLogic(scope,
 					       obj->name(), 2,
-					       NetLogic::BUF);
+					       NetLogic::BUF, 1);

 		      tmp->rise_time(obj->rise_time());
 		      tmp->fall_time(obj->fall_time());
@@ -760,11 +693,11 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		      if (obj->type() == NetLogic::XOR)
 			    tmp = new NetLogic(scope,
 					       obj->name(), 2,
-					       NetLogic::BUF);
+					       NetLogic::BUF, 1);
 		      else
 			    tmp = new NetLogic(scope,
 					       obj->name(), 2,
-					       NetLogic::NOT);
+					       NetLogic::NOT, 1);

 		      tmp->rise_time(obj->rise_time());
 		      tmp->fall_time(obj->fall_time());
@@ -786,7 +719,7 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		if (top < obj->pin_count()) {
 		      NetLogic*tmp = new NetLogic(scope,
 						  obj->name(), top,
-						  obj->type());
+						  obj->type(), 1);
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
 		      tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -799,14 +732,56 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		}
 		break;
 	    }
-
+#endif
 	  default:
 	    break;
      }
 }

+static void replace_with_bufif(Design*des, NetMux*obj, NetLogic::TYPE type)
+{
+      NetScope*scope = obj->scope();
+      NetLogic*tmp = new NetLogic(obj->scope(),
+				  scope->local_symbol(),
+				  3, type, obj->width());
+
+      des->add_node(tmp);
+
+      connect(obj->pin_Result(), tmp->pin(0));
+      connect(obj->pin_Data(type==NetLogic::BUFIF0? 0 : 1),  tmp->pin(1));
+
+      if (obj->width() == 1) {
+	      /* Special case that the expression is 1 bit
+		 wide. Connect the select directly to the enable. */
+	    connect(obj->pin_Sel(), tmp->pin(2));
+
+      } else {
+	      /* General case that the expression is arbitrarily
+		 wide. Replicate the enable signal (which we
+		 assume is 1 bit wide) to match the expression,
+		 and connect the enable vector to the enable
+		 input of the gate. */
+	    NetReplicate*rtmp = new NetReplicate(scope,
+						 scope->local_symbol(),
+						 obj->width(),
+						 obj->width());
+	    des->add_node(rtmp);
+
+	    connect(obj->pin_Sel(), rtmp->pin(1));
+	    connect(tmp->pin(2), rtmp->pin(0));
+
+	    NetNet*rsig = new NetNet(scope, scope->local_symbol(),
+				     NetNet::WIRE, obj->width());
+	    rsig->local_flag(true);
+	    rsig->data_type(IVL_VT_LOGIC);
+	    connect(tmp->pin(2), rsig->pin(0));
+      }
+
+      delete obj;
+}
+
 /*
- * This detects the case where the mux selects between a value an
+ * This detects the case where the mux selects between a value and
 * Vz. In this case, replace the device with a bufif with the sel
 * input used to enable the output.
 */
@@ -821,64 +796,36 @@ void cprop_functor::lpm_mux(Design*des, NetMux*obj)
 	   NetMux with an array of BUFIF1 devices, with the enable
 	   connected to the select input. */
      bool flag = true;
-      for (unsigned idx = 0 ;  idx < obj->width() ;  idx += 1) {
-	    if (! obj->pin_Data(idx, 0).nexus()->drivers_constant()) {
-		  flag = false;
-		  break;
-	    }

-	    if (obj->pin_Data(idx, 0).nexus()->driven_value() != verinum::Vz) {
-		  flag = false;
-		  break;
-	    }
+      if (! obj->pin_Data(0).nexus()->drivers_constant()) {
+	    flag = false;
+      }
+
+      if (flag && obj->pin_Data(0).nexus()->driven_value() != verinum::Vz) {
+	    flag = false;
      }

      if (flag) {
-	    for (unsigned idx = 0 ;  idx < obj->width() ;  idx += 1) {
-		  NetLogic*tmp = new NetLogic(obj->scope(),
-					      des->local_symbol(obj->name()),
-					      3, NetLogic::BUFIF1);
-
-		  connect(obj->pin_Result(idx), tmp->pin(0));
-		  connect(obj->pin_Data(idx,1), tmp->pin(1));
-		  connect(obj->pin_Sel(0), tmp->pin(2));
-		  des->add_node(tmp);
-	    }
-
+	    replace_with_bufif(des, obj, NetLogic::BUFIF1);
 	    count += 1;
-	    delete obj;
 	    return;
      }

+
 	/* If instead the second input is all constant Vz, replace the
 	   NetMux with an array of BUFIF0 devices. */
      flag = true;
-      for (unsigned idx = 0 ;  idx < obj->width() ;  idx += 1) {
-	    if (! obj->pin_Data(idx, 1).nexus()->drivers_constant()) {
-		  flag = false;
-		  break;
-	    }
+      if (! obj->pin_Data(1).nexus()->drivers_constant()) {
+	    flag = false;
+      }

-	    if (obj->pin_Data(idx, 1).nexus()->driven_value() != verinum::Vz) {
-		  flag = false;
-		  break;
-	    }
+      if (flag && obj->pin_Data(1).nexus()->driven_value() != verinum::Vz) {
+	    flag = false;
      }

      if (flag) {
-	    for (unsigned idx = 0 ;  idx < obj->width() ;  idx += 1) {
-		  NetLogic*tmp = new NetLogic(obj->scope(),
-					      des->local_symbol(obj->name()),
-					      3, NetLogic::BUFIF0);
-
-		  connect(obj->pin_Result(idx), tmp->pin(0));
-		  connect(obj->pin_Data(idx,0), tmp->pin(1));
-		  connect(obj->pin_Sel(0), tmp->pin(2));
-		  des->add_node(tmp);
-	    }
-
+	    replace_with_bufif(des, obj, NetLogic::BUFIF0);
 	    count += 1;
-	    delete obj;
 	    return;
      }
 }
@@ -897,7 +844,7 @@ struct cprop_dc_functor  : public functor_t {
 void cprop_dc_functor::lpm_const(Design*des, NetConst*obj)
 {
 	// 'bz constant values drive high impedance to whatever is
-	// connected to it. In otherwords, it is a noop.
+	// connected to it. In other words, it is a noop.
      { unsigned tmp = 0;
        for (unsigned idx = 0 ;  idx < obj->pin_count() ;  idx += 1)
 	      if (obj->value(idx) == verinum::Vz) {
@@ -957,6 +904,13 @@ void cprop_dc_functor::lpm_const(Design*des, NetConst*obj)

 		  assert(tmp->scope());

+		    // If the net is a signal name from the source,
+		    // then users will probably want to see it in the
+		    // waveform dump, so unhooking the constant will
+		    // make it look wrong.
+		  if (! tmp->local_flag())
+			return;
+
 		    // If the net has an eref, then there is an
 		    // expression somewhere that reads this signal. So
 		    // the constant does get read.
@@ -980,7 +934,7 @@ void cprop_dc_functor::lpm_const(Design*des, NetConst*obj)

 void cprop(Design*des)
 {
-	// Continually propogate constants until a scan finds nothing
+	// Continually propagate constants until a scan finds nothing
 	// to do.
      cprop_functor prop;
      do {
@@ -994,6 +948,58 @@ void cprop(Design*des)

 /*
 * $Log: cprop.cc,v $
+ * Revision 1.55  2006/05/24 04:32:57  steve
+ *  Fix handling of ternary-to-bufif0 constant propagation.
+ *
+ * Revision 1.54  2005/07/15 19:22:52  steve
+ *  bufif enable is LOGIC.
+ *
+ * Revision 1.53  2005/05/15 04:44:30  steve
+ *  Disable obsolete logic constant fixup code.
+ *
+ * Revision 1.52  2005/04/24 23:44:01  steve
+ *  Update DFF support to new data flow.
+ *
+ * Revision 1.51  2005/02/12 22:52:45  steve
+ *  Fix copyright notice.
+ *
+ * Revision 1.50  2005/02/12 06:25:40  steve
+ *  Restructure NetMux devices to pass vectors.
+ *  Generate NetMux devices from ternary expressions,
+ *  Reduce NetMux devices to bufif when appropriate.
+ *
+ * Revision 1.49  2005/01/16 04:20:32  steve
+ *  Implement LPM_COMPARE nodes as two-input vector functors.
+ *
+ * Revision 1.48  2004/12/11 02:31:25  steve
+ *  Rework of internals to carry vectors through nexus instead
+ *  of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ *  down this path.
+ *
+ * Revision 1.47  2004/02/20 18:53:34  steve
+ *  Addtrbute keys are perm_strings.
+ *
+ * Revision 1.46  2003/11/08 17:53:34  steve
+ *  Do not remove constants accessible to VPI.
+ *
+ * Revision 1.45  2003/10/31 02:40:06  steve
+ *  Donot elide FF that has set or clr connections.
+ *
+ * Revision 1.44  2003/04/25 05:06:32  steve
+ *  Handle X values in constant == nets.
+ *
+ * Revision 1.43  2003/03/06 00:28:41  steve
+ *  All NetObj objects have lex_string base names.
+ *
+ * Revision 1.42  2003/02/26 01:29:24  steve
+ *  LPM objects store only their base names.
+ *
+ * Revision 1.41  2003/01/30 16:23:07  steve
+ *  Spelling fixes.
+ *
+ * Revision 1.40  2003/01/27 05:09:17  steve
+ *  Spelling fixes.
+ *
 * Revision 1.39  2002/08/20 04:12:22  steve
 *  Copy gate delays when doing gate delay substitutions.
 *
@@ -1013,128 +1019,5 @@ void cprop(Design*des)
 *
 *  Divide signal reference counts between rval
 *  and lval references.
- *
- * Revision 1.34  2002/05/23 03:08:51  steve
- *  Add language support for Verilog-2001 attribute
- *  syntax. Hook this support into existing $attribute
- *  handling, and add number and void value types.
- *
- *  Add to the ivl_target API new functions for access
- *  of complex attributes attached to gates.
- *
- * Revision 1.33  2002/04/14 02:51:37  steve
- *  Fix bug removing pairs of ones in XOR.
- *
- * Revision 1.32  2002/02/03 00:06:28  steve
- *  Comments about xor evaluation.
- *
- * Revision 1.31  2001/12/31 01:56:08  steve
- *  Get sense of 1-bit == operator right.
- *
- * Revision 1.30  2001/10/28 01:14:53  steve
- *  NetObj constructor finally requires a scope.
- *
- * Revision 1.29  2001/07/25 03:10:48  steve
- *  Create a config.h.in file to hold all the config
- *  junk, and support gcc 3.0. (Stephan Boettcher)
- *
- * Revision 1.28  2001/06/15 04:14:18  steve
- *  Generate vvp code for GT and GE comparisons.
- *
- * Revision 1.27  2001/06/07 02:12:43  steve
- *  Support structural addition.
- *
- * Revision 1.26  2001/02/18 01:07:32  steve
- *  check signals in the cprop functor.
- *
- * Revision 1.25  2001/02/16 03:27:31  steve
- *  Constant propagation for compare ==.
- *
- * Revision 1.24  2001/02/10 04:50:54  steve
- *  Catch constants driving root module ports. (PR#130)
- *
- * Revision 1.23  2000/12/30 03:11:15  steve
- *  Propagate initial value of constants into wires.
- *
- * Revision 1.22  2000/11/23 01:55:52  steve
- *  Propagate constants through xnor gates. (PR#51)
- *
- * Revision 1.21  2000/11/19 05:26:58  steve
- *  Replace AND constand propagation.
- *
- * Revision 1.20  2000/11/18 05:13:27  steve
- *  Thorough constant propagation for or and nor gates.
- *
- * Revision 1.19  2000/11/18 04:10:37  steve
- *  Handle constant propagation through XOR gates,
- *  including reducing the gate to a constant,
- *  a buffer or an inverter if possible.
- *
- * Revision 1.18  2000/11/11 00:03:36  steve
- *  Add support for the t-dll backend grabing flip-flops.
- *
- * Revision 1.17  2000/10/07 19:45:42  steve
- *  Put logic devices into scopes.
- *
- * Revision 1.16  2000/10/06 21:26:34  steve
- *  Eliminate zero inputs to xor.
- *
- * Revision 1.15  2000/08/02 14:48:01  steve
- *  use bufif0 if z is in true case of mux.
- *
- * Revision 1.14  2000/07/25 02:55:13  steve
- *  Unlink z constants from nets.
- *
- * Revision 1.13  2000/07/15 05:13:43  steve
- *  Detect muxing Vz as a bufufN.
- *
- * Revision 1.12  2000/06/25 19:59:41  steve
- *  Redesign Links to include the Nexus class that
- *  carries properties of the connected set of links.
- *
- * Revision 1.11  2000/06/24 22:55:19  steve
- *  Get rid of useless next_link method.
- *
- * Revision 1.10  2000/05/14 17:55:04  steve
- *  Support initialization of FF Q value.
- *
- * Revision 1.9  2000/05/07 04:37:56  steve
- *  Carry strength values from Verilog source to the
- *  pform and netlist for gates.
- *
- *  Change vvm constants to use the driver_t to drive
- *  a constant value. This works better if there are
- *  multiple drivers on a signal.
- *
- * Revision 1.8  2000/04/28 21:00:28  steve
- *  Over agressive signal elimination in constant probadation.
- *
- * Revision 1.7  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.6  2000/01/02 17:56:42  steve
- *  Do not delete constants that input to exressions.
- *
- * Revision 1.5  1999/12/30 04:19:12  steve
- *  Propogate constant 0 in low bits of adders.
- *
- * Revision 1.4  1999/12/17 06:18:15  steve
- *  Rewrite the cprop functor to use the functor_t interface.
- *
- * Revision 1.3  1999/12/17 03:38:46  steve
- *  NetConst can now hold wide constants.
- *
- * Revision 1.2  1998/12/02 04:37:13  steve
- *  Add the nobufz function to eliminate bufz objects,
- *  Object links are marked with direction,
- *  constant propagation is more careful will wide links,
- *  Signal folding is aware of attributes, and
- *  the XNF target can dump UDP objects based on LCA
- *  attributes.
- *
- * Revision 1.1  1998/11/13 06:23:17  steve
- *  Introduce netlist optimizations with the
- *  cprop function to do constant propogation.
- *
 */

@@ -1,29 +1,35 @@
-
-This file describes the build procedure under cygwin32 (Windows 95/98/NT/2K)
----------------------------------------------------------------------------
-To build using cygwin:
-
-Prerequisites:
-
- o Latest net release (1.1.4) of cygwin (sources.redhat.com/cygwin)
-
-Procedure:
- o Get the source code - see the main icarus verilog page for how to 
-   do this
- o cd to the verilog directory
- o autoconf.sh
- o ./configure
- o make
- o make install
-
-That's all that's needed.  
-
-To build your own extensions - just include vpi_user.h and link with
-a command like this:
-
- $(CC) -shared -o <dllname> <objects> -Wl,--enable-auto-image-base -L../vvm -lvvm -lvpip
-
- - Venkat Iyer <[email protected]>
-
-
-
+
+This file describes the build procedure under cygwin32 (Windows 95/98/NT/2K)
+----------------------------------------------------------------------------
+
+Note: Icarus Verilog also compiles to native Windows binaries if you
+use the instructions in the mingw.txt file. Some people prefer cygwin
+binaries, and these instructions apply.
+
+
+To build using cygwin:
+
+Prerequisites:
+
+ o Latest net release (1.1.4) of cygwin (sources.redhat.com/cygwin)
+
+Procedure:
+ o Get the source code - see the main Icarus Verilog page for how to
+   do this
+ o cd to the verilog directory
+ o autoconf.sh
+ o ./configure
+ o make
+ o make install
+
+That's all that's needed.
+
+To build your own extensions - just include vpi_user.h and link with
+a command like this:
+
+ $(CC) -shared -o <dllname> <objects> -Wl,--enable-auto-image-base -L../vvm -lvvm -lvpip
+
+ - Venkat Iyer <[email protected]>
+
+
+
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: design_dump.cc,v 1.135 2002/10/23 01:47:17 steve Exp $"
+#ident "$Id: design_dump.cc,v 1.167 2006/07/31 03:50:17 steve Exp $"
 #endif

 # include "config.h"
@@ -29,7 +29,7 @@
 # include  <iostream>
 # include  <iomanip>
 # include  "netlist.h"
-
+# include  "compiler.h"

 static ostream& operator<< (ostream&o, NetBlock::Type t)
 {
@@ -68,6 +68,28 @@ ostream& operator << (ostream&o, Link::strength_t str)
      return o;
 }

+ostream& operator << (ostream&o, ivl_variable_type_t val)
+{
+      switch (val) {
+	  case IVL_VT_VOID:
+	    o << "void";
+	    break;
+	  case IVL_VT_NO_TYPE:
+	    o << "<no_type>";
+	    break;
+	  case IVL_VT_REAL:
+	    o << "real";
+	    break;
+	  case IVL_VT_BOOL:
+	    o << "bool";
+	    break;
+	  case IVL_VT_LOGIC:
+	    o << "logic";
+	    break;
+      }
+      return o;
+}
+
 /* Dump a net. This can be a wire or register. */
 void NetNet::dump_net(ostream&o, unsigned ind) const
 {
@@ -75,6 +97,7 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
 	    pin_count() << "]";
      if (local_flag_)
 	    o << " (local)";
+      o << " " << data_type_;
      if (signed_)
 	    o << " signed";
      switch (port_type_) {
@@ -96,8 +119,10 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
      o << " (eref=" << peek_eref() << ", lref=" << peek_lref() << ")";
      if (scope())
 	    o << " scope=" << scope()->name();
-      o << " #(" << rise_time() << "," << fall_time() << "," <<
-	    decay_time() << ") init=";
+      o << " #(" << rise_time() << "," << fall_time() << ","
+	<<  decay_time() << ") vector_width=" << vector_width()
+	<< " pin_count=" << pin_count()
+	<< " init=";
      for (unsigned idx = pin_count() ;  idx > 0 ;  idx -= 1)
 	    o << pin(idx-1).get_init();

@@ -117,13 +142,6 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
      dump_obj_attr(o, ind+4);
 }

-void NetSubnet::dump_net(ostream&o, unsigned ind) const
-{
-      o << setw(ind) << "" << "** " << name() << " is a NetSubnet **"
-	<< endl;
-      NetNet::dump_net(o, ind);
-}
-
 void NetMemory::dump(ostream&o, unsigned ind) const
 {
      o << setw(ind) << ""  << name_ << "[" << width_ << "] " <<
@@ -189,18 +207,13 @@ void NetObj::dump_obj_attr(ostream&o, unsigned ind) const

 void NetAddSub::dump_node(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "Adder (NetAddSub): " << name() << endl;
+      o << setw(ind) << "" << "Adder (NetAddSub): " << name()
+	<< " width=" << width() << " pin_count=" << pin_count()
+	<< endl;
      dump_node_pins(o, ind+4);
      dump_obj_attr(o, ind+4);
 }

-void NetCAssign::dump_node(ostream&o, unsigned ind) const
-{
-      o << setw(ind) << "" << "Procedural continuous assign (NetCAssign): "
-	<< name() << endl;
-      dump_node_pins(o, ind+4);
-}
-
 void NetCLShift::dump_node(ostream&o, unsigned ind) const
 {
      o << setw(ind) << "" << "Combinatorial shift (NetCLShift): " <<
@@ -216,6 +229,16 @@ void NetCompare::dump_node(ostream&o, unsigned ind) const
      dump_obj_attr(o, ind+4);
 }

+void NetConcat::dump_node(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << "NetConcat: "
+	<< name()
+	<< " scope=" << (scope()? scope()->name() : "")
+	<< " width=" << width_ << endl;
+      dump_node_pins(o, ind+4);
+      dump_obj_attr(o, ind+4);
+}
+
 void NetDivide::dump_node(ostream&o, unsigned ind) const
 {
      o << setw(ind) << "" << "NET_DIVIDE (NetDivide): " << name() << endl;
@@ -223,12 +246,6 @@ void NetDivide::dump_node(ostream&o, unsigned ind) const
      dump_obj_attr(o, ind+4);
 }

-void NetForce::dump_node(ostream&o, unsigned ind) const
-{
-      o << setw(ind) << "" << "force " << lval_->name() << endl;
-      dump_node_pins(o, ind+4);
-}
-
 void NetMult::dump_node(ostream&o, unsigned ind) const
 {
      o << setw(ind) << "" << "LPM_MULT (NetMult): " << name() << endl;
@@ -239,6 +256,7 @@ void NetMult::dump_node(ostream&o, unsigned ind) const
 void NetMux::dump_node(ostream&o, unsigned ind) const
 {
      o << setw(ind) << "" << "Multiplexer (NetMux): " << name()
+	<< " width=" << width_ << " swidth=" << swidth_ << " size=" << size_
 	<< " scope=" << scope()->name() << endl;
      dump_node_pins(o, ind+4);
      dump_obj_attr(o, ind+4);
@@ -249,20 +267,24 @@ void NetBUFZ::dump_node(ostream&o, unsigned ind) const
      o << setw(ind) << "" << "NetBUFZ: " << name()
 	<< " scope=" << (scope()? scope()->name() : "")
 	<< " delay=(" << rise_time() << "," << fall_time() << "," <<
-	    decay_time() << ")" << endl;
+	    decay_time() << ") width=" << width() << endl;
      dump_node_pins(o, ind+4);
 }

 void NetCaseCmp::dump_node(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "case compare === : " << name() << endl;
+      if (eeq_)
+	    o << setw(ind) << "" << "case compare === : " << name() << endl;
+      else
+	    o << setw(ind) << "" << "case compare !== : " << name() << endl;
+
      dump_node_pins(o, ind+4);
 }

 void NetConst::dump_node(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "constant ";
-      for (unsigned idx = pin_count() ;  idx > 0 ;  idx -= 1)
+      o << setw(ind) << "" << "constant " << width_ << "'b";
+      for (unsigned idx = width_ ;  idx > 0 ;  idx -= 1)
 	    o << value_[idx-1];
      o << ": " << name() << endl;
      dump_node_pins(o, ind+4);
@@ -278,6 +300,13 @@ void NetFF::dump_node(ostream&o, unsigned ind) const
      dump_obj_attr(o, ind+4);
 }

+void NetLiteral::dump_node(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << "constant real " << real_
+	<< ": " << name() << endl;
+      dump_node_pins(o, ind+4);
+}
+
 void NetLogic::dump_node(ostream&o, unsigned ind) const
 {
      o << setw(ind) << "" << "logic: ";
@@ -353,6 +382,26 @@ void NetModulo::dump_node(ostream&o, unsigned ind) const
      dump_obj_attr(o, ind+4);
 }

+void NetPartSelect::dump_node(ostream&o, unsigned ind) const
+{
+      const char*pt = "";
+      switch (dir_) {
+	  case VP:
+	    pt = "VP";
+	    break;
+	  case PV:
+	    pt = "PV";
+	    break;
+	  case BI:
+	    pt = "BI";
+	    break;
+      }
+      o << setw(ind) << "" << "NetPartSelect(" << pt << "): "
+	<< name() << " off=" << off_ << " wid=" << wid_ <<endl;
+      dump_node_pins(o, ind+4);
+      dump_obj_attr(o, ind+4);
+}
+
 void NetRamDq::dump_node(ostream&o, unsigned ind) const
 {
      o << setw(ind) << "" << "LPM_RAM_DQ (" << mem_->name() << "): "
@@ -361,6 +410,65 @@ void NetRamDq::dump_node(ostream&o, unsigned ind) const
      dump_obj_attr(o, ind+4);
 }

+void NetReplicate::dump_node(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << "NetReplicate: "
+	<< name() << " wid=" << width_ << ", repeat_=" << repeat_
+	<< ", input wid=" << width_/repeat_ << endl;
+      dump_node_pins(o, ind+4);
+      dump_obj_attr(o, ind+4);
+}
+
+void NetSignExtend::dump_node(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << "NetSignExtend: "
+	<< name() << " output width=" << width_ << endl;
+      dump_node_pins(o, ind+4);
+      dump_obj_attr(o, ind+4);
+}
+
+void NetUReduce::dump_node(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << "reduction logic: ";
+      switch (type_) {
+	  case NONE:
+	    o << "NONE";
+	    break;
+	  case AND:
+	    o << "and";
+	    break;
+	  case OR:
+	    o << "or";
+	    break;
+	  case XOR:
+	    o << "xor";
+	    break;
+	  case NAND:
+	    o << "nand";
+	    break;
+	  case NOR:
+	    o << "nor";
+	    break;
+	  case XNOR:
+	    o << "xnor";
+	    break;
+      }
+      o << " #(" << rise_time()
+	<< "," << fall_time() << "," << decay_time() << ") " << name()
+	<< " scope=" << (scope()? scope()->name() : "")
+	<< endl;
+
+      dump_node_pins(o, ind+4);
+      dump_obj_attr(o, ind+4);
+}
+
+void NetSysFunc::dump_node(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << def_->name << "(...)" << endl;
+      dump_node_pins(o, ind+4);
+      dump_obj_attr(o, ind+4);
+}
+
 void NetUserFunc::dump_node(ostream&o, unsigned ind) const
 {
      o << setw(ind) << "" << def_->name() << "(";
@@ -436,8 +544,8 @@ void NetAssign_::dump_lval(ostream&o) const
 	    if (bmux_) {
 		  o << "[" << *bmux_ << "]";

-	    } else {
-		  o << "[" << (loff_+lwid_-1) << ":" << loff_ << "]";
+	    } else if (base_) {
+		  o << "[" << *base_ << " +: " << lwid_ << "]";
 	    }
      } else if (mem_) {
 	    // Is there an obvious way to flag memories in the dump
@@ -447,6 +555,10 @@ void NetAssign_::dump_lval(ostream&o) const
 	    if (bmux_) o << *bmux_;
 	      else     o << "**oops**";
 	    o << "]";
+
+	    if (base_) {
+		  o << "[" << *base_ << " +: " << lwid_ << "]";
+	    }
      } else {
 	    o << "";
      }
@@ -472,10 +584,10 @@ void NetAssign::dump(ostream&o, unsigned ind) const
      dump_lval(o);

      o << " = ";
-#if 0
-      if (l_val(0)->rise_time())
-	    o << "#" << l_val(0)->rise_time() << " ";
-#endif
+
+      if (const NetExpr*de = get_delay())
+	    o << "#(" << *de << ") ";
+
      o << *rval() << ";" << endl;
 }

@@ -485,14 +597,23 @@ void NetAssignNB::dump(ostream&o, unsigned ind) const
      dump_lval(o);

      o << " <= ";
-#if 0
-      if (l_val(0)->rise_time())
-	    o << "#" << l_val(0)->rise_time() << " ";
-#endif
+
+      if (const NetExpr*de = get_delay())
+	    o << "#(" << *de << ") ";
+
      o << *rval() << ";" << endl;

 }

+void NetAssignBase::dump(ostream&o, unsigned ind) const
+{
+      if (const NetAssignNB *n1 = dynamic_cast<const NetAssignNB*>(this)) {
+	    n1->dump(o,ind);
+      } else if (const NetAssign *n2 = dynamic_cast<const NetAssign*>(this)) {
+	    n2->dump(o,ind);
+      }
+}
+
 /* Dump a block statement */
 void NetBlock::dump(ostream&o, unsigned ind) const
 {
@@ -546,8 +667,9 @@ void NetCase::dump(ostream&o, unsigned ind) const

 void NetCAssign::dump(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "cassign " << lval_->name() << " = "
-	<< name() << ";" << endl;
+      o << setw(ind) << "" << "cassign ";
+      dump_lval(o);
+      o << " = " << *rval() << "; /* " << get_line() << " */" << endl;
 }

 void NetCondit::dump(ostream&o, unsigned ind) const
@@ -567,8 +689,9 @@ void NetCondit::dump(ostream&o, unsigned ind) const

 void NetDeassign::dump(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "deassign " << lval_->name() << "; "
-	<< "/* " << get_line() << " */" << endl;
+      o << setw(ind) << "" << "deassign ";
+      dump_lval(o);
+      o << "; /* " << get_line() << " */" << endl;
 }

 void NetDisable::dump(ostream&o, unsigned ind) const
@@ -621,8 +744,9 @@ void NetEvWait::dump(ostream&o, unsigned ind) const

 void NetForce::dump(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "force " << lval_->name() << " = "
-	<< name() << ";" << endl;
+      o << setw(ind) << "" << "force ";
+      dump_lval(o);
+      o << " = " << *rval() << "; /* " << get_line() << " */" << endl;
 }

 void NetForever::dump(ostream&o, unsigned ind) const
@@ -634,6 +758,9 @@ void NetForever::dump(ostream&o, unsigned ind) const
 void NetFuncDef::dump(ostream&o, unsigned ind) const
 {
      o << setw(ind) << "" << "function " << scope_->name() << endl;
+      if (result_sig_)
+	    o << setw(ind+2) << "" << "Return signal: "
+	      << result_sig_->name() << endl;
      if (statement_)
 	    statement_->dump(o, ind+2);
      else
@@ -659,12 +786,9 @@ void NetPDelay::dump(ostream&o, unsigned ind) const

 void NetRelease::dump(ostream&o, unsigned ind) const
 {
-      if (lval_)
-	    o << setw(ind) << "" << "release " << lval_->name() << "; "
-	      << "/* " << get_line() << " */" << endl;
-      else
-	    o << setw(ind) << "" << "release (null); "
-	      << "/* " << get_line() << " */" << endl;
+      o << setw(ind) << "" << "release ";
+      dump_lval(o);
+      o << "; /* " << get_line() << " */" << endl;
 }

 void NetRepeat::dump(ostream&o, unsigned ind) const
@@ -675,7 +799,9 @@ void NetRepeat::dump(ostream&o, unsigned ind) const

 void NetScope::dump(ostream&o) const
 {
+	/* This is a constructed hierarchical name. */
      o << name();
+
      switch (type_) {
 	  case BEGIN_END:
 	    o << " sequential block";
@@ -687,22 +813,29 @@ void NetScope::dump(ostream&o) const
 	    o << " function";
 	    break;
 	  case MODULE:
-	    o << " module <" << (module_name_? module_name_ : "") << ">";
+	    o << " module <" << (module_name_? module_name_.str() : "") << ">";
 	    break;
 	  case TASK:
 	    o << " task";
 	    break;
+	  case GENBLOCK:
+	    o << " generate block";
+	    break;
      }
      o << endl;

+      for (unsigned idx = 0 ;  idx < attr_cnt() ;  idx += 1)
+	    o << "    (* " << attr_key(idx) << " = "
+	      << attr_value(idx) << " *)" << endl;
+
      o << "    timescale = 10e" << time_unit() << " / 10e"
 	<< time_precision() << endl;

 	/* Dump the parameters for this scope. */
      {
-	    map<string,param_expr_t>::const_iterator pp;
-	    for (pp = parameters_.begin()
-		       ; pp != parameters_.end() ;  pp ++) {
+	    map<perm_string,param_expr_t>::const_iterator pp;
+	    for (pp = parameters.begin()
+		       ; pp != parameters.end() ;  pp ++) {
 		  o << "    parameter ";

 		  if ((*pp).second.signed_flag)
@@ -716,8 +849,8 @@ void NetScope::dump(ostream&o) const
 			*(*pp).second.expr << ";" << endl;
 	    }

-	    for (pp = localparams_.begin()
-		       ; pp != localparams_.end() ;  pp ++) {
+	    for (pp = localparams.begin()
+		       ; pp != localparams.end() ;  pp ++) {
 		  o << "    localparam " << (*pp).first << " = "  <<
 			*(*pp).second.expr << ";" << endl;
 	    }
@@ -759,11 +892,16 @@ void NetScope::dump(ostream&o) const

      switch (type_) {
 	  case FUNC:
-	    func_def()->dump(o, 4);
+	    if (func_def())
+		  func_def()->dump(o, 4);
+	    else
+		  o << "    MISSING FUNCTION DEFINITION" << endl;
 	    break;
 	  case TASK:
 	    task_def()->dump(o, 4);
 	    break;
+	  default:
+	    break;
      }

 	/* Dump any sub-scopes. */
@@ -808,7 +946,7 @@ void NetProc::dump(ostream&o, unsigned ind) const
      o << setw(ind) << "" << "// " << typeid(*this).name() << endl;
 }

-/* Dump an expression that noone wrote a dump method for. */
+/* Dump an expression that no one wrote a dump method for. */
 void NetExpr::dump(ostream&o) const
 {
      o << "(?" << typeid(*this).name() << "?)";
@@ -853,9 +991,15 @@ void NetEBinary::dump(ostream&o) const
 	  case 'O':
 	    o << "~|";
 	    break;
+	  case 'p':
+	    o << "**";
+	    break;
 	  case 'r':
 	    o << ">>";
 	    break;
+	  case 'R':
+	    o << ">>>";
+	    break;
 	  case 'X':
 	    o << "~^";
 	    break;
@@ -896,11 +1040,54 @@ void NetEConst::dump(ostream&o) const
 	    o << value_;
 }

+void NetEConstParam::dump(ostream&o) const
+{
+      o << "<" << name_ << "=";
+      NetEConst::dump(o);
+      o << ", wid=" << expr_width() << ">";
+}
+
+void NetECReal::dump(ostream&o) const
+{
+      o << value_;
+}
+
+void NetECRealParam::dump(ostream&o) const
+{
+      o << "<" << name_ << "=";
+      NetECReal::dump(o);
+      o << ">";
+}
+
+void NetEEvent::dump(ostream&o) const
+{
+      o << "<event=" << event_->name() << ">";
+}
+
 void NetEScope::dump(ostream&o) const
 {
      o << "<scope=" << scope_->name() << ">";
 }

+void NetESelect::dump(ostream&o) const
+{
+      o << "<select";
+      if (has_sign())
+	    o << "+=";
+      else
+	    o << "=";
+
+      expr_->dump(o);
+      o << "[";
+
+      if (base_)
+	    base_->dump(o);
+      else
+	    o << "(0)";
+
+      o << "+:" << expr_width() << "]>";
+}
+
 void NetESFunc::dump(ostream&o) const
 {
      o << name_ << "(";
@@ -915,15 +1102,7 @@ void NetESignal::dump(ostream&o) const
 {
      if (has_sign())
 	    o << "+";
-      o << name() << "[" << msi_<<":"<<lsi_ << "]";
-}
-
-void NetEBitSel::dump(ostream&o) const
-{
-      sig_->dump(o);
-      o << "[";
-      idx_->dump(o);
-      o << "]";
+      o << name() << "[" << msi()<<":"<<lsi() << "]";
 }

 void NetEMemory::dump(ostream&o) const
@@ -979,7 +1158,7 @@ void Design::dump(ostream&o) const
 {
      o << "DESIGN TIME PRECISION: 10e" << get_precision() << endl;
      o << "SCOPES:" << endl;
-      for (list<NetScope*>::const_iterator scope = root_scopes_.begin(); 
+      for (list<NetScope*>::const_iterator scope = root_scopes_.begin();
 	   scope != root_scopes_.end(); scope++)
 	    (*scope)->dump(o);

@@ -1004,6 +1183,117 @@ void Design::dump(ostream&o) const

 /*
 * $Log: design_dump.cc,v $
+ * Revision 1.167  2006/07/31 03:50:17  steve
+ *  Add support for power in constant expressions.
+ *
+ * Revision 1.166  2006/06/18 04:15:50  steve
+ *  Add support for system functions in continuous assignments.
+ *
+ * Revision 1.165  2006/04/10 00:37:42  steve
+ *  Add support for generate loops w/ wires and gates.
+ *
+ * Revision 1.164  2006/02/02 02:43:57  steve
+ *  Allow part selects of memory words in l-values.
+ *
+ * Revision 1.163  2005/08/27 04:32:08  steve
+ *  Handle synthesis of fully packed case statements.
+ *
+ * Revision 1.162  2005/07/11 16:56:50  steve
+ *  Remove NetVariable and ivl_variable_t structures.
+ *
+ * Revision 1.161  2005/07/07 16:22:49  steve
+ *  Generalize signals to carry types.
+ *
+ * Revision 1.160  2005/05/24 01:44:27  steve
+ *  Do sign extension of structuran nets.
+ *
+ * Revision 1.159  2005/05/17 20:56:55  steve
+ *  Parameters cannot have their width changed.
+ *
+ * Revision 1.158  2005/05/07 03:13:30  steve
+ *  Include delay expressions for assignments in dump.
+ *
+ * Revision 1.157  2005/03/09 05:52:03  steve
+ *  Handle case inequality in netlists.
+ *
+ * Revision 1.156  2005/02/08 00:12:36  steve
+ *  Add the NetRepeat node, and code generator support.
+ *
+ * Revision 1.155  2005/02/03 04:56:20  steve
+ *  laborate reduction gates into LPM_RED_ nodes.
+ *
+ * Revision 1.154  2005/01/24 05:28:30  steve
+ *  Remove the NetEBitSel and combine all bit/part select
+ *  behavior into the NetESelect node and IVL_EX_SELECT
+ *  ivl_target expression type.
+ *
+ * Revision 1.153  2005/01/22 18:16:00  steve
+ *  Remove obsolete NetSubnet class.
+ *
+ * Revision 1.152  2005/01/09 20:16:00  steve
+ *  Use PartSelect/PV and VP to handle part selects through ports.
+ *
+ * Revision 1.151  2004/12/29 23:55:43  steve
+ *  Unify elaboration of l-values for all proceedural assignments,
+ *  including assing, cassign and force.
+ *
+ *  Generate NetConcat devices for gate outputs that feed into a
+ *  vector results. Use this to hande gate arrays. Also let gate
+ *  arrays handle vectors of gates when the outputs allow for it.
+ *
+ * Revision 1.150  2004/12/11 02:31:25  steve
+ *  Rework of internals to carry vectors through nexus instead
+ *  of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ *  down this path.
+ *
+ * Revision 1.149  2004/10/04 01:10:52  steve
+ *  Clean up spurious trailing white space.
+ *
+ * Revision 1.148  2004/05/31 23:34:36  steve
+ *  Rewire/generalize parsing an elaboration of
+ *  function return values to allow for better
+ *  speed and more type support.
+ *
+ * Revision 1.147  2004/02/20 06:22:56  steve
+ *  parameter keys are per_strings.
+ *
+ * Revision 1.146  2004/02/18 17:11:54  steve
+ *  Use perm_strings for named langiage items.
+ *
+ * Revision 1.145  2003/12/17 16:52:39  steve
+ *  Debug dumps for synth2.
+ *
+ * Revision 1.144  2003/07/26 03:34:42  steve
+ *  Start handling pad of expressions in code generators.
+ *
+ * Revision 1.143  2003/07/05 20:42:08  steve
+ *  Fix some enumeration warnings.
+ *
+ * Revision 1.142  2003/06/20 00:53:19  steve
+ *  Module attributes from the parser
+ *  through to elaborated form.
+ *
+ * Revision 1.141  2003/06/18 03:55:18  steve
+ *  Add arithmetic shift operators.
+ *
+ * Revision 1.140  2003/05/30 02:55:32  steve
+ *  Support parameters in real expressions and
+ *  as real expressions, and fix multiply and
+ *  divide with real results.
+ *
+ * Revision 1.139  2003/04/22 04:48:29  steve
+ *  Support event names as expressions elements.
+ *
+ * Revision 1.138  2003/03/10 23:40:53  steve
+ *  Keep parameter constants for the ivl_target API.
+ *
+ * Revision 1.137  2003/01/27 05:09:17  steve
+ *  Spelling fixes.
+ *
+ * Revision 1.136  2003/01/26 21:15:58  steve
+ *  Rework expression parsing and elaboration to
+ *  accommodate real/realtime values and expressions.
+ *
 * Revision 1.135  2002/10/23 01:47:17  steve
 *  Fix synth2 handling of aset/aclr signals where
 *  flip-flops are split by begin-end blocks.
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: dosify.c,v 1.3 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: dosify.c,v 1.5 2003/07/15 16:17:47 steve Exp $"
 #endif

 /*
@@ -69,6 +69,12 @@ int main(int argc, char*argv[])

 /*
 * $Log: dosify.c,v $
+ * Revision 1.5  2003/07/15 16:17:47  steve
+ *  Fix spelling of ifdef.
+ *
+ * Revision 1.4  2003/07/15 03:49:22  steve
+ *  Spelling fixes.
+ *
 * Revision 1.3  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -0,0 +1,2 @@
+Makefile
+iverilog-vpi.exe
@@ -0,0 +1,80 @@
+#
+#    This source code is free software; you can redistribute it
+#    and/or modify it in source code form under the terms of the GNU
+#    Library General Public License as published by the Free Software
+#    Foundation; either version 2 of the License, or (at your option)
+#    any later version.
+#
+#    This program is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU Library General Public License for more details.
+#
+#    You should have received a copy of the GNU Library General Public
+#    License along with this program; if not, write to the Free
+#    Software Foundation, Inc.,
+#    59 Temple Place - Suite 330
+#    Boston, MA 02111-1307, USA
+#
+#ident "$Id: Makefile.in,v 1.7 2004/10/13 22:01:34 steve Exp $"
+#
+#
+SHELL = /bin/sh
+
+VERSION = 0.8
+
+prefix = @prefix@
+exec_prefix = @exec_prefix@
+srcdir = @srcdir@
+
+VPATH = $(srcdir)
+
+bindir = $(exec_prefix)/bin
+libdir = $(exec_prefix)/lib
+includedir = $(prefix)/include
+mandir = @mandir@
+
+dllib=@DLLIB@
+
+CC = @CC@
+INSTALL = @INSTALL@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_DATA = @INSTALL_DATA@
+
+CPPFLAGS = @ident_support@ -I. -I$(srcdir)/.. -DVERSION='"$(VERSION)"' @CPPFLAGS@ @DEFS@
+CFLAGS = -Wall @CFLAGS@
+LDFLAGS = @LDFLAGS@
+
+all: iverilog-vpi@EXEEXT@
+
+clean:
+	rm -f *.o
+	rm -f iverilog-vpi@EXEEXT@
+
+distclean: clean
+	rm -f Makefile
+
+O = main.o res.o
+
+iverilog-vpi@EXEEXT@: $O
+	$(CC) $(LDFLAGS) $O -o iverilog-vpi@EXEEXT@ @EXTRALIBS@
+
+
+main.o: main.c
+	$(CC) $(CPPFLAGS) $(CFLAGS) -c $(srcdir)/main.c
+
+# Windows specific...
+res.o: res.rc
+	windres -i res.rc -o res.o
+#
+
+install: all installdirs $(bindir)/iverilog-vpi@EXEEXT@
+
+$(bindir)/iverilog-vpi@EXEEXT@: ./iverilog-vpi@EXEEXT@
+	$(INSTALL_PROGRAM) ./iverilog-vpi@EXEEXT@ $(bindir)/iverilog-vpi@EXEEXT@
+
+installdirs: ../mkinstalldirs
+	$(srcdir)/../mkinstalldirs $(bindir)
+
+uninstall:
+	rm -f $(bindir)/iverilog-vpi@EXEEXT@
@@ -0,0 +1,565 @@
+/*
+ * Copyright (c) 2002 Gus Baldauf (gus@picturel.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+/*
+ *	iverilog-vpi.c
+ *
+ *	this program provides the functionality of iverilog-vpi.sh under Win32
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <windows.h>
+
+/* Macros used for compiling and linking */
+
+#define IVERILOG_VPI_CC        "gcc"				/* no .exe extension  */
+#define IVERILOG_VPI_CXX       "gcc"				/* no .exe extension  */
+#define IVERILOG_VPI_CFLAGS    "-O"					/* -I appended  later */
+#define IVERILOG_VPI_LD        "gcc"				/* no .exe extension  */
+#define IVERILOG_VPI_LDFLAGS   "-shared -Wl,--enable-auto-image-base"
+#define IVERILOG_VPI_LDLIBS    "-lveriuser -lvpi"	/* -L prepended later */
+
+/* pointers to global strings */
+
+static struct global_strings {
+	char *pCCSRC;		/* list of C source files */
+	char *pCXSRC;		/* list of C++ source files */
+	char *pOBJ;			/* list of object files */
+	char *pLIB;			/* list of library files */
+	char *pOUT;			/* output file name (.vpi extension), if 0 length then no source files specified */
+	char *pMINGW;		/* path to MinGW directory */
+	char *pIVL;			/* path to IVL directory */
+	char *pCFLAGS;		/* CFLAGS option */
+	char *pLDLIBS;		/* LDLIBS option */
+	char *pNewPath;		/* new PATH environment variable setting */
+} gstr;
+
+
+static void deInitDynString(char *str)
+{
+	free(str);
+}
+
+/* when finished, free allocated memory and return error code */
+
+static void myExit(int exitVal)
+{
+	deInitDynString(gstr.pCCSRC);
+	deInitDynString(gstr.pCXSRC);
+	deInitDynString(gstr.pOBJ);
+	deInitDynString(gstr.pLIB);
+	deInitDynString(gstr.pOUT);
+	deInitDynString(gstr.pMINGW);
+	deInitDynString(gstr.pIVL);
+	deInitDynString(gstr.pCFLAGS);
+	deInitDynString(gstr.pLDLIBS);
+	deInitDynString(gstr.pNewPath);
+
+	exit(exitVal);
+}
+
+/* display usage summary and exit */
+
+static void usage()
+{
+	fprintf(stderr,"usage: iverilog-vpi [--name=name] [-llibrary] [-mingw=dir] [-ivl=dir] sourcefile...\n");
+	fprintf(stderr,"   or  iverilog-vpi -mingw=dir\n");
+	fprintf(stderr,"   or  iverilog-vpi -ivl=dir\n");
+	myExit(1);
+}
+
+static void initDynString(char **str)
+{
+	*str = (char *) malloc(1);
+
+	if (!*str) {
+		fprintf(stderr,"error: out of memory\n");
+		myExit(4);
+	}
+
+	*str[0] = 0;
+}
+
+/* initialize dynamic memory buffers */
+
+static void init()
+{
+	initDynString(&gstr.pCCSRC);
+	initDynString(&gstr.pCXSRC);
+	initDynString(&gstr.pOBJ);
+	initDynString(&gstr.pLIB);
+	initDynString(&gstr.pOUT);
+	initDynString(&gstr.pMINGW);
+	initDynString(&gstr.pIVL);
+	initDynString(&gstr.pCFLAGS);
+	initDynString(&gstr.pLDLIBS);
+	initDynString(&gstr.pNewPath);
+}
+
+/* return true if "str" is terminated with with "end", case insensitive */
+
+static int endsIn (char *end, char *str)
+{
+	char *ext;
+
+	if (strlen(end) >= strlen(str))
+		return 0;
+
+	ext = str + (strlen(str) - strlen(end));
+
+	return stricmp(end,ext) ? 0 : 1;
+}
+
+/* return true if "str" begins with "prefix", case insensitive */
+
+static int startsWith (char *prefix, char *str)
+{
+	if (strlen(prefix) >= strlen(str))
+		return 0;
+
+	return strnicmp(prefix,str,strlen(prefix)) ? 0 : 1;
+}
+
+/* append "app" to "ptr", allocating memory as needed    */
+/*   if count is zero, then copy all characters of "app" */
+
+static void appendn (char **ptr, char *app, int count)
+{
+	*ptr = (char *) realloc(*ptr,strlen(*ptr)+(count?count:strlen(app))+1);
+
+	if (*ptr == NULL) {
+		fprintf(stderr,"error: out of memory\n");
+		myExit(4);
+	}
+
+	if (count)
+		strncat(*ptr,app,count);
+	else
+		strcat(*ptr,app);
+}
+
+/* append "app" to "ptr", allocating memory as needed    */
+
+static void append (char **ptr, char *app)
+{
+	appendn(ptr,app,0);
+}
+
+/* if the string does not end with a backslash, add one */
+
+static void appendBackSlash(char **str)
+{
+	if ((*str)[strlen(*str)-1] != '\\')
+		append(str,"\\");
+}
+
+/* copy count characters of "str" to "ptr", allocating memory as needed */
+/*   if count is zero, then copy all characters of "str"                */
+
+static void assignn (char **ptr, char *str, int count)
+{
+	*ptr = (char *) realloc(*ptr,(count?count:strlen(str))+1);
+
+	if (*ptr == NULL) {
+		fprintf(stderr,"error: out of memory\n");
+		myExit(4);
+	}
+
+	if (count) {
+		strncpy(*ptr,str,count);
+		(*ptr)[count] = 0;
+	}
+	else
+		strcpy(*ptr,str);
+}
+
+/* copy count characters of "str" to "ptr", allocating memory as needed */
+
+static void assign (char **ptr, char *str)
+{
+	assignn(ptr,str,0);
+}
+
+/* get a copy of a Icarus Verilog registry string key */
+
+static int GetRegistryKey(char *key, char **value)
+{
+	long lrv;
+	HKEY hkKey;
+	char *regKeyBuffer;
+	DWORD regKeyType, regKeySize;
+
+	lrv = RegOpenKeyEx(HKEY_LOCAL_MACHINE,"Software\\Icarus Verilog",0,KEY_QUERY_VALUE,&hkKey);
+	if (lrv != ERROR_SUCCESS)
+		return 0;
+
+	lrv = RegQueryValueEx(hkKey,key,NULL,&regKeyType,NULL,&regKeySize);
+	if ((lrv != ERROR_SUCCESS) || (regKeyType != REG_SZ) || (!regKeySize)) {
+		lrv = RegCloseKey(hkKey);
+		return 0;
+	}
+
+	regKeyBuffer = (char *) malloc(regKeySize+1);
+	if (!regKeyBuffer) {
+		lrv = RegCloseKey(hkKey);
+		fprintf(stderr,"error: out of memory\n");
+		myExit(4);
+	}
+	regKeyBuffer[regKeySize] = 0;		/* makes sure there is a trailing NULL */
+
+	lrv = RegQueryValueEx(hkKey,key,NULL,&regKeyType,regKeyBuffer,&regKeySize);
+	if ((lrv != ERROR_SUCCESS) || (regKeyType != REG_SZ) || (!regKeySize)) {
+		lrv = RegCloseKey(hkKey);
+		free(regKeyBuffer);
+		return 0;
+	}
+
+	RegCloseKey(hkKey);
+
+	assign(value,regKeyBuffer);
+	free(regKeyBuffer);
+
+	return 1;
+}
+
+/* store a copy of a Icarus Verilog registry string key */
+
+static void SetRegistryKey(char *key, char *value)
+{
+	HKEY hkKey;
+	DWORD res;
+
+	if (RegCreateKeyEx(
+		HKEY_LOCAL_MACHINE,
+		"Software\\Icarus Verilog",
+		0,
+		"",
+		REG_OPTION_NON_VOLATILE,
+		KEY_ALL_ACCESS,NULL,
+		&hkKey,
+		&res) != ERROR_SUCCESS)
+			return;
+
+	RegSetValueEx(hkKey,key,0,REG_SZ,value,strlen(value)+1);
+	RegCloseKey(hkKey);
+
+	printf("info:  storing %s in Windows' registry entry\n",value);
+	printf("       HKEY_LOCAL_MACHINE\\Software\\Icarus Verilog\\%s\n",key);
+}
+
+/* parse the command line, assign results to global variable strings */
+
+static int parse(int argc, char *argv[])
+{
+	int idx, srcFileCnt=0;
+
+	char dot_c_ext[]    = ".c";
+	char dot_cc_ext[]   = ".cc";
+	char dot_o_ext[]    = ".o";
+	char name_option[]  = "--name=";
+	char lib_option[]   = "-l";
+	char mingw_option[] = "-mingw=";
+	char ivl_option[]   = "-ivl=";
+
+	if (argc == 1)
+		return 0;
+
+	for (idx=1; idx<argc; ++idx) {
+		if (endsIn(dot_c_ext,argv[idx])) {				/* check for C source files */
+			++srcFileCnt;
+			append(&gstr.pCCSRC,argv[idx]);
+			append(&gstr.pCCSRC," ");
+			if (!*gstr.pOUT)
+			   assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_c_ext));
+		}
+		else if (endsIn(dot_cc_ext,argv[idx])) {		/* check for C++ source files */
+			++srcFileCnt;
+			append(&gstr.pCXSRC,argv[idx]);
+			append(&gstr.pCXSRC," ");
+			if (!*gstr.pOUT)
+			   assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_cc_ext));
+		}
+		else if (endsIn(dot_o_ext,argv[idx])) {			/* check for compiled object files */
+			++srcFileCnt;
+			append(&gstr.pOBJ,argv[idx]);
+			append(&gstr.pOBJ," ");
+			if (!*gstr.pOUT)
+			   assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_o_ext));
+		}
+		else if (startsWith(name_option,argv[idx])) {	/* check for --name option */
+			assignn(&gstr.pOUT,argv[idx]+sizeof(name_option)-1,strlen(argv[idx])-(sizeof(name_option)-1));
+		}
+		else if (startsWith(lib_option,argv[idx])) {	/* check for -l option */
+			append(&gstr.pLIB,argv[idx]);
+			append(&gstr.pLIB," ");
+		}
+		else if (startsWith(mingw_option,argv[idx]))	/* check for -mingw option */
+			assignn(&gstr.pMINGW,argv[idx]+sizeof(mingw_option)-1,strlen(argv[idx])-(sizeof(mingw_option)-1));
+		else if (startsWith(ivl_option,argv[idx]))		/* check for -ivl   option */
+			assignn(&gstr.pIVL,argv[idx]+sizeof(ivl_option)-1,strlen(argv[idx])-(sizeof(ivl_option)-1));
+		else
+			return 0;	/* different from iverilog-vpi.sh, we don't ignore accept arguments */
+	}
+
+	if (0 == srcFileCnt)
+		assign(&gstr.pOUT,"");				/* in case they used --name with no source files */
+
+	if (!*gstr.pOUT) {						/* normally it's an error if there are no *.c,*.cc,*.o files */
+		if (!*gstr.pMINGW && !*gstr.pIVL)	/* unless they are just setting the IVL or MinGW registry entries */
+			usage();
+	}
+	else {
+		append(&gstr.pOUT,".vpi");			/* the result file should have a .vpi extension */
+		append(&gstr.pOUT," ");
+	}
+
+	return 1;
+}
+
+/* do minimal check that the MinGW root directory looks valid */
+
+static void checkMingwDir(char *root)
+{
+	int irv;
+	struct _stat stat_buf;
+
+	char *path;
+	initDynString(&path);
+	assign(&path,gstr.pMINGW);
+	appendBackSlash(&path);
+	append(&path,"bin\\" IVERILOG_VPI_CC ".exe");
+
+	irv = _stat(path,&stat_buf);
+	deInitDynString(path);
+
+	if (irv) {
+		fprintf(stderr,"error: %s does not appear to be the valid root directory\n",root);
+		fprintf(stderr,"       of MinGW.  Use the -mingw option of iverilog-vpi.exe to\n");
+		fprintf(stderr,"       point to the MinGW root directory.  For a Windows command\n");
+		fprintf(stderr,"       shell the option would be something like -mingw=c:\\mingw\n");
+		fprintf(stderr,"       For a Cygwin shell the option would be something like\n");
+		fprintf(stderr,"       -mingw=c:\\\\mingw\n");
+		myExit(5);
+	}
+}
+
+/* do minimal check that the Icarus Verilog root directory looks valid */
+
+static void checkIvlDir(char *root)
+{
+	int irv;
+	struct _stat stat_buf;
+
+	char *path;
+	initDynString(&path);
+	assign(&path,gstr.pIVL);
+	appendBackSlash(&path);
+	append(&path,"bin\\vvp.exe");
+
+	irv = _stat(path,&stat_buf);
+	deInitDynString(path);
+
+	if (irv) {
+		fprintf(stderr,"error: %s does not appear to be the valid root directory of\n",root);
+		fprintf(stderr,"       Icarus Verilog.  Use the -ivl option of iverilog-vpi.exe to\n");
+		fprintf(stderr,"       point to the Icarus Verilog root directory.  For a Windows\n");
+		fprintf(stderr,"       command shell the option would be something like -ivl=c:\\iverilog\n");
+		fprintf(stderr,"       For a Cygwin shell the option would be something like\n");
+		fprintf(stderr,"       -ivl=c:\\\\iverilog\n");
+		myExit(6);
+	}
+}
+
+/* see if we can find mingw root */
+
+#define IVL_REGKEY_MINGW "MingwDir"
+
+static void setup_mingw_environment()
+{
+	char *pOldPATH = getenv("PATH");		/* get current path */
+
+	if (*gstr.pMINGW) {
+		checkMingwDir(gstr.pMINGW);
+		SetRegistryKey(IVL_REGKEY_MINGW,gstr.pMINGW);
+	}
+	else
+		if (!GetRegistryKey(IVL_REGKEY_MINGW,&gstr.pMINGW)) {
+			fprintf(stderr,"error: can not locate the MinGW root directory, use the -mingw option of\n");
+			fprintf(stderr,"       iverilog-vpi.exe to point to the MinGW root directory.  For\n");
+			fprintf(stderr,"       a Windows command shell the option would be something like\n");
+			fprintf(stderr,"       -mingw=c:\\mingw  For a Cygwin shell the option would be\n");
+			fprintf(stderr,"       something like -mingw=c:\\\\mingw\n");
+			myExit(5);
+		}
+
+	assign(&gstr.pNewPath,"PATH=");			/* create new path */
+	append(&gstr.pNewPath,gstr.pMINGW);
+	appendBackSlash(&gstr.pNewPath);
+	append(&gstr.pNewPath,"bin;");
+	append(&gstr.pNewPath,pOldPATH);
+
+	_putenv(gstr.pNewPath);					/* place new path in environment variable */
+}
+
+/* see if we can find iverilog root */
+
+#define IVL_REGKEY_IVL   "InstallDir"
+
+static void setup_ivl_environment()
+{
+	if (*gstr.pIVL) {
+		checkIvlDir(gstr.pIVL);
+		SetRegistryKey(IVL_REGKEY_IVL,gstr.pIVL);
+	}
+	else
+		if (!GetRegistryKey(IVL_REGKEY_IVL,&gstr.pIVL)) {
+			fprintf(stderr,"error: can not locate the Icarus Verilog root directory, use the -ivl option\n");
+			fprintf(stderr,"       of iverilog-vpi.exe to point to the Icarus Verilog root directory.\n");
+			fprintf(stderr,"       For a Windows command shell the option would be something like\n");
+			fprintf(stderr,"       -ivl=c:\\iverilog  For a Cygwin shell the option would be something\n");
+			fprintf(stderr,"       like -ivl=c:\\\\iverilog\n");
+			myExit(6);
+		}
+
+	/* build up the CFLAGS option string */
+
+	assign(&gstr.pCFLAGS,IVERILOG_VPI_CFLAGS);
+	append(&gstr.pCFLAGS," -I");
+	append(&gstr.pCFLAGS,gstr.pIVL);
+	appendBackSlash(&gstr.pCFLAGS);
+	append(&gstr.pCFLAGS,"include");
+
+	/* build up the LDFLAGS option string */
+
+	assign(&gstr.pLDLIBS,"-L");
+	append(&gstr.pLDLIBS,gstr.pIVL);
+	appendBackSlash(&gstr.pLDLIBS);
+	append(&gstr.pLDLIBS,"lib ");
+	append(&gstr.pLDLIBS,IVERILOG_VPI_LDLIBS);
+}
+
+/* compile source modules */
+
+static void compile(char *pSource, char **pObject, char *ext, int *compile_errors, char *compiler)
+{
+	char *ptr1 = pSource;
+	char *ptr2 = strchr(pSource,' ');
+	char *buf=0,*src=0,*obj=0;
+
+	while (ptr2) {
+		int len = ptr2 - ptr1;
+		assignn(&src,ptr1,len);
+
+		assignn(&obj,ptr1,len-strlen(ext));		/* strip off the extension */
+		append (&obj,".o");
+
+		assign (&buf,compiler);
+		append (&buf," -c -o ");
+		append (&buf,obj);
+		append (&buf," ");
+		append (&buf,gstr.pCFLAGS);
+		append (&buf," ");
+		append (&buf,src);
+
+		append (pObject,obj);
+		append (pObject," ");
+
+		printf("%s\n",buf);
+
+		if (system(buf))
+			++*compile_errors;
+
+		ptr1 = ptr2 + 1;					/* advance to next token */
+		ptr2 = strchr(ptr1,' ');
+	}
+
+	free(buf);
+	free(src);
+	free(obj);
+}
+
+/* using the global strings, compile and link */
+
+static void compile_and_link()
+{
+	char *buf=0;
+	int iRet, compile_errors = 0;
+
+	/* print out the mingw and ivl directories to help the user debug problems */
+
+	printf("info:  %s will be used as the MinGW root directory.\n",gstr.pMINGW);
+	checkMingwDir(gstr.pMINGW);
+
+	printf("info:  %s will be used as the Icarus Verilog root directory.\n",gstr.pIVL);
+	checkIvlDir(gstr.pIVL);
+
+	/* compile */
+
+	compile(gstr.pCCSRC,&gstr.pOBJ,".c" ,&compile_errors,IVERILOG_VPI_CC );		/* compile the C   source files */
+	compile(gstr.pCXSRC,&gstr.pOBJ,".cc",&compile_errors,IVERILOG_VPI_CXX);		/* compile the C++ source files */
+
+	if (compile_errors) {
+		fprintf(stderr,"iverilog-vpi: Some %d files failed to compile.\n",compile_errors);
+		myExit(2);
+	}
+
+	/* link */
+
+	assign(&buf,IVERILOG_VPI_LD);
+	append(&buf," -o ");
+	append(&buf,gstr.pOUT);				/* has a trailing space */
+	append(&buf,IVERILOG_VPI_LDFLAGS);
+	append(&buf," ");
+	append(&buf,gstr.pOBJ)				/* has a trailing space */;
+	append(&buf,gstr.pLIB);				/* has a trailing space */
+	append(&buf,gstr.pLDLIBS);
+
+	printf("%s\n",buf);
+
+	iRet = system(buf);
+
+	free(buf);
+
+	if (iRet)
+		myExit(3);
+}
+
+/* program execution starts here */
+
+int main(int argc, char *argv[])
+{
+	init();
+
+	if (!parse(argc,argv))
+		usage();
+
+	setup_mingw_environment();
+	setup_ivl_environment();
+
+	if (*gstr.pOUT)				/* are there any *.c,*.cc,*.o files specified */
+		compile_and_link();
+
+	myExit(0);
+}
@@ -0,0 +1,38 @@
+
+// LANGUAGE ENGLISH
+LANGUAGE 9, 4
+
+
+/////////////////////////////////////////////////////////////////////////////
+//
+// Version
+//
+
+1 VERSIONINFO
+ FILEVERSION 2002,11,13,0
+ PRODUCTVERSION 0,7,0,0
+ FILEFLAGSMASK 0x3fL
+ FILEFLAGS 0x2L
+ FILEOS 0x40004L
+ FILETYPE 0x2L
+ FILESUBTYPE 0x0L
+BEGIN
+    BLOCK "StringFileInfo"
+    BEGIN
+        BLOCK "040904b0"
+        BEGIN
+            VALUE "CompanyName", "Icarus Verilog\0"
+            VALUE "FileDescription", "Icarus Verilog VPI Tool\0"
+            VALUE "FileVersion", "2002, 11, 13, 0\0"
+            VALUE "InternalName", "iverilog-vpi\0"
+            VALUE "LegalCopyright", "Copyright 2002 Gus Baldauf\0"
+            VALUE "OriginalFilename", "iverilog-vpi.exe\0"
+            VALUE "ProductName", "Icarus Verilog\0"
+            VALUE "ProductVersion", "0, 7, 0, 0\0"
+        END
+    END
+    BLOCK "VarFileInfo"
+    BEGIN
+        VALUE "Translation", 0x409, 1200
+    END
+END
@@ -3,9 +3,7 @@
 #    and/or modify it in source code form under the terms of the GNU
 #    Library General Public License as published by the Free Software
 #    Foundation; either version 2 of the License, or (at your option)
-#    any later version. In order to redistribute the software in
-#    binary form, you will need a Picture Elements Binary Software
-#    License.
+#    any later version.
 #
 #    This program is distributed in the hope that it will be useful,
 #    but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -18,12 +16,12 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.15 2002/08/10 22:36:59 steve Exp $"
+#ident "$Id: Makefile.in,v 1.24 2004/10/13 22:01:34 steve Exp $"
 #
 #
 SHELL = /bin/sh

-VERSION = 0.6
+VERSION = 0.8

 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -39,14 +37,12 @@ mandir = @mandir@
 dllib=@DLLIB@

 CC = @CC@
-CXX = @CXX@
 INSTALL = @INSTALL@
 INSTALL_PROGRAM = @INSTALL_PROGRAM@
 INSTALL_DATA = @INSTALL_DATA@

-CPPFLAGS = @CPPFLAGS@ @DEFS@
-CFLAGS = @CFLAGS@ -I. -I$(srcdir)/.. -DVERSION='"$(VERSION)"'
-CXXFLAGS = @CXXFLAGS@ -I. -I$(srcdir)/..
+CPPFLAGS = @ident_support@ -I. -I.. -I$(srcdir)/.. -I$(srcdir) -DVERSION='"$(VERSION)"' @CPPFLAGS@ @DEFS@
+CFLAGS = -Wall @CFLAGS@
 LDFLAGS = @LDFLAGS@

 all: iverilog@EXEEXT@
@@ -54,18 +50,16 @@ all: iverilog@EXEEXT@
 clean:
 	rm -f *.o lexor.c parse.c parse.h parse.output
 	rm -f cflexor.c cfparse.c cfparse.h cfparse.output
+	rm -f iverilog@EXEEXT@

-O = main.o build_string.o lexor.o parse.o substit.o cflexor.o cfparse.o
+distclean: clean
+	rm -f Makefile
+
+O = main.o substit.o cflexor.o cfparse.o

 iverilog@EXEEXT@: $O
 	$(CC) $(LDFLAGS) $O -o iverilog@EXEEXT@ @EXTRALIBS@

-lexor.c: lexor.lex
-	flex -s -olexor.c $(srcdir)/lexor.lex
-
-parse.h parse.c: parse.y
-	bison --verbose -t -d -o parse.c $(srcdir)/parse.y
-
 cflexor.c: cflexor.lex
 	flex -s -Pcf -ocflexor.c $(srcdir)/cflexor.lex

@@ -74,11 +68,9 @@ cfparse.h cfparse.c: cfparse.y


 main.o: main.c globals.h
-	$(CC) $(CFLAGS) -c -DCXX='"@CXX@"' -DIVL_ROOT='"@libdir@/ivl"'  -DIVL_INC='"@includedir@"' -DIVL_LIB='"@libdir@"' -DDLLIB='"@DLLIB@"' $(srcdir)/main.c
+	$(CC) $(CPPFLAGS) $(CFLAGS) -c -DIVL_ROOT='"@libdir@/ivl"'  -DIVL_INC='"@includedir@"' -DIVL_LIB='"@libdir@"' -DDLLIB='"@DLLIB@"' $(srcdir)/main.c

 build_string.o: build_string.c globals.h
-lexor.o: lexor.c parse.h globals.h
-parse.o: parse.c globals.h
 cflexor.o: cflexor.c cfparse.h cfparse_misc.h globals.h
 cfparse.o: cfparse.c globals.h cfparse_misc.h

@@ -89,8 +81,8 @@ iverilog.pdf: iverilog.ps
 	ps2pdf iverilog.ps iverilog.pdf

 ifeq (@WIN32@,yes)
-INSTALL_DOC = $(prefix)/iverilog.pdf
-INSTALL_DOCDIR =
+INSTALL_DOC = $(prefix)/iverilog.pdf $(mandir)/man1/iverilog.1
+INSTALL_DOCDIR = $(mandir)/man1
 all: iverilog.pdf
 else
 INSTALL_DOC = $(mandir)/man1/iverilog.1
@@ -1,205 +0,0 @@
-/*
- * Copyright (c) 2000 Stephen Williams (steve@picturel.com)
- *
- *    This source code is free software; you can redistribute it
- *    and/or modify it in source code form under the terms of the GNU
- *    General Public License as published by the Free Software
- *    Foundation; either version 2 of the License, or (at your option)
- *    any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-#ifdef HAVE_CVS_IDENT
-#ident "$Id: build_string.c,v 1.11 2002/08/12 01:35:01 steve Exp $"
-#endif
-
-# include "config.h"
-
-# include  "globals.h"
-# include  <string.h>
-# include  <assert.h>
-
-int build_string(char*output, size_t olen, const char*pattern)
-{
-      char tmp_buf[1024];
-
-      char*output_save = output;
-      while (*pattern) {
-
-	    if (*pattern == '%') {
-		  pattern += 1;
-		  switch (*pattern) {
-		      case 0:
-			break;
-
-		      case '%':
-			*output++ = '%';
-			break;
-
-		      case '[': {
-			    const char*tail;
-			    pattern += 1;
-			    assert(*pattern);
-			    tail = strchr(pattern+1, ']');
-			    assert(tail);
-			    strncpy(tmp_buf, pattern+1, tail-pattern-1);
-			    tmp_buf[tail-pattern-1] = 0;
-
-			    if (((*pattern == 's') && start)
-				|| ((*pattern == 'v') && verbose_flag)
-				|| ((*pattern == 'M') && depfile)
-				|| ((*pattern == 'N') && npath)
-				|| ((*pattern == 'T') && mtm)) {
-				  int rc = build_string(output, olen,
-							tmp_buf);
-				  output += rc;
-				  olen -= rc;
-			    }
-			    pattern = tail;
-			    break;
-		      }
-
-		      case 'B':
-			strcpy(output, base);
-			output += strlen(base);
-			olen -= strlen(base);
-			break;
-
-		      case 'C':
-			strcpy(output, iconfig_path);
-			output += strlen(iconfig_path);
-			olen -= strlen(iconfig_path);
-			break;
-
-		      case 'g':
-			strcpy(output, generation);
-			output += strlen(generation);
-			olen -= strlen(generation);
-			break;
-
-		      case 'f':
-			if (f_list) {
-			      strcpy(output, f_list);
-			      output += strlen(f_list);
-			      olen -= strlen(f_list);
-			}
-			break;
-
-		      case 'm':
-			if (mod_list) {
-			      strcpy(output, mod_list);
-			      output += strlen(mod_list);
-			      olen -= strlen(mod_list);
-			}
-			break;
-
-		      case 'M':
-			if (depfile) {
-			      strcpy(output, depfile);
-			      output += strlen(depfile);
-			      olen -= strlen(depfile);
-			}
-			break;
-
-		      case 'N':
-			if (npath) {
-			      strcpy(output, npath);
-			      output += strlen(npath);
-			      olen -= strlen(npath);
-			}
-			break;
-
-		      case 'o':
-			strcpy(output, opath);
-			output += strlen(opath);
-			olen -= strlen(opath);
-			break;
-
-		      case 's':
-			if (start) {
-			      strcpy(output, start);
-			      output += strlen(start);
-			      olen -= strlen(start);
-			}
-			break;
-
-		      case 'T':
-			if (mtm) {
-			      strcpy(output, mtm);
-			      output += strlen(mtm);
-			      olen -= strlen(mtm);
-			}
-			break;
-
-		      case 't':
-			strcpy(output, targ);
-			output += strlen(targ);
-			olen -= strlen(targ);
-			break;
-
-		      case 'W':
-			strcpy(output, warning_flags);
-			output += strlen(warning_flags);
-			olen -= strlen(warning_flags);
-			break;
-
-		  }
-		  pattern += 1;
-
-	    } else {
-		  *output++ = *pattern++;
-		  olen -= 1;
-	    }
-      }
-
-      *output = 0;
-      return output-output_save;
-}
-
-/*
- * $Log: build_string.c,v $
- * Revision 1.11  2002/08/12 01:35:01  steve
- *  conditional ident string using autoconfig.
- *
- * Revision 1.10  2002/05/28 02:25:03  steve
- *  Pass library paths through -Cfile instead of command line.
- *
- * Revision 1.9  2002/05/28 00:50:39  steve
- *  Add the ivl -C flag for bulk configuration
- *  from the driver, and use that to run library
- *  modules through the preprocessor.
- *
- * Revision 1.8  2002/05/24 01:13:00  steve
- *  Support language generation flag -g.
- *
- * Revision 1.7  2002/04/04 05:26:13  steve
- *  Add dependency generation.
- *
- * Revision 1.6  2001/11/16 05:07:19  steve
- *  Add support for +libext+ in command files.
- *
- * Revision 1.5  2001/10/20 23:02:40  steve
- *  Add automatic module libraries.
- *
- * Revision 1.4  2001/07/25 03:10:50  steve
- *  Create a config.h.in file to hold all the config
- *  junk, and support gcc 3.0. (Stephan Boettcher)
- *
- * Revision 1.3  2001/07/03 04:09:25  steve
- *  Generate verbuse status messages (Stephan Boettcher)
- *
- * Revision 1.2  2000/10/28 03:45:47  steve
- *  Use the conf file to generate the vvm ivl string.
- *
- * Revision 1.1  2000/10/08 22:36:56  steve
- *  iverilog with an iverilog.conf configuration file.
- *
- */
-
@@ -18,8 +18,8 @@
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: cflexor.lex,v 1.6 2002/05/28 20:40:37 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: cflexor.lex,v 1.8 2004/10/04 01:10:56 steve Exp $"
 #endif

 # include  "cfparse.h"
@@ -113,10 +113,10 @@ static int comment_enter;
     is a little bit tricky, as we don't want to mistake a comment for
     a string word. */
 "/"[^\*\/].* { cflval.text = strdup(yytext);
-               return TOK_STRING; } 
+               return TOK_STRING; }

 [^/\n \t\b\r+-].* { cflval.text = strdup(yytext);
-                   return TOK_STRING; } 
+                   return TOK_STRING; }

  /* Fallback match. */
 . { return yytext[0]; }
@@ -17,14 +17,17 @@
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: cfparse.y,v 1.8 2002/06/23 20:10:51 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: cfparse.y,v 1.10 2003/09/26 21:25:58 steve Exp $"
 #endif


 # include  "globals.h"
 # include  "cfparse_misc.h"
 # include  <ctype.h>
+# include  <stdlib.h>
+# include  <string.h>
+

 /*
 * This flag is set to 0, 1 or 2 if file names are to be translated to
@@ -207,4 +210,5 @@ skip_arg : TOK_PLUSARG

 int yyerror(const char*msg)
 {
+	return 0;
 }
@@ -20,7 +20,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: cfparse_misc.h,v 1.4 2002/08/12 01:35:01 steve Exp $"
+#ident "$Id: cfparse_misc.h,v 1.6 2004/02/15 18:03:30 steve Exp $"
 #endif

 /*
@@ -38,8 +38,18 @@ struct cfltype {
 # define YYLTYPE struct cfltype
 extern YYLTYPE yylloc;

+int cflex(void);
+int cferror(const char *);
+int cfparse(void);
+
 /*
 * $Log: cfparse_misc.h,v $
+ * Revision 1.6  2004/02/15 18:03:30  steve
+ *  Cleanup of warnings.
+ *
+ * Revision 1.5  2003/09/26 21:25:58  steve
+ *  Warnings cleanup.
+ *
 * Revision 1.4  2002/08/12 01:35:01  steve
 *  conditional ident string using autoconfig.
 *
@@ -19,7 +19,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: globals.h,v 1.16 2002/08/12 01:35:01 steve Exp $"
+#ident "$Id: globals.h,v 1.19 2003/11/18 06:31:46 steve Exp $"
 #endif

 # include  <stddef.h>
@@ -29,15 +29,7 @@ extern const char*base;

  /* This is the path to the iconfig file sent to ivl. */
 extern char* iconfig_path;
-
-  /* This is a list of all the -f<key>=<value> options from the
-     command line, concatenated together. */
-extern char*f_list;
-
-extern char*mod_list;
-
-  /* This is the optional -Tmin|typ|max setting. */
-extern const char*mtm;
+extern char* iconfig_common_path;

  /* Ths is the optional -M<dependfile> value, if one was supplied. */
 extern const char*depfile;
@@ -57,9 +49,6 @@ extern int synth_flag;
  /* This is the name of the selected target. */
 extern const char*targ;

-  /* This is the language generation flag. */
-extern const char*generation;
-
  /* Perform variable substitutions on the string. */
 extern char* substitutions(const char*str);

@@ -86,12 +75,17 @@ extern char warning_flags[];
 extern char* library_flags;
 extern char* library_flags2;

-extern const char*lookup_pattern(const char*key);
-
-extern int build_string(char*out, size_t olen, const char*pattern);
-
 /*
 * $Log: globals.h,v $
+ * Revision 1.19  2003/11/18 06:31:46  steve
+ *  Remove the iverilog.conf file.
+ *
+ * Revision 1.18  2003/11/13 04:09:49  steve
+ *  Pass flags through the temporary config file.
+ *
+ * Revision 1.17  2003/11/01 04:21:57  steve
+ *  Add support for a target static config file.
+ *
 * Revision 1.16  2002/08/12 01:35:01  steve
 *  conditional ident string using autoconfig.
 *
@@ -106,44 +100,5 @@ extern int build_string(char*out, size_t olen, const char*pattern);
 *  Add the ivl -C flag for bulk configuration
 *  from the driver, and use that to run library
 *  modules through the preprocessor.
- *
- * Revision 1.12  2002/05/24 01:13:00  steve
- *  Support language generation flag -g.
- *
- * Revision 1.11  2002/04/04 05:26:13  steve
- *  Add dependency generation.
- *
- * Revision 1.10  2001/11/16 05:07:19  steve
- *  Add support for +libext+ in command files.
- *
- * Revision 1.9  2001/11/13 03:30:26  steve
- *  The +incdir+ plusarg can take multiple directores,
- *  and add initial support for +define+ in the command file.
- *
- * Revision 1.8  2001/11/12 18:47:32  steve
- *  Support +incdir in command files, and ignore other
- *  +args flags. Also ignore -a and -v flags.
- *
- * Revision 1.7  2001/11/12 01:26:36  steve
- *  More sophisticated command file parser.
- *
- * Revision 1.6  2001/10/23 00:37:30  steve
- *  The -s flag can now be repeated on the iverilog command.
- *
- * Revision 1.5  2001/10/20 23:02:40  steve
- *  Add automatic module libraries.
- *
- * Revision 1.4  2001/07/03 04:09:25  steve
- *  Generate verbuse status messages (Stephan Boettcher)
- *
- * Revision 1.3  2000/11/09 21:58:00  steve
- *  Remember to include the -S condition.
- *
- * Revision 1.2  2000/10/28 03:45:47  steve
- *  Use the conf file to generate the vvm ivl string.
- *
- * Revision 1.1  2000/10/08 22:36:56  steve
- *  iverilog with an iverilog.conf configuration file.
- *
 */
 #endif
@@ -1,10 +1,10 @@
-.TH iverilog 1 "$Date: 2002/06/23 20:10:51 $" Version "$Date: 2002/06/23 20:10:51 $"
+.TH iverilog 1 "$Date: 2005/06/28 04:25:55 $" Version "$Date: 2005/06/28 04:25:55 $"
 .SH NAME
 iverilog - Icarus Verilog compiler

 .SH SYNOPSIS
 .B iverilog
-[-ESVv] [-Cpath] [-ccmdfile] [-g1|-g2|-g3.0] [-Dmacro[=defn]] [-pflag=value]
+[-ESVv] [-Bpath] [-ccmdfile] [-g1|-g2|-g2x] [-Dmacro[=defn]] [-pflag=value]
 [-Iincludedir] [-mmodule] [-Mfile] [-Nfile] [-ooutputfilename]
 [-stopmodule] [-ttype] [-Tmin/typ/max] [-Wclass] [-ypath] sourcefile

@@ -21,11 +21,12 @@ types are added as code generators are implemented.
 \fIiverilog\fP accepts the following options:
 .TP 8
 .B -B\fIbase\fP
-The \fIiverilog\fP program uses external programs to preprocess and
-compile the Verilog source. Normally, the path used to locate these
-tools is built into the \fIiverilog\fP program. However, the \fB-B\fP
-switch allows the user to select a different set of programs. The path
-given is used to locate \fIivlpp\fP, \fIivl\fP and the VPI modules.
+The \fIiverilog\fP program uses external programs and configuration
+files to preprocess and compile the Verilog source. Normally, the path
+used to locate these tools is built into the \fIiverilog\fP
+program. However, the \fB-B\fP switch allows the user to select a
+different set of programs. The path given is used to locate
+\fIivlpp\fP, \fIivl\fP, code generators and the VPI modules.
 .TP 8
 .B -c\fIfile\fP
 This flag specifies an input file that contains a list of Verilog
@@ -33,14 +34,6 @@ source files. This is similar to the \fIcommand file\fP of other
 Verilog simulators, in that it is a file that contains the file names
 instead of taking them on the command line. See \fBCommand Files\fP below.
 .TP 8
-.B -C\fIpath\fP
-This flag selects the driver configuration file to use. Normally, the
-iverilog program will read its configuration file from
-/usr/lib/ivl/iverilog.conf (or the install path configured at compile
-time) but the user can specify the path to a different configuration
-file. This is useful when testing new configuration files. See the
-installed configuration file for a summary of the file format.
-.TP 8
 .B -D\fImacro\fP
 Defines macro \fImacro\fP with the string `1' as its definition. This
 form is normally only used to trigger ifdef conditionals in the
@@ -55,16 +48,16 @@ is the Verilog input, but with file inclusions and macro references
 expanded and removed. This is useful, for example, to preprocess
 Verilog source for use by other compilers.
 .TP 8
-.B -g1\fI|\fP-g2\fI|\fP-g3.0
+.B -g1\fI|\fP-g2\fI|\fP-g2x
 Select the Verilog language \fIgeneration\fP to support in the
 compiler. This selects between \fIIEEE1364-1995\fP(1),
-\fIIEEE1364-2001\fP(2), or \fISystemVerilog 3.0\fP(3.0). Normally,
+\fIIEEE1364-2001\fP(2), or \fIVerilog with extension\fP(2x). Normally,
 Icarus Verilog defaults to the latest known generation of the
 language. This flag is most useful to restrict the language to a set
 supported by tools of specific generations, for compatibility with
 other tools.
 .TP 8
-.B -I\fIincludedir\fP 
+.B -I\fIincludedir\fP
 Append directory \fIincludedir\fP to list of directories searched
 for Verilog include files. The \fB-I\fP switch may be used many times
 to specify several directories to search, the directories are searched
@@ -127,7 +120,11 @@ Use this switch to specify the target output format. See the
 Turn on verbose messages. This will print the command lines that are
 executed to perform the actual compilation, along with version
 information from the various components, as well as the version of the
-product as a whole.
+product as a whole.  You will notice that the command lines include
+a reference to a key temporary file that passes information to the
+compiler proper.  To keep that file from being deleted at the end
+of the process, provide a file name of your own in the environment
+variable \fBIVERILOG_ICONFIG\fP.
 .TP 8
 .B -V
 Print the version of the compiler, and exit.
@@ -175,14 +172,15 @@ but must be run by the \fBvvp\fP command.
 .TP 8
 .B xnf
 This is the Xilinx Netlist Format used by many tools for placing
-devices in FPGAs or other programmable devices. The Icarus Verilog XNF
-code generator can generate complete designs or XNF macros that can be
-imported into larger designs by other tools. (This target is obsolete,
-use the \fBfpga\fP target instead.)
+devices in FPGAs or other programmable devices. This target is
+obsolete, use the \fBfpga\fP target instead.
 .TP 8
 .B fpga
 This is a synthesis target that supports a variety of fpga devices,
-mostly by EDIF format output.
+mostly by EDIF format output. The Icarus Verilog fpga code generator
+can generate complete designs or EDIF macros that can in turn be
+imported into larger designs by other tools. The \fBfpga\fP target
+implies the synthesis \fB-S\fP flag.

 .SH "WARNING TYPES"
 These are the types of warnings that can be selected by the \fB-W\fP
@@ -200,6 +198,12 @@ This enables warnings for creation of implicit declarations. For
 example, if a scalar wire X is used but not declared in the Verilog
 source, this will print a warning at its first use.

+.TP 8
+.B portbind
+This enables warnings for ports of module instantiations that are not
+connected but probably should be. Dangling input ports, for example,
+will generate a warning.
+
 .TP 8
 .B timescale
 This enables warnings for inconsistent use of the timescale
@@ -208,6 +212,33 @@ inherit timescale from another file. Both probably mean that
 timescales are inconsistent, and simulation timing can be confusing
 and dependent on compilation order.

+.SH "SYSTEM FUNCTION TABLE FILES"
+If the source file name as a \fB.sft\fP suffix, then it is taken to be
+a system function table file. A System function table file is used to
+describe to the compiler the return types for system functions. This
+is necessary because the compiler needs this information to elaborate
+expressions that contain these system functions, but cannot run the
+sizetf functions since it has no run-time.
+
+The format of the table is ASCII, one function per line. Empty lines
+are ignored, and lines that start with the '\fI#\fP' character are
+comment lines. Each non-comment line starts with the function name,
+then the vpi type (i.e. vpiSysFuncReal). The following types are
+supported:
+
+.TP 8
+.B vpiSysFuncReal
+The function returns a real/realtime value.
+
+.TP 8
+.B vpiSysFuncInt
+The function returns an integer.
+
+.TP 8
+.B vpiSysFuncSized <wid> <signed|unsigned>
+The function returns a vector with the given width, and is signed or
+unsigned according to the flag.
+
 .SH "COMMAND FILES"
 The command file allows the user to place source file names and
 certain command line switches into a text file instead of on a long
@@ -285,7 +316,7 @@ and directory strings.
 Variable values come from the operating system environment, and not
 from preprocessor defines elsewhere in the file or the command line.

-.SH EXAMPLES 
+.SH EXAMPLES
 These examples assume that you have a Verilog source file called hello.v in
 the current directory

@@ -318,5 +349,5 @@ vvp(1),
 .nf
 Copyright \(co  2002 Stephen Williams

-This document can be freely redistributed according to the terms of the 
+This document can be freely redistributed according to the terms of the
 GNU General Public License version 2.0
@@ -1,80 +0,0 @@
-
-%{
-/*
- * Copyright (c) 2000 Stephen Williams ([email protected])
- *
- *    This source code is free software; you can redistribute it
- *    and/or modify it in source code form under the terms of the GNU
- *    General Public License as published by the Free Software
- *    Foundation; either version 2 of the License, or (at your option)
- *    any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: lexor.lex,v 1.5 2001/07/25 03:10:50 steve Exp $"
-#endif
-
-# include "config.h"
-
-# include  <string.h>
-# include  "parse.h"
-
-%}
-
-%x CTOKENS
-%x PATTERN
-
-%%
-
-"#".* { /* eat comments */; }
-
-"\n" { /* eat line-ends */; }
-"\r" { /* eat line-ends */; }
-
-"[" { BEGIN(CTOKENS); return '['; }
-
-<CTOKENS>"]" { BEGIN(0); return ']'; }
-
-<CTOKENS>[ \t\b]+ { /* skip white space */; }
-
-<CTOKENS>"-S" { return CT_S; }
-
-<CTOKENS>"-t"[a-zA-Z0-9\-_]+ {
-      yylval.text = strdup(yytext+2);
-      return CT_t; }
-
-"<"[^>]*">" {
-      BEGIN(PATTERN);
-      yylval.text = strdup(yytext);
-      return PATTERN_NAME; }
-
-<PATTERN>.* {
-      BEGIN(0);
-	/* Trim off a trailing \r. This is an issue in the DOS world. */
-      if (yytext[strlen(yytext)-1] == '\r')
-	    yytext[strlen(yytext)-1] = 0;
-
-      yylval.text = strdup(yytext);
-      return PATTERN_TEXT; }
-
-. { fprintf(stderr, "driver lexor: Unmatched character: %c\n", yytext[0]); }
-
-%%
-
-void reset_lexor(FILE*fd)
-{
-      yyrestart(fd);
-}
-
-int yywrap()
-{
-      return 1;
-}
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000-2001 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2005 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -16,13 +16,30 @@
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
-#ident "$Id: main.c,v 1.47 2002/08/12 01:27:48 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: main.c,v 1.69 2006/07/26 00:11:40 steve Exp $"
+#endif

 # include "config.h"

+const char NOTICE[] =
+"  This program is free software; you can redistribute it and/or modify\n"
+"  it under the terms of the GNU General Public License as published by\n"
+"  the Free Software Foundation; either version 2 of the License, or\n"
+"  (at your option) any later version.\n"
+"\n"
+"  This program is distributed in the hope that it will be useful,\n"
+"  but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
+"  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n"
+"  GNU General Public License for more details.\n"
+"\n"
+"  You should have received a copy of the GNU General Public License\n"
+"  along with this program; if not, write to the Free Software\n"
+"  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA\n"
+;

 const char HELP[] =
-"Usage: iverilog [-ESvV] [-B base] [-C path] [-c cmdfile] [-g1|-g2|-g3.0]\n"
+"Usage: iverilog [-ESvV] [-B base] [-c cmdfile] [-g1|-g2|-g2x]\n"
 "                [-D macro[=defn]] [-I includedir] [-M depfile] [-m module]\n"
 "                [-N file] [-o filename] [-p flag=value]\n"
 "                [-s topmodule] [-t target] [-T min|typ|max]\n"
@@ -44,8 +61,10 @@ const char HELP[] =

 #ifdef __MINGW32__
 #include <windows.h>
+#ifdef HAVE_LIBIBERTY_H
 #include <libiberty.h>
 #endif
+#endif

 #if HAVE_GETOPT_H
 #include <getopt.h>
@@ -70,6 +89,7 @@ extern const char*optarg;
 #endif

 # include  "globals.h"
+#include "cfparse_misc.h"   /* cfparse() */

 #ifdef __MINGW32__
 const char sep = '\\';
@@ -80,23 +100,19 @@ const char sep = '/';
 extern void cfreset(FILE*fd, const char*path);

 const char*base = 0;
+const char*pbase = 0;
 const char*mtm  = 0;
 const char*opath = "a.out";
 const char*npath = 0;
 const char*targ  = "vvp";
 const char*depfile = 0;

-const char*generation = "-g3.0";
+const char*generation = "2x";

 char warning_flags[16] = "";

-char*inc_list = 0;
-char*def_list = 0;
 char*mod_list = 0;
 char*command_filename = 0;
-char*start = 0;
-
-char*f_list = 0;

 /* These are used to collect the list of file names that will be
   passed to ivlpp. Keep the list in a file because it can be a long
@@ -105,9 +121,15 @@ char*source_path = 0;
 FILE*source_file = 0;
 unsigned source_count = 0;

+char*defines_path = 0;
+FILE*defines_file = 0;
+
 char*iconfig_path = 0;
 FILE*iconfig_file = 0;

+static char iconfig_common_path_buf[4096] = "";
+char*iconfig_common_path = iconfig_common_path_buf;
+
 int synth_flag = 0;
 int verbose_flag = 0;
 int command_file = 0;
@@ -119,6 +141,35 @@ char tmp[MAXSIZE];

 static char ivl_root[MAXSIZE];

+#ifdef __MINGW32__
+# include  <io.h>
+# include  <fcntl.h>
+static FILE*fopen_safe(const char*path)
+{
+      FILE*file = 0;
+      int fd;
+
+      fd = _open(path, _O_WRONLY|_O_CREAT|_O_EXCL, 0700);
+      if (fd != -1)
+	    file = _fdopen(fd, "w");
+
+       return file;
+}
+#else
+# include  <fcntl.h>
+static FILE*fopen_safe(const char*path)
+{
+      FILE*file = 0;
+      int fd;
+
+      fd = open(path, O_WRONLY|O_CREAT|O_EXCL, 0700);
+      if (fd != -1)
+	    file = fdopen(fd, "w");
+
+       return file;
+}
+#endif
+
 static const char*my_tempfile(const char*str, FILE**fout)
 {
      FILE*file;
@@ -148,7 +199,7 @@ static const char*my_tempfile(const char*str, FILE**fout)
      while ((retry > 0) && (file == NULL)) {
 	    unsigned code = rand();
 	    sprintf(pathbuf, "%s%c%s%04x", tmpdir, sep, str, code);
-	    file = fopen(pathbuf, "w");
+	    file = fopen_safe(pathbuf);
 	    retry -= 1;
      }

@@ -163,32 +214,55 @@ static const char*my_tempfile(const char*str, FILE**fout)
 */
 static int t_default(char*cmd, unsigned ncmd)
 {
-      int rc;
-      const char*pattern;
+      unsigned rc;
+#ifdef __MINGW32__
+      unsigned ncmd_start = ncmd;
+#endif

-      pattern = lookup_pattern("<ivl>");
-      if (pattern == 0) {
-	    fprintf(stderr, "No such target: %s\n", targ);
-	    return -1;
+      snprintf(tmp, sizeof tmp, " | %s/ivl", base);
+      rc = strlen(tmp);
+      cmd = realloc(cmd, ncmd+rc+1);
+      strcpy(cmd+ncmd, tmp);
+      ncmd += rc;
+
+      if (verbose_flag) {
+	    const char*vv = " -v";
+	    rc = strlen(vv);
+	    cmd = realloc(cmd, ncmd+rc+1);
+	    strcpy(cmd+ncmd, vv);
+	    ncmd += rc;
      }

-      tmp[0] = ' ';
-      tmp[1] = '|';
-      tmp[2] = ' ';
-      rc = build_string(tmp+3, sizeof tmp - 3, pattern);
-      cmd = realloc(cmd, ncmd+3+rc+1);
+      if (npath != 0) {
+	    snprintf(tmp, sizeof tmp, " -N%s", npath);
+	    rc = strlen(tmp);
+	    cmd = realloc(cmd, ncmd+rc+1);
+	    strcpy(cmd+ncmd, tmp);
+	    ncmd += rc;
+      }
+
+      snprintf(tmp, sizeof tmp, " -C%s", iconfig_path);
+      rc = strlen(tmp);
+      cmd = realloc(cmd, ncmd+rc+1);
+      strcpy(cmd+ncmd, tmp);
+      ncmd += rc;
+
+      snprintf(tmp, sizeof tmp, " -C%s -- -", iconfig_common_path);
+      rc = strlen(tmp);
+      cmd = realloc(cmd, ncmd+rc+1);
+      strcpy(cmd+ncmd, tmp);
+      ncmd += rc;
+
 #ifdef __MINGW32__
      {
 	char *t;
-	for (t = tmp; *t; t++)
+	for (t = cmd+ncmd_start; *t; t++)
 	  {
 	    if (*t == '/') *t = '\\';
 	  }
      }
 #endif

-      strcpy(cmd+ncmd, tmp);
-

      if (verbose_flag)
 	    printf("translate: %s\n", cmd);
@@ -196,7 +270,11 @@ static int t_default(char*cmd, unsigned ncmd)

      rc = system(cmd);
      remove(source_path);
-      remove(iconfig_path);
+      if ( ! getenv("IVERILOG_ICONFIG")) {
+	    remove(iconfig_path);
+	    remove(defines_path);
+      }
+
      if (rc != 0) {
 	    if (rc == 127) {
 		  fprintf(stderr, "Failed to execute: %s\n", cmd);
@@ -216,15 +294,15 @@ static int t_default(char*cmd, unsigned ncmd)

 static void process_warning_switch(const char*name)
 {
-      if (warning_flags[0] == 0)
-	    strcpy(warning_flags, "-W");
-
      if (strcmp(name,"all") == 0) {
-	    strcat(warning_flags, "it");
+	    strcat(warning_flags, "ipt");

      } else if (strcmp(name,"implicit") == 0) {
 	    if (! strchr(warning_flags+2, 'i'))
 		  strcat(warning_flags, "i");
+      } else if (strcmp(name,"portbind") == 0) {
+	    if (! strchr(warning_flags+2, 'p'))
+		  strcat(warning_flags, "p");
      } else if (strcmp(name,"timescale") == 0) {
 	    if (! strchr(warning_flags+2, 't'))
 		  strcat(warning_flags, "t");
@@ -234,6 +312,12 @@ static void process_warning_switch(const char*name)
 		  cp[0] = cp[1];
 		  cp += 1;
 	    }
+      } else if (strcmp(name,"no-portbind") == 0) {
+	    char*cp = strchr(warning_flags+2, 'p');
+	    if (cp) while (*cp) {
+		  cp[0] = cp[1];
+		  cp += 1;
+	    }
      } else if (strcmp(name,"no-timescale") == 0) {
 	    char*cp = strchr(warning_flags+2, 't');
 	    if (cp) while (*cp) {
@@ -260,50 +344,41 @@ void process_library2_switch(const char *name)

 void process_include_dir(const char *name)
 {
-      if (inc_list == 0) {
-	    inc_list = malloc(strlen(" -I")+strlen(name)+1);
-	    strcpy(inc_list, " -I");
-	    strcat(inc_list, name);
-      } else {
-	    inc_list = realloc(inc_list, strlen(inc_list)
-			       + strlen(" -I")
-			       + strlen(name) + 1);
-	    strcat(inc_list, " -I");
-	    strcat(inc_list, name);
-      }
+      fprintf(defines_file, "I:%s\n", name);
 }

 void process_define(const char*name)
 {
-      if (def_list == 0) {
-	    def_list = malloc(strlen(" -D")+strlen(name)+1);
-	    strcpy(def_list, " -D");
-	    strcat(def_list, name);
-      } else {
-	    def_list = realloc(def_list, strlen(def_list)
-			       + strlen(" -D")
-			       + strlen(name) + 1);
-	    strcat(def_list, " -D");
-	    strcat(def_list, name);
-      }
+      fprintf(defines_file,"D:%s\n", name);
 }

+/*
+ * This function is called while processing a file name in a command
+ * file, or a file name on the command line. Look to see if there is a
+ * .sft suffix, and if so pass that as a sys_func file. Otherwise, it
+ * is a Verilog source file to be written into the file list.
+ */
 void process_file_name(const char*name)
 {
-      fprintf(source_file, "%s\n", name);
-      source_count += 1;
+      if (strlen(name) > 4 && strcasecmp(".sft", name+strlen(name)-4) == 0) {
+	    fprintf(iconfig_file,"sys_func:%s\n", name);
+
+      } else {
+	    fprintf(source_file, "%s\n", name);
+	    source_count += 1;
+      }
 }

 int process_generation(const char*name)
 {
      if (strcmp(name,"1") == 0)
-	    generation = "-g1";
+	    generation = "1";

      else if (strcmp(name,"2") == 0)
-	    generation = "-g2";
+	    generation = "2";

-      else if (strcmp(name,"3.0") == 0)
-	    generation = "-g3.0";
+      else if (strcmp(name,"2x") == 0)
+	    generation = "2x";

      else {
 	    fprintf(stderr, "Unknown/Unsupported Language generation "
@@ -311,7 +386,7 @@ int process_generation(const char*name)
 	    fprintf(stderr, "Supported generations are:\n");
 	    fprintf(stderr, "    1   -- IEEE1364-1995 (Verilog 1)\n"
 		            "    2   -- IEEE1364-2001 (Verilog 2001)\n"
-		            "    3.0 -- SystemVerilog 3.0\n");
+		            "    2x  -- Verilog with extensions\n");
 	    return 1;
      }

@@ -320,13 +395,11 @@ int process_generation(const char*name)

 int main(int argc, char **argv)
 {
-      const char*config_path = 0;
      char*cmd;
      unsigned ncmd;
      int e_flag = 0;
      int version_flag = 0;
      int opt, idx, rc;
-      char*cp;

 #ifdef __MINGW32__
      { char * s;
@@ -376,26 +449,58 @@ int main(int argc, char **argv)
 	    return 1;
      }

+      defines_path = strdup(my_tempfile("ivrlg2", &defines_file));
+      if (NULL == defines_file) {
+	    fprintf(stderr, "%s: Error opening temporary file %s\n",
+		    argv[0], defines_path);
+	    fprintf(stderr, "%s: Please check TMP or TMPDIR.\n", argv[0]);
+
+	    fclose(source_file);
+	    remove(source_path);
+	    return 1;
+      }
+
+      fprintf(defines_file, "D:__ICARUS__=1\n");
+
 	/* Create another temporary file for passing configuration
 	   information to ivl. */
-      iconfig_path = strdup(my_tempfile("ivrlh", &iconfig_file));
+
+      if ( (iconfig_path = getenv("IVERILOG_ICONFIG")) ) {
+	    fprintf(stderr, "%s: IVERILOG_ICONFIG=%s\n",
+		    argv[0], iconfig_path);
+
+	    iconfig_file = fopen(iconfig_path, "w");
+
+      } else {
+
+	    iconfig_path = strdup(my_tempfile("ivrlh", &iconfig_file));
+      }
+
      if (NULL == iconfig_file) {
 	    fprintf(stderr, "%s: Error opening temporary file %s\n",
 		    argv[0], iconfig_path);
 	    fprintf(stderr, "%s: Please check TMP or TMPDIR.\n", argv[0]);
 	    fclose(source_file);
 	    remove(source_path);
+
+	    fclose(defines_file);
+	    remove(defines_path);
 	    return 1;
      }

-      while ((opt = getopt(argc, argv, "B:C:c:D:Ef:g:hI:M:m:N::o:p:Ss:T:t:vVW:y:Y:")) != EOF) {
+      while ((opt = getopt(argc, argv, "B:c:D:Ef:g:hI:M:m:N::o:p:Ss:T:t:vVW:y:Y:")) != EOF) {

 	    switch (opt) {
 		case 'B':
-		  base = optarg;
-		  break;
-		case 'C':
-		  config_path = optarg;
+		    /* Undocumented feature: The preprocessor itself
+		       may be located at a different location. If the
+		       base starts with a 'P', set this special base
+		       instead of the main base. */
+		  if (optarg[0] == 'P') {
+			pbase = optarg+1;
+		  } else {
+			base=optarg;
+		  }
 		  break;
 		case 'c':
 		  command_filename = malloc(strlen(optarg)+1);
@@ -410,17 +515,7 @@ int main(int argc, char **argv)
 		case 'f':
 		  fprintf(stderr, "warning: The -f flag is moved to -p\n");
 		case 'p':
-		  if (f_list == 0) {
-			f_list = malloc(strlen(" -p")+strlen(optarg)+1);
-			strcpy(f_list, " -p");
-			strcat(f_list, optarg);
-		  } else {
-			f_list = realloc(f_list, strlen(f_list) +
-					 strlen(" -p") +
-					 strlen(optarg) + 1);
-			strcat(f_list, " -p");
-			strcat(f_list, optarg);
-		  }
+		  fprintf(iconfig_file, "flag:%s\n", optarg);
 		  break;

 		case 'g':
@@ -441,17 +536,7 @@ int main(int argc, char **argv)
 		  break;

 		case 'm':
-		  if (mod_list == 0) {
-			mod_list = malloc(strlen(" -m")+strlen(optarg)+1);
-			strcpy(mod_list, " -m");
-			strcat(mod_list, optarg);
-		  } else {
-			mod_list = realloc(mod_list, strlen(mod_list)
-					   + strlen(" -m")
-					   + strlen(optarg) + 1);
-			strcat(mod_list, " -m");
-			strcat(mod_list, optarg);
-		  }
+		  fprintf(iconfig_file, "module:%s\n", optarg);
 		  break;

 		case 'N':
@@ -466,18 +551,7 @@ int main(int argc, char **argv)
 		  synth_flag = 1;
 		  break;
 		case 's':
-	          if (start) {
-			static const char *s = " -s ";
-			size_t l = strlen(start);
-			start = realloc(start, l + strlen(optarg) + strlen(s) + 1);
-			strcpy(start + l, s);
-			strcpy(start + l + strlen(s), optarg);
-		  } else {
-			static const char *s = "-s ";
-			start = malloc(strlen(optarg) + strlen(s) + 1);
-			strcpy(start, s);
-			strcpy(start + strlen(s), optarg);
-		  }
+		  fprintf(iconfig_file, "root:%s\n", optarg);
 		  break;
 		case 'T':
 		  if (strcmp(optarg,"min") == 0) {
@@ -516,15 +590,36 @@ int main(int argc, char **argv)
 	    }
      }

+      if (pbase == 0)
+	    pbase = base;
+
      if (version_flag || verbose_flag) {
-	    printf("Icarus Verilog version " VERSION "\n");
-	    printf("Copyright 1998-2002 Stephen Williams\n");
-	    printf("$Name:  $\n");
+	    printf("Icarus Verilog version " VERSION " ($Name:  $)\n");
+	    printf("Copyright 1998-2003 Stephen Williams\n");
+	    puts(NOTICE);

 	    if (version_flag)
 		  return 0;
      }

+	/* Make a common conf file path to reflect the target. */
+      sprintf(iconfig_common_path, "%s%c%s%s.conf",
+	      base,sep, targ, synth_flag? "-s" : "");
+
+	/* Write values to the iconfig file. */
+      fprintf(iconfig_file, "basedir:%s\n", base);
+
+	/* Tell the core where to find the system.sft. This file
+	   describes the system functions so that elaboration knows
+	   how to handle them. */
+      fprintf(iconfig_file, "sys_func:%s%csystem.sft\n", base, sep);
+
+      if (mtm != 0) fprintf(iconfig_file, "-T:%s\n", mtm);
+      fprintf(iconfig_file, "generation:%s\n", generation);
+      fprintf(iconfig_file, "warnings:%s\n", warning_flags);
+      fprintf(iconfig_file, "out:%s\n", opath);
+      if (depfile) fprintf(iconfig_file, "depfile:%s\n", depfile);
+
      if (command_filename) {
 	    int rc;

@@ -552,58 +647,28 @@ int main(int argc, char **argv)
      fclose(source_file);
      source_file = 0;

+      fclose(defines_file);
+      defines_file = 0;
+
      if (source_count == 0) {
 	    fprintf(stderr, "%s: No input files.\n", argv[0]);
 	    fprintf(stderr, "%s\n", HELP);
 	    return 1;
      }

-	/* Load the iverilog.conf file to get our substitution
-	   strings. */
-
-      { char path[1024];
-        FILE*fd;
-	if (config_path) {
-	      strcpy(path, config_path);
-	} else {
-	      sprintf(path, "%s%civerilog.conf", base,sep);
-	}
-	fd = fopen(path, "r");
-	if (fd == 0) {
-	      fprintf(stderr, "Config file \"%s\" not found\n",path);
-	      return 1;
-	}
-	reset_lexor(fd);
-	yyparse();
-      }

 	/* Start building the preprocess command line. */

-      sprintf(tmp, "%s%civlpp %s%s -D__ICARUS__=1 -f%s ", base,sep,
+      sprintf(tmp, "%s%civlpp %s%s -F%s -f%s ", pbase,sep,
 	      verbose_flag?" -v":"",
-	      e_flag?"":" -L", source_path);
+	      e_flag?"":" -L", defines_path, source_path);

      ncmd = strlen(tmp);
      cmd = malloc(ncmd + 1);
      strcpy(cmd, tmp);

-      if (inc_list) {
-	    cmd = realloc(cmd, ncmd + strlen(inc_list) + 1);
-	    strcat(cmd, inc_list);
-	    ncmd += strlen(inc_list);
-      }
-
-      if (def_list) {
-	    cmd = realloc(cmd, ncmd + strlen(def_list) + 1);
-	    strcat(cmd, def_list);
-	    ncmd += strlen(def_list);
-      }
-
      if (depfile) {
-	    cmd = realloc(cmd, ncmd + strlen(depfile) + 5);
-	    strcat(cmd, " -M ");
-	    strcat(cmd, depfile);
-	    ncmd += strlen(depfile) + 4;
+	    fprintf(defines_file, "M:%s\n", depfile);
      }

 	/* If the -E flag was given on the command line, then all we
@@ -624,7 +689,8 @@ int main(int argc, char **argv)
 	    rc = system(cmd);
 	    remove(source_path);
 	    fclose(iconfig_file);
-	    remove(iconfig_path);
+	    if ( ! getenv("IVERILOG_ICONFIG"))
+		  remove(iconfig_path);

 	    if (rc != 0) {
 		  if (WIFEXITED(rc)) {
@@ -642,10 +708,8 @@ int main(int argc, char **argv)
 	/* Write the preprocessor command needed to preprocess a
 	   single file. This may be used to preprocess library
 	   files. */
-      fprintf(iconfig_file, "ivlpp:%s%civlpp -D__ICARUS__ -L %s %s\n",
-	      base, sep,
-	      inc_list? inc_list : "",
-	      def_list? def_list : "");
+      fprintf(iconfig_file, "ivlpp:%s%civlpp -D__ICARUS__ -L -F%s\n",
+	      pbase, sep, defines_path);

 	/* Done writing to the iconfig file. Close it now. */
      fclose(iconfig_file);
@@ -657,135 +721,61 @@ int main(int argc, char **argv)

 /*
 * $Log: main.c,v $
- * Revision 1.47  2002/08/12 01:27:48  steve
- *  Escape the backslash in the windows file name.
+ * Revision 1.69  2006/07/26 00:11:40  steve
+ *  Pass depfiles through temp defines file.
 *
- * Revision 1.46  2002/08/10 22:36:59  steve
- *  No longer any nead for -rdynamic flag
+ * Revision 1.68  2006/07/26 00:02:48  steve
+ *  Pass defines and includes through temp file.
 *
- * Revision 1.45  2002/08/10 22:27:13  steve
- *  Kill links to vvm.
+ * Revision 1.67  2005/07/14 23:38:44  steve
+ *  Display as version 0.9.devel
 *
- * Revision 1.44  2002/07/15 00:33:50  steve
- *  Improve temporary file name guess.
+ * Revision 1.66  2005/06/28 04:25:55  steve
+ *  Remove reference to SystemVerilog.
 *
- * Revision 1.43  2002/07/14 23:32:31  steve
- *  No longer need the .exe on generated files.
+ * Revision 1.65  2004/06/17 14:47:22  steve
+ *  Add a .sft file for the system functions.
 *
- * Revision 1.42  2002/07/14 23:11:35  steve
- *  Do temp file creation by hand.
+ * Revision 1.64  2004/03/10 04:51:25  steve
+ *  Add support for system function table files.
 *
- * Revision 1.41  2002/05/28 20:40:37  steve
- *  ivl indexes the search path for libraries, and
- *  supports case insensitive module-to-file lookup.
+ * Revision 1.63  2004/02/15 18:03:30  steve
+ *  Cleanup of warnings.
 *
- * Revision 1.40  2002/05/28 02:25:03  steve
- *  Pass library paths through -Cfile instead of command line.
+ * Revision 1.62  2003/12/12 04:36:48  steve
+ *  Fix make check to support -tconf configuration method.
 *
- * Revision 1.39  2002/05/28 00:50:40  steve
- *  Add the ivl -C flag for bulk configuration
- *  from the driver, and use that to run library
- *  modules through the preprocessor.
+ * Revision 1.61  2003/11/18 06:31:46  steve
+ *  Remove the iverilog.conf file.
 *
- * Revision 1.38  2002/05/27 23:14:06  steve
- *  Predefine __ICARUS__
+ * Revision 1.60  2003/11/13 05:55:33  steve
+ *  Move the DLL= flag to target config files.
 *
- * Revision 1.37  2002/05/24 01:13:00  steve
- *  Support language generation flag -g.
+ * Revision 1.59  2003/11/13 04:09:49  steve
+ *  Pass flags through the temporary config file.
 *
- * Revision 1.36  2002/04/24 02:02:31  steve
- *  add -Wno- arguments to the driver.
+ * Revision 1.58  2003/11/01 04:21:57  steve
+ *  Add support for a target static config file.
 *
- * Revision 1.35  2002/04/15 00:04:23  steve
- *  Timescale warnings.
+ * Revision 1.57  2003/10/26 22:43:42  steve
+ *  Improve -V messages,
 *
- * Revision 1.34  2002/04/04 05:26:13  steve
- *  Add dependency generation.
+ * Revision 1.56  2003/09/26 21:25:58  steve
+ *  Warnings cleanup.
 *
- * Revision 1.33  2002/03/15 23:27:42  steve
- *  Patch to allow user to set place for temporary files.
+ * Revision 1.55  2003/09/23 05:57:15  steve
+ *  Pass -m flag from driver via iconfig file.
 *
- * Revision 1.32  2002/02/03 07:05:37  steve
- *  Support print of version number.
+ * Revision 1.54  2003/09/22 01:12:09  steve
+ *  Pass more ivl arguments through the iconfig file.
 *
- * Revision 1.31  2001/11/21 02:20:34  steve
- *  Pass list of file to ivlpp via temporary file.
+ * Revision 1.53  2003/08/26 16:26:02  steve
+ *  ifdef idents correctly.
 *
- * Revision 1.30  2001/11/16 05:07:19  steve
- *  Add support for +libext+ in command files.
+ * Revision 1.52  2003/02/22 04:55:36  steve
+ *  portbind adds p, not i, flag.
 *
- * Revision 1.29  2001/11/13 03:30:26  steve
- *  The +incdir+ plusarg can take multiple directores,
- *  and add initial support for +define+ in the command file.
- *
- * Revision 1.28  2001/11/12 18:47:32  steve
- *  Support +incdir in command files, and ignore other
- *  +args flags. Also ignore -a and -v flags.
- *
- * Revision 1.27  2001/11/12 01:26:36  steve
- *  More sophisticated command file parser.
- *
- * Revision 1.26  2001/11/11 00:10:05  steve
- *  Remov XNF dead wood.
- *
- * Revision 1.25  2001/10/23 00:37:30  steve
- *  The -s flag can now be repeated on the iverilog command.
- *
- * Revision 1.24  2001/10/20 23:02:40  steve
- *  Add automatic module libraries.
- *
- * Revision 1.23  2001/10/19 23:10:08  steve
- *  Fix memory fault with -c flag.
- *
- * Revision 1.22  2001/10/11 00:12:49  steve
- *  Detect execv failures.
- *
- * Revision 1.21  2001/07/25 03:10:50  steve
- *  Create a config.h.in file to hold all the config
- *  junk, and support gcc 3.0. (Stephan Boettcher)
- *
- * Revision 1.20  2001/06/30 21:53:42  steve
- *  Make the vvp target the default.
- *
- * Revision 1.19  2001/06/30 04:23:02  steve
- *  Get include and lib paths right for mingw and vvm.
- *
- * Revision 1.18  2001/06/30 00:59:24  steve
- *  Redo the ivl_root calculator for mingw.
- *
- * Revision 1.17  2001/06/27 02:22:26  steve
- *  Get include and lib paths from Makefile.
- *
- * Revision 1.16  2001/06/20 02:25:40  steve
- *  Edit ivl_install_dir only on mingw
- *
- * Revision 1.15  2001/06/15 05:14:21  steve
- *  Fix library path calculation on non Windows systems
- *  to include the install directories. (Brendan Simon)
- *
- * Revision 1.14  2001/06/12 03:53:10  steve
- *  Change the VPI call process so that loaded .vpi modules
- *  use a function table instead of implicit binding.
- *
- * Revision 1.13  2001/05/20 18:22:02  steve
- *  Fix WIFEXITED macro.
- *
- * Revision 1.12  2001/05/20 18:06:57  steve
- *  local declares if the header is missing.
- *
- * Revision 1.11  2001/05/20 15:09:40  steve
- *  Mingw32 support (Venkat Iyer)
- *
- * Revision 1.10  2001/05/17 03:14:26  steve
- *  Update help message.
- *
- * Revision 1.9  2001/04/26 16:04:39  steve
- *  Handle missing or uninstalled .conf files.
- *
- * Revision 1.8  2001/02/01 17:12:22  steve
- *  Forgot to actually allow the -p flag.
- *
- * Revision 1.7  2001/01/20 19:02:05  steve
- *  Switch hte -f flag to the -p flag.
+ * Revision 1.51  2003/02/22 04:12:49  steve
+ *  Add the portbind warning.
 */

@@ -1,167 +0,0 @@
-%{
-/*
- * Copyright (c) 2000 Stephen Williams ([email protected])
- *
- *    This source code is free software; you can redistribute it
- *    and/or modify it in source code form under the terms of the GNU
- *    General Public License as published by the Free Software
- *    Foundation; either version 2 of the License, or (at your option)
- *    any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: parse.y,v 1.5 2002/03/31 04:07:16 steve Exp $"
-#endif
-
-# include "config.h"
-
-# include  <stdio.h>
-#ifdef HAVE_MALLOC_H
-# include  <malloc.h>
-#endif
-# include  <stdlib.h>
-# include  "globals.h"
-
-
-void yyerror(const char*);
-
-enum drive_code_t {
-      CODE_S,
-      CODE_t,
-};
-
-struct drive_cond {
-      struct drive_cond*next;
-      enum drive_code_t code;
-      char* text;
-};
-
-static struct drive_cond *cur_cond = 0;
-
-static void add_cond(enum drive_code_t code, char*text)
-{
-      struct drive_cond*tmp;
-      tmp = calloc(1, sizeof(struct drive_cond));
-      tmp->code = code;
-      tmp->text = text;
-
-      tmp->next = cur_cond;
-      cur_cond = tmp;
-}
-
-struct drive_pattern {
-      struct drive_pattern*next;
-      char*name;
-      char*text;
-      struct drive_cond*cond;
-};
-
-static struct drive_pattern *patterns = 0;
-static struct drive_pattern *plast = 0;
-
-static void add_pattern(char*name, char*text)
-{
-      struct drive_pattern*tmp;
-      tmp = calloc(1, sizeof(struct drive_pattern));
-      tmp->name = name;
-      tmp->text = text;
-      tmp->cond = cur_cond;
-      tmp->next = 0;
-
-
-      if (plast) {
-	    plast->next = tmp;
-	    plast = tmp;
-      } else {
-	    patterns = tmp;
-	    plast = tmp;
-      }
-}
-
-const char*lookup_pattern(const char*key)
-{
-      struct drive_pattern*cur;
-      struct drive_cond*cc;
-
-      for (cur = patterns ;  cur ;  cur = cur->next) {
-
-	    if (strcmp(key, cur->name) != 0)
-		  continue;
-
-	    for (cc = cur->cond ;  cc ;  cc = cc->next) {
-
-		  switch (cc->code) {
-		      case CODE_S:
-			if (synth_flag)
-			      continue;
-			break;
-		      case CODE_t:
-			if (strcmp(targ, cc->text) == 0)
-			      continue;
-			break;
-		  }
-
-		  break;
-	    }
-
-	    if (cc) continue;
-
-	    return cur->text;
-      }
-
-      return 0;
-}
-
-%}
-
-%union {
-      char*text;
-};
-
-%token <text> PATTERN_NAME PATTERN_TEXT
-%token <text> CT_t
-%token CT_S
-
-%%
-
-start: section_list ;
-
-section_list
-	: section
-	| section_list section
-	;
-
-section : '[' ctoken_list ']' pattern_list { cur_cond = 0; } ;
-
-ctoken_list
-	: ctoken
-	| ctoken_list ctoken
-	;
-
-ctoken  : CT_S  { add_cond(CODE_S, 0); }
-	| CT_t  { add_cond(CODE_t, $1); }
-	;
-
-pattern_list
-	: pattern
-	| pattern_list pattern
-	;
-
-pattern : PATTERN_NAME PATTERN_TEXT
-		{ add_pattern($1, $2); }
-	;
-
-%%
-
-void yyerror(const char*msg)
-{
-      fprintf(stderr, "%s\n", msg);
-}
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: substit.c,v 1.4 2002/08/12 01:35:01 steve Exp $"
+#ident "$Id: substit.c,v 1.5 2003/12/19 01:27:10 steve Exp $"
 #endif

 # include  <string.h>
@@ -66,7 +66,7 @@ char* substitutions(const char*str)
 		  cp += strlen(cp);

 	    } else {
-		  if ( (cp - buf) == nbuf ) {
+		  if ( cp == (buf + nbuf) ) {
 			size_t old_size = nbuf;
 			nbuf = old_size + 32;
 			buf = realloc(buf, nbuf);
@@ -79,7 +79,7 @@ char* substitutions(const char*str)

 	/* Add the trailing nul to the string, and reallocate the
 	   buffer to be a tight fit. */
-      if ( (cp - buf) == nbuf ) {
+      if ( cp == (buf + nbuf) ) {
 	    size_t old_size = nbuf;
 	    nbuf = old_size + 1;
 	    buf = realloc(buf, nbuf);
@@ -96,6 +96,9 @@ char* substitutions(const char*str)

 /*
 * $Log: substit.c,v $
+ * Revision 1.5  2003/12/19 01:27:10  steve
+ *  Fix various unsigned compare warnings.
+ *
 * Revision 1.4  2002/08/12 01:35:01  steve
 *  conditional ident string using autoconfig.
 *
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2002 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: dup_expr.cc,v 1.8 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: dup_expr.cc,v 1.20 2005/07/11 16:56:50 steve Exp $"
 #endif

 # include "config.h"
@@ -25,6 +25,40 @@
 # include  "netlist.h"
 # include  <cassert>

+NetEBComp* NetEBComp::dup_expr() const
+{
+      NetEBComp*result = new NetEBComp(op_, left_->dup_expr(),
+				       right_->dup_expr());
+      return result;
+}
+
+NetEConst* NetEConst::dup_expr() const
+{
+      NetEConst*tmp = new NetEConst(value_);
+      tmp->set_line(*this);
+      return tmp;
+}
+
+NetEConstParam* NetEConstParam::dup_expr() const
+{
+      NetEConstParam*tmp = new NetEConstParam(scope_, name_, value());
+      tmp->set_line(*this);
+      return tmp;
+}
+
+NetECRealParam* NetECRealParam::dup_expr() const
+{
+      NetECRealParam*tmp = new NetECRealParam(scope_, name_, value());
+      tmp->set_line(*this);
+      return tmp;
+}
+
+NetEEvent* NetEEvent::dup_expr() const
+{
+      assert(0);
+      return 0;
+}
+
 NetEScope* NetEScope::dup_expr() const
 {
      assert(0);
@@ -39,8 +73,10 @@ NetESelect* NetESelect::dup_expr() const

 NetESFunc* NetESFunc::dup_expr() const
 {
-      NetESFunc*tmp = new NetESFunc(name_, expr_width(), nparms());
+      NetESFunc*tmp = new NetESFunc(name_, type_, expr_width(), nparms());
      assert(tmp);
+
+      tmp->cast_signed(has_sign());
      for (unsigned idx = 0 ;  idx < nparms() ;  idx += 1) {
 	    assert(tmp->parm(idx));
 	    tmp->parm(idx, tmp->parm(idx)->dup_expr());
@@ -51,7 +87,7 @@ NetESFunc* NetESFunc::dup_expr() const

 NetESignal* NetESignal::dup_expr() const
 {
-      NetESignal*tmp = new NetESignal(net_, msi_, lsi_);
+      NetESignal*tmp = new NetESignal(net_);
      assert(tmp);
      tmp->expr_width(expr_width());
      return tmp;
@@ -65,6 +101,22 @@ NetETernary* NetETernary::dup_expr() const
      return tmp;
 }

+NetEUFunc* NetEUFunc::dup_expr() const
+{
+      NetEUFunc*tmp;
+      svector<NetExpr*> tmp_parms (parms_.count());
+
+      for (unsigned idx = 0 ;  idx < tmp_parms.count() ;  idx += 1) {
+	    assert(parms_[idx]);
+	    tmp_parms[idx] = parms_[idx]->dup_expr();
+      }
+
+      tmp = new NetEUFunc(func_, result_sig_->dup_expr(), tmp_parms);
+
+      assert(tmp);
+      return tmp;
+}
+
 NetEUnary* NetEUnary::dup_expr() const
 {
      NetEUnary*tmp = new NetEUnary(op_, expr_->dup_expr());
@@ -72,8 +124,58 @@ NetEUnary* NetEUnary::dup_expr() const
      return tmp;
 }

+NetEUReduce* NetEUReduce::dup_expr() const
+{
+      NetEUReduce*tmp = new NetEUReduce(op_, expr_->dup_expr());
+      assert(tmp);
+      return tmp;
+}
+
 /*
 * $Log: dup_expr.cc,v $
+ * Revision 1.20  2005/07/11 16:56:50  steve
+ *  Remove NetVariable and ivl_variable_t structures.
+ *
+ * Revision 1.19  2004/12/11 02:31:25  steve
+ *  Rework of internals to carry vectors through nexus instead
+ *  of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ *  down this path.
+ *
+ * Revision 1.18  2004/06/17 16:06:18  steve
+ *  Help system function signedness survive elaboration.
+ *
+ * Revision 1.17  2004/05/31 23:34:36  steve
+ *  Rewire/generalize parsing an elaboration of
+ *  function return values to allow for better
+ *  speed and more type support.
+ *
+ * Revision 1.16  2003/10/31 02:47:11  steve
+ *  NetEUReduce has its own dup_expr method.
+ *
+ * Revision 1.15  2003/05/30 02:55:32  steve
+ *  Support parameters in real expressions and
+ *  as real expressions, and fix multiply and
+ *  divide with real results.
+ *
+ * Revision 1.14  2003/04/22 04:48:29  steve
+ *  Support event names as expressions elements.
+ *
+ * Revision 1.13  2003/03/15 18:08:43  steve
+ *  Comparison operators do have defined width.
+ *
+ * Revision 1.12  2003/03/15 04:46:28  steve
+ *  Better organize the NetESFunc return type guesses.
+ *
+ * Revision 1.11  2003/03/10 23:40:53  steve
+ *  Keep parameter constants for the ivl_target API.
+ *
+ * Revision 1.10  2003/01/26 21:15:58  steve
+ *  Rework expression parsing and elaboration to
+ *  accommodate real/realtime values and expressions.
+ *
+ * Revision 1.9  2002/11/09 00:25:27  steve
+ *  Add dup_expr for user defined function calls.
+ *
 * Revision 1.8  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -97,12 +199,5 @@ NetEUnary* NetEUnary::dup_expr() const
 * Revision 1.3  2000/05/04 03:37:58  steve
 *  Add infrastructure for system functions, move
 *  $time to that structure and add $random.
- *
- * Revision 1.2  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.1  1999/11/27 19:07:57  steve
- *  Support the creation of scopes.
- *
 */

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000 Stephen Williams (steve@icarus.com.com)
+ * Copyright (c) 2000-2003 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_anet.cc,v 1.5 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: elab_anet.cc,v 1.12 2006/05/01 20:47:58 steve Exp $"
 #endif

 # include "config.h"
@@ -29,12 +29,13 @@

 # include  "PExpr.h"
 # include  "netlist.h"
+# include  "netmisc.h"
 # include  <iostream>

 NetNet* PExpr::elaborate_anet(Design*des, NetScope*scope) const
 {
      cerr << get_line() << ": error: Invalid expression on left side "
-	   << "of precedural continuous asignment." << endl;
+	   << "of procedural continuous assignment." << endl;
      return 0;
 }

@@ -86,12 +87,15 @@ NetNet* PEConcat::elaborate_anet(Design*des, NetScope*scope) const
 	   Allow for a repeat count other then 1 by repeating the
 	   connect loop as many times as necessary. */

-      NetNet*osig = new NetNet(scope, des->local_symbol(scope->name()),
+      NetNet*osig = new NetNet(scope, scope->local_symbol(),
 			       NetNet::IMPLICIT_REG, pins);
+	/* Assume that all the data types are the same. */
+      osig->data_type(nets[0]->data_type());

      pins = 0;
      for (unsigned idx = nets.count() ;  idx > 0 ;  idx -= 1) {
 	    NetNet*cur = nets[idx-1];
+	    assert(cur->data_type() == osig->data_type());
 	    for (unsigned pin = 0;  pin < cur->pin_count();  pin += 1) {
 		  connect(osig->pin(pins), cur->pin(pin));
 		  pins += 1;
@@ -104,17 +108,33 @@ NetNet* PEConcat::elaborate_anet(Design*des, NetScope*scope) const

 NetNet* PEIdent::elaborate_anet(Design*des, NetScope*scope) const
 {
-      NetNet*sig = des->find_signal(scope, path_);
+      assert(scope);
+
+      NetNet*       sig = 0;
+      NetMemory*    mem = 0;
+      const NetExpr*par = 0;
+      NetEvent*     eve = 0;
+
+      symbol_search(des, scope, path_, sig, mem, par, eve);
+
+
+      if (mem != 0) {
+	    cerr << get_line() << ": error: memories not allowed "
+		 << "on left side of procedural continuous "
+		 << "assignment." << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+      if (eve != 0) {
+	    cerr << get_line() << ": error: named events not allowed "
+		 << "on left side of procedural continuous "
+		 << "assignment." << endl;
+	    des->errors += 1;
+	    return 0;
+      }

      if (sig == 0) {
-	    if (NetMemory*mem = des->find_memory(scope, path_)) {
-		  cerr << get_line() << ": error: memories not allowed "
-		       << "on left side of procedural continuous "
-		       << "asignment." << endl;
-		  des->errors += 1;
-		  return 0;
-	    }
-
 	    cerr << get_line() << ": error: reg ``" << path_ << "'' "
 		 << "is undefined in this scope." << endl;
 	    des->errors += 1;
@@ -138,8 +158,8 @@ NetNet* PEIdent::elaborate_anet(Design*des, NetScope*scope) const
      if (msb_ || lsb_) {

 	    cerr << get_line() << ": error: bit/part selects not allowed "
-		 << "on left side of procedural continuous asignment."
-		 << endl; 
+		 << "on left side of procedural continuous assignment."
+		 << endl;
 	    des->errors += 1;
 	    return 0;
      }
@@ -149,6 +169,27 @@ NetNet* PEIdent::elaborate_anet(Design*des, NetScope*scope) const

 /*
 * $Log: elab_anet.cc,v $
+ * Revision 1.12  2006/05/01 20:47:58  steve
+ *  More explicit datatype setup.
+ *
+ * Revision 1.11  2005/07/11 16:56:50  steve
+ *  Remove NetVariable and ivl_variable_t structures.
+ *
+ * Revision 1.10  2004/10/04 01:10:52  steve
+ *  Clean up spurious trailing white space.
+ *
+ * Revision 1.9  2003/09/19 03:50:12  steve
+ *  Remove find_memory method from Design class.
+ *
+ * Revision 1.8  2003/06/21 01:21:43  steve
+ *  Harmless fixup of warnings.
+ *
+ * Revision 1.7  2003/03/06 00:28:41  steve
+ *  All NetObj objects have lex_string base names.
+ *
+ * Revision 1.6  2003/01/27 05:09:17  steve
+ *  Spelling fixes.
+ *
 * Revision 1.5  2002/08/12 01:34:58  steve
 *  conditional ident string using autoconfig.
 *
@@ -17,35 +17,36 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_lval.cc,v 1.20 2002/08/12 01:34:58 steve Exp $"
+#ident "$Id: elab_lval.cc,v 1.36 2006/06/02 04:48:50 steve Exp $"
 #endif

 # include "config.h"

 # include  "PExpr.h"
 # include  "netlist.h"
+# include  "netmisc.h"

 # include  <iostream>

 /*
 * These methods generate a NetAssign_ object for the l-value of the
- * assignemnt. This is common code for the = and <= statements.
+ * assignment. This is common code for the = and <= statements.
 *
 * What gets generated depends on the structure of the l-value. If the
- * l-value is a simple name (i.e. foo <= <value>) the the NetAssign_
+ * l-value is a simple name (i.e., foo <= <value>) the the NetAssign_
 * is created the width of the foo reg and connected to all the
 * bits.
 *
- * If there is a part select (i.e. foo[3:1] <= <value>) the NetAssign_
+ * If there is a part select (i.e., foo[3:1] <= <value>) the NetAssign_
 * is made only as wide as it needs to be (3 bits in this example) and
 * connected to the correct bits of foo. A constant bit select is a
- * special case of the part select. 
+ * special case of the part select.
 *
- * If the bit-select is non-constant (i.e. foo[<expr>] = <value>) the
+ * If the bit-select is non-constant (i.e., foo[<expr>] = <value>) the
 * NetAssign_ is made wide enough to connect to all the bits of foo,
 * then the mux expression is elaborated and attached to the
 * NetAssign_ node as a b_mux value. The target must interpret the
- * presense of a bmux value as taking a single bit and assigning it to
+ * presence of a bmux value as taking a single bit and assigning it to
 * the bit selected by the bmux expression.
 *
 * If the l-value expression is non-trivial, but can be fully
@@ -55,7 +56,7 @@
 * l-value.
 *
 * This last case can turn up in statements like: {a, b[1]} = c;
- * rather then create a NetAssign_ for each item in the contatenation,
+ * rather then create a NetAssign_ for each item in the concatenation,
 * elaboration makes a single NetAssign_ and connects it up properly.
 */

@@ -65,7 +66,9 @@
 * is to try to make a net elaboration, and see if the result is
 * suitable for assignment.
 */
-NetAssign_* PExpr::elaborate_lval(Design*des, NetScope*scope) const
+NetAssign_* PExpr::elaborate_lval(Design*des,
+				  NetScope*scope,
+				  bool is_force) const
 {
      NetNet*ll = 0;
      if (ll == 0) {
@@ -91,7 +94,9 @@ NetAssign_* PExpr::elaborate_lval(Design*des, NetScope*scope) const
 * a is the MSB and b the LSB. Connect the LSB to the low pins of the
 * NetAssign_ object.
 */
-NetAssign_* PEConcat::elaborate_lval(Design*des, NetScope*scope) const
+NetAssign_* PEConcat::elaborate_lval(Design*des,
+				     NetScope*scope,
+				     bool is_force) const
 {
      if (repeat_) {
 	    cerr << get_line() << ": error: Repeat concatenations make "
@@ -103,7 +108,15 @@ NetAssign_* PEConcat::elaborate_lval(Design*des, NetScope*scope) const
      NetAssign_*res = 0;

      for (unsigned idx = 0 ;  idx < parms_.count() ;  idx += 1) {
-	    NetAssign_*tmp = parms_[idx]->elaborate_lval(des, scope);
+
+	    if (parms_[idx] == 0) {
+		  cerr << get_line() << ": error: Empty expressions "
+		       << "not allowed in concatenations." << endl;
+		  des->errors += 1;
+		  continue;
+	    }
+
+	    NetAssign_*tmp = parms_[idx]->elaborate_lval(des, scope, is_force);

 	      /* If the l-value doesn't elaborate, the error was
 		 already detected and printed. We just skip it and let
@@ -131,17 +144,31 @@ NetAssign_* PEConcat::elaborate_lval(Design*des, NetScope*scope) const
 * Handle the ident as an l-value. This includes bit and part selects
 * of that ident.
 */
-NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
+NetAssign_* PEIdent::elaborate_lval(Design*des,
+				    NetScope*scope,
+				    bool is_force) const
 {
-	/* Get the signal referenced by the identifier, and make sure
-	   it is a register. (Wires are not allows in this context. */
-      NetNet*reg = des->find_signal(scope, path_);
+      NetNet*       reg = 0;
+      NetMemory*    mem = 0;
+      const NetExpr*par = 0;
+      NetEvent*     eve = 0;
+
+      symbol_search(des, scope, path_, reg, mem, par, eve);
+
+      if (mem) {
+	    if (is_force) {
+		  cerr << get_line() << ": error: Memories "
+		       << "(" << path_ << " in this case)"
+		       << " are not allowed"
+		       << " as l-values to force statements." << endl;
+		  des->errors += 1;
+		  return 0;
+	    }
+
+	    return elaborate_mem_lval_(des, scope, mem);
+      }

      if (reg == 0) {
-	    NetMemory*mem = des->find_memory(scope, path_);
-	    if (mem != 0)
-		  return elaborate_mem_lval_(des, scope, mem);
-
 	    cerr << get_line() << ": error: Could not find variable ``"
 		 << path_ << "'' in ``" << scope->name() <<
 		  "''" << endl;
@@ -149,56 +176,47 @@ NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
 	    des->errors += 1;
 	    return 0;
      }
+
      assert(reg);

-      if (reg->type() != NetNet::REG) {
+      if (sel_ == SEL_PART)
+	    return elaborate_lval_net_part_(des, scope, reg);
+
+      if (sel_ == SEL_IDX_UP)
+	    return elaborate_lval_net_idx_up_(des, scope, reg);
+
+      if (sel_ == SEL_IDX_DO)
+	    return elaborate_lval_net_idx_do_(des, scope, reg);
+
+	/* Get the signal referenced by the identifier, and make sure
+	   it is a register. Wires are not allows in this context,
+	   unless this is the l-value of a force. */
+      if ((reg->type() != NetNet::REG) && !is_force) {
 	    cerr << get_line() << ": error: " << path_ <<
 		  " is not a reg/integer/time in " << scope->name() <<
 		  "." << endl;
+	    cerr << reg->get_line() << ":      : " << path_ <<
+		  " is declared here as " << reg->type() << "." << endl;
 	    des->errors += 1;
 	    return 0;
      }

+      assert(msb_ == 0);
+      assert(lsb_ == 0);
      long msb, lsb;
      NetExpr*mux;

-      if (msb_ && lsb_) {
-	      /* This handles part selects. In this case, there are
-		 two bit select expressions, and both must be
-		 constant. Evaluate them and pass the results back to
-		 the caller. */
-	    verinum*vl = lsb_->eval_const(des, scope);
-	    if (vl == 0) {
-		  cerr << lsb_->get_line() << ": error: "
-			"Part select expressions must be constant: "
-		       << *lsb_;
-		  des->errors += 1;
-		  return 0;
-	    }
-	    verinum*vm = msb_->eval_const(des, scope);
-	    if (vl == 0) {
-		  cerr << msb_->get_line() << ": error: "
-			"Part select expressions must be constant: "
-		       << *msb_;
-		  des->errors += 1;
-		  return 0;
-	    }
-
-	    msb = vm->as_long();
-	    lsb = vl->as_long();
-	    mux = 0;
-
-      } else if (msb_) {
+      if (! idx_.empty()) {

 	      /* If there is only a single select expression, it is a
 		 bit select. Evaluate the constant value and treat it
 		 as a part select with a bit width of 1. If the
 		 expression it not constant, then return the
 		 expression as a mux. */
-	    assert(lsb_ == 0);
-	    verinum*v = msb_->eval_const(des, scope);
+	    assert(idx_.size() == 1);
+	    verinum*v = idx_[0]->eval_const(des, scope);
 	    if (v == 0) {
-		  NetExpr*m = msb_->elaborate_expr(des, scope);
+		  NetExpr*m = idx_[0]->elaborate_expr(des, scope, -1, false);
 		  assert(m);
 		  msb = 0;
 		  lsb = 0;
@@ -216,8 +234,6 @@ NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
 	      /* No select expressions, so presume a part select the
 		 width of the register. */

-	    assert(msb_ == 0);
-	    assert(lsb_ == 0);
 	    msb = reg->msb();
 	    lsb = reg->lsb();
 	    mux = 0;
@@ -232,7 +248,19 @@ NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
 		 bmux to select the target bit. */
 	    lv = new NetAssign_(reg);

-	    lv->set_bmux(mux);
+	      /* Correct the mux for the range of the vector. */
+	    if (reg->msb() < reg->lsb())
+		  mux = make_sub_expr(reg->lsb(), mux);
+	    else if (reg->lsb() != 0)
+		  mux = make_add_expr(mux, - reg->lsb());
+
+	    lv->set_part(mux, 1);
+
+      } else if (msb == reg->msb() && lsb == reg->lsb()) {
+
+	      /* No bit select, and part select covers the entire
+		 vector. Simplest case. */
+	    lv = new NetAssign_(reg);

      } else {

@@ -256,7 +284,7 @@ NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
 		 converted to normalized form so is relative the
 		 variable pins. */

-	    if ((wid + loff) > reg->pin_count()) {
+	    if ((wid + loff) > reg->vector_width()) {
 		  cerr << get_line() << ": error: bit/part select "
 		       << reg->name() << "[" << msb<<":"<<lsb<<"]"
 		       << " is out of range." << endl;
@@ -265,31 +293,248 @@ NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
 	    }

 	    lv = new NetAssign_(reg);
-	    lv->set_part(loff, wid);
-
-	    assert(moff < reg->pin_count());
+	    lv->set_part(new NetEConst(verinum(loff)), wid);
      }


      return lv;
 }

+NetAssign_* PEIdent::elaborate_lval_net_part_(Design*des,
+					      NetScope*scope,
+					      NetNet*reg) const
+{
+      assert(msb_ && lsb_);
+
+	/* This handles part selects. In this case, there are
+	   two bit select expressions, and both must be
+	   constant. Evaluate them and pass the results back to
+	   the caller. */
+      NetExpr*lsb_ex = elab_and_eval(des, scope, lsb_, -1);
+      NetEConst*lsb_c = dynamic_cast<NetEConst*>(lsb_ex);
+      if (lsb_c == 0) {
+	    cerr << lsb_->get_line() << ": error: "
+		  "Part select expressions must be constant."
+		 << endl;
+	    cerr << lsb_->get_line() << ":      : This lsb expression "
+		  "violates the rule: " << *lsb_ << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+      NetExpr*msb_ex = elab_and_eval(des, scope, msb_, -1);
+      NetEConst*msb_c = dynamic_cast<NetEConst*>(msb_ex);
+      if (msb_c == 0) {
+	    cerr << msb_->get_line() << ": error: "
+		  "Part select expressions must be constant."
+		 << endl;
+	    cerr << msb_->get_line() << ":      : This msb expression "
+		  "violates the rule: " << *msb_ << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+      long msb = msb_c->value().as_long();
+      long lsb = lsb_c->value().as_long();
+
+      delete msb_ex;
+      delete lsb_ex;
+
+      NetAssign_*lv = 0;
+
+      if (msb == reg->msb() && lsb == reg->lsb()) {
+
+	      /* No bit select, and part select covers the entire
+		 vector. Simplest case. */
+	    lv = new NetAssign_(reg);
+
+      } else {
+
+	      /* If the bit/part select is constant, then make the
+		 NetAssign_ only as wide as it needs to be and connect
+		 only to the selected bits of the reg. */
+	    unsigned loff = reg->sb_to_idx(lsb);
+	    unsigned moff = reg->sb_to_idx(msb);
+	    unsigned wid = moff - loff + 1;
+
+	    if (moff < loff) {
+		  cerr << get_line() << ": error: part select "
+		       << reg->name() << "[" << msb<<":"<<lsb<<"]"
+		       << " is reversed." << endl;
+		  des->errors += 1;
+		  return 0;
+	    }
+
+	      /* If the part select extends beyond the extreme of the
+		 variable, then report an error. Note that loff is
+		 converted to normalized form so is relative the
+		 variable pins. */
+
+	    if ((wid + loff) > reg->vector_width()) {
+		  cerr << get_line() << ": error: bit/part select "
+		       << reg->name() << "[" << msb<<":"<<lsb<<"]"
+		       << " is out of range." << endl;
+		  des->errors += 1;
+		  return 0;
+	    }
+
+	    lv = new NetAssign_(reg);
+	    lv->set_part(new NetEConst(verinum(loff)), wid);
+      }
+
+      return lv;
+}
+
+NetAssign_* PEIdent::elaborate_lval_net_idx_up_(Design*des,
+						NetScope*scope,
+						NetNet*reg) const
+{
+      assert(lsb_);
+      assert(msb_);
+
+      if (reg->type() != NetNet::REG) {
+	    cerr << get_line() << ": error: " << path_ <<
+		  " is not a reg/integer/time in " << scope->name() <<
+		  "." << endl;
+	    cerr << reg->get_line() << ":      : " << path_ <<
+		  " is declared here as " << reg->type() << "." << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+	/* Calculate the width expression (in the lsb_ position)
+	   first. If the expression is not constant, error but guess 1
+	   so we can keep going and find more errors. */
+      NetExpr*wid_ex = elab_and_eval(des, scope, lsb_, -1);
+      NetEConst*wid_c = dynamic_cast<NetEConst*>(wid_ex);
+
+      if (wid_c == 0) {
+	    cerr << get_line() << ": error: Indexed part width must be "
+		 << "constant. Expression in question is..." << endl;
+	    cerr << get_line() << ":      : " << *wid_ex << endl;
+	    des->errors += 1;
+      }
+
+      unsigned wid = wid_c? wid_c->value().as_ulong() : 1;
+      delete wid_ex;
+
+      NetExpr*base = elab_and_eval(des, scope, msb_, -1);
+
+	/* Correct the mux for the range of the vector. */
+      if (reg->msb() < reg->lsb())
+	    base = make_sub_expr(reg->lsb(), base);
+      else if (reg->lsb() != 0)
+	    base = make_add_expr(base, - reg->lsb());
+
+      NetAssign_*lv = new NetAssign_(reg);
+      lv->set_part(base, wid);
+
+      return lv;
+}
+
+NetAssign_* PEIdent::elaborate_lval_net_idx_do_(Design*des,
+						NetScope*scope,
+						NetNet*reg) const
+{
+      assert(lsb_);
+      assert(msb_);
+      cerr << get_line() << ": internal error: don't know how to "
+	    "deal with SEL_IDX_DO in lval?" << endl;
+      des->errors += 1;
+      return 0;
+}
+
 NetAssign_* PEIdent::elaborate_mem_lval_(Design*des, NetScope*scope,
 					NetMemory*mem) const
 {
-      assert(msb_ && !lsb_);
+      if (idx_.empty()) {
+	    cerr << get_line() << ": error: Assign to memory \""
+		 << mem->name() << "\" requires a word select index."
+		 << endl;
+	    des->errors += 1;
+	    return 0;
+      }

-      NetExpr*ix = msb_->elaborate_expr(des, scope);
+      if (idx_.size() != mem->dimensions()) {
+	    cerr << get_line() << ": error: " << idx_.size()
+		 << " indices do not properly address a "
+		 << mem->dimensions() << "-dimension memory/array."
+		 << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+	// XXXX For now, require exactly 1 index.
+      assert(idx_.size() == 1);
+
+	/* Elaborate the address expression. */
+      NetExpr*ix = elab_and_eval(des, scope, idx_[0], -1);
      if (ix == 0)
 	    return 0;

      NetAssign_*lv = new NetAssign_(mem);
      lv->set_bmux(ix);
-      lv->set_part(0, mem->width());
+
+	/* If there is no extra part select, then we are done. */
+      if (msb_ == 0 && lsb_ == 0) {
+	    lv->set_part(0, mem->width());
+	    return lv;
+      }
+
+      assert(sel_ != SEL_NONE);
+      assert(msb_ && lsb_);
+
+      if (sel_ == SEL_PART) {
+	    NetExpr*le = elab_and_eval(des, scope, lsb_, -1);
+	    NetExpr*me = elab_and_eval(des, scope, msb_, -1);
+
+	    NetEConst*lec = dynamic_cast<NetEConst*>(le);
+	    NetEConst*mec = dynamic_cast<NetEConst*>(me);
+
+	    if (lec == 0 || mec == 0) {
+		  cerr << get_line() << ": error: Part select "
+		       << "expressions must be constant." << endl;
+		  des->errors += 1;
+		  delete le;
+		  delete me;
+		  return lv;
+	    }
+
+	    verinum wedv = mec->value() - lec->value();
+	    unsigned wid = wedv.as_long() + 1;
+
+	    lv->set_part(lec, wid);
+	    return lv;
+      }
+
+      assert(sel_ == SEL_IDX_UP || sel_ == SEL_IDX_DO);
+
+      NetExpr*wid_ex = elab_and_eval(des, scope, lsb_, -1);
+      NetEConst*wid_ec = dynamic_cast<NetEConst*> (wid_ex);
+      if (wid_ec == 0) {
+	    cerr << lsb_->get_line() << ": error: "
+		 << "Second expression of indexed part select "
+		 << "most be constant." << endl;
+	    des->errors += 1;
+	    return lv;
+      }
+
+      unsigned wid = wid_ec->value().as_ulong();
+
+      NetExpr*base_ex = elab_and_eval(des, scope, msb_, -1);
+      if (base_ex == 0) {
+	    return 0;
+      }
+
+      if (sel_ == SEL_IDX_DO && wid > 1) {
+	    base_ex = make_add_expr(base_ex, 1-(long)wid);
+      }
+
+      lv->set_part(base_ex, wid);
      return lv;
 }

-NetAssign_* PENumber::elaborate_lval(Design*des, NetScope*) const
+NetAssign_* PENumber::elaborate_lval(Design*des, NetScope*, bool) const
 {
      cerr << get_line() << ": error: Constant values not allowed "
 	   << "in l-value expressions." << endl;
@@ -299,75 +544,43 @@ NetAssign_* PENumber::elaborate_lval(Design*des, NetScope*) const

 /*
 * $Log: elab_lval.cc,v $
- * Revision 1.20  2002/08/12 01:34:58  steve
- *  conditional ident string using autoconfig.
+ * Revision 1.36  2006/06/02 04:48:50  steve
+ *  Make elaborate_expr methods aware of the width that the context
+ *  requires of it. In the process, fix sizing of the width of unary
+ *  minus is context determined sizes.
 *
- * Revision 1.19  2002/06/04 05:38:44  steve
- *  Add support for memory words in l-value of
- *  blocking assignments, and remove the special
- *  NetAssignMem class.
+ * Revision 1.35  2006/04/16 00:54:04  steve
+ *  Cleanup lval part select handling.
 *
- * Revision 1.18  2002/03/09 04:02:26  steve
- *  Constant expressions are not l-values for task ports.
+ * Revision 1.34  2006/04/16 00:15:43  steve
+ *  Fix part selects in l-values.
 *
- * Revision 1.17  2001/12/03 04:47:14  steve
- *  Parser and pform use hierarchical names as hname_t
- *  objects instead of encoded strings.
+ * Revision 1.33  2006/02/02 02:43:57  steve
+ *  Allow part selects of memory words in l-values.
 *
- * Revision 1.16  2001/11/08 05:15:50  steve
- *  Remove string paths from PExpr elaboration.
+ * Revision 1.32  2005/07/11 16:56:50  steve
+ *  Remove NetVariable and ivl_variable_t structures.
 *
- * Revision 1.15  2001/11/07 04:01:59  steve
- *  eval_const uses scope instead of a string path.
+ * Revision 1.31  2004/12/29 23:55:43  steve
+ *  Unify elaboration of l-values for all proceedural assignments,
+ *  including assing, cassign and force.
 *
- * Revision 1.14  2001/08/25 23:50:02  steve
- *  Change the NetAssign_ class to refer to the signal
- *  instead of link into the netlist. This is faster
- *  and uses less space. Make the NetAssignNB carry
- *  the delays instead of the NetAssign_ lval objects.
+ *  Generate NetConcat devices for gate outputs that feed into a
+ *  vector results. Use this to hande gate arrays. Also let gate
+ *  arrays handle vectors of gates when the outputs allow for it.
 *
- *  Change the vvp code generator to support multiple
- *  l-values, i.e. concatenations of part selects.
+ * Revision 1.30  2004/12/11 02:31:25  steve
+ *  Rework of internals to carry vectors through nexus instead
+ *  of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ *  down this path.
 *
- * Revision 1.13  2001/07/25 03:10:48  steve
- *  Create a config.h.in file to hold all the config
- *  junk, and support gcc 3.0. (Stephan Boettcher)
+ * Revision 1.29  2004/10/04 01:10:52  steve
+ *  Clean up spurious trailing white space.
 *
- * Revision 1.12  2001/02/09 03:16:48  steve
- *  Report bit/part select out of range errors. (PR#133)
- *
- * Revision 1.11  2001/01/10 03:13:23  steve
- *  Build task outputs as lval instead of nets. (PR#98)
- *
- * Revision 1.10  2001/01/06 06:31:58  steve
- *  declaration initialization for time variables.
- *
- * Revision 1.9  2001/01/06 02:29:36  steve
- *  Support arrays of integers.
- *
- * Revision 1.8  2000/12/12 06:14:51  steve
- *  sorry for concatenated memories in l-values. (PR#76)
- *
- * Revision 1.7  2000/12/01 02:55:37  steve
- *  Detect part select errors on l-values.
- *
- * Revision 1.6  2000/10/31 17:49:02  steve
- *  Support time variables.
- *
- * Revision 1.5  2000/10/26 17:09:46  steve
- *  Fix handling of errors in behavioral lvalues. (PR#28)
- *
- * Revision 1.4  2000/09/10 15:43:59  steve
- *  Some error checking.
- *
- * Revision 1.3  2000/09/10 03:59:59  steve
- *  Agressively merge NetAssign_ within concatenations.
- *
- * Revision 1.2  2000/09/10 02:18:16  steve
- *  elaborate complex l-values
- *
- * Revision 1.1  2000/09/09 15:21:26  steve
- *  move lval elaboration to PExpr virtual methods.
+ * Revision 1.28  2004/08/28 14:59:44  steve
+ *  More detailed error message about bad variable.
 *
+ * Revision 1.27  2003/09/19 03:30:05  steve
+ *  Fix name search in elab_lval.
 */

@@ -17,12 +17,13 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_pexpr.cc,v 1.16 2002/08/12 01:34:59 steve Exp $"
+#ident "$Id: elab_pexpr.cc,v 1.24 2006/06/02 04:48:50 steve Exp $"
 #endif

 # include "config.h"

 # include  "PExpr.h"
+# include  "compiler.h"
 # include  "util.h"

 # include  <iostream>
@@ -61,7 +62,7 @@ NetExpr*PEBinary::elaborate_pexpr (Design*des, NetScope*scope) const
 * expressions can include concatenation expressions. This requires
 * that the subexpressions all have well-defined size (in spite of
 * being in a parameter expression) in order to get a defined
- * value. The sub-expressions themsilves must also be value parameter
+ * value. The sub-expressions themselves must also be value parameter
 * expressions.
 */
 NetEConcat* PEConcat::elaborate_pexpr(Design*des, NetScope*scope) const
@@ -108,11 +109,6 @@ NetEConcat* PEConcat::elaborate_pexpr(Design*des, NetScope*scope) const
 		       << *ex << endl;
 		  des->errors += 1;

-	    } else if (ex->expr_width() == 0) {
-		  cerr << ex->get_line() << ": internal error: "
-		       << "Operand of concatenation has no width: "
-		       << *ex << endl;
-		  des->errors += 1;
 	    }

 	    tmp->set(idx, ex);
@@ -123,7 +119,7 @@ NetEConcat* PEConcat::elaborate_pexpr(Design*des, NetScope*scope) const

 NetExpr*PEFNumber::elaborate_pexpr(Design*des, NetScope*scope) const
 {
-      return elaborate_expr(des, scope);
+      return elaborate_expr(des, scope, -1, false);
 }

 /*
@@ -141,24 +137,42 @@ NetExpr*PEIdent::elaborate_pexpr(Design*des, NetScope*scope) const
      if (path.peek_name(0))
 	    pscope = des->find_scope(scope, path);

-      const NetExpr*ex = pscope->get_parameter(name);
+      perm_string perm_name = lex_strings.make(name);
+      delete name;
+
+      const NetExpr*ex_msb;
+      const NetExpr*ex_lsb;
+      const NetExpr*ex = pscope->get_parameter(perm_name, ex_msb, ex_lsb);
      if (ex == 0) {
 	    cerr << get_line() << ": error: identifier ``" << path_ <<
 		  "'' is not a parameter in " << scope->name() << "." << endl;
 	    des->errors += 1;
-	    delete name;
 	    return 0;
      }

-      if (msb_ || lsb_ || idx_) {
-	    cerr << get_line() << ": error: Cannot bit/part select "
+      NetExpr*res = new NetEParam(des, pscope, perm_name);
+      res->set_line(*this);
+      assert(res);
+
+      if (msb_ && lsb_) {
+	    assert(idx_.empty());
+	    cerr << get_line() << ": sorry: Cannot part select "
 		  "bits of parameters." << endl;
 	    des->errors += 1;
+
+      } else if (!idx_.empty()) {
+	    assert(msb_==0);
+	    assert(lsb_==0);
+	    assert(idx_.size() == 1);
+
+	      /* We have here a bit select. Insert a NetESelect node
+		 to handle it. */
+	    NetExpr*tmp = idx_[0]->elaborate_pexpr(des, scope);
+	    if (tmp != 0) {
+		  res = new NetESelect(res, tmp, 1);
+	    }
      }

-      NetExpr*res = new NetEParam(des, pscope, hname_t(name));
-      assert(res);
-      delete name;
      return res;
 }

@@ -167,13 +181,13 @@ NetExpr*PEIdent::elaborate_pexpr(Design*des, NetScope*scope) const
 */
 NetExpr*PENumber::elaborate_pexpr(Design*des, NetScope*sc) const
 {
-      return elaborate_expr(des, sc);
+      return elaborate_expr(des, sc, -1, false);
 }


 NetEConst* PEString::elaborate_pexpr(Design*des, NetScope*scope) const
 {
-      return elaborate_expr(des, scope);
+      return elaborate_expr(des, scope, -1, false);
 }

 NetETernary* PETernary::elaborate_pexpr(Design*des, NetScope*scope) const
@@ -222,6 +236,34 @@ NetExpr*PEUnary::elaborate_pexpr (Design*des, NetScope*scope) const

 /*
 * $Log: elab_pexpr.cc,v $
+ * Revision 1.24  2006/06/02 04:48:50  steve
+ *  Make elaborate_expr methods aware of the width that the context
+ *  requires of it. In the process, fix sizing of the width of unary
+ *  minus is context determined sizes.
+ *
+ * Revision 1.23  2006/02/02 02:43:58  steve
+ *  Allow part selects of memory words in l-values.
+ *
+ * Revision 1.22  2005/11/27 05:56:20  steve
+ *  Handle bit select of parameter with ranges.
+ *
+ * Revision 1.21  2004/02/20 06:22:56  steve
+ *  parameter keys are per_strings.
+ *
+ * Revision 1.20  2003/05/30 02:55:32  steve
+ *  Support parameters in real expressions and
+ *  as real expressions, and fix multiply and
+ *  divide with real results.
+ *
+ * Revision 1.19  2003/01/27 05:09:17  steve
+ *  Spelling fixes.
+ *
+ * Revision 1.18  2002/12/05 02:14:33  steve
+ *  Support bit select in constant expressions.
+ *
+ * Revision 1.17  2002/11/09 01:40:19  steve
+ *  Postpone parameter width check to evaluation.
+ *
 * Revision 1.16  2002/08/12 01:34:59  steve
 *  conditional ident string using autoconfig.
 *
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2003 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,12 +17,14 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_scope.cc,v 1.17 2002/10/19 22:59:49 steve Exp $"
+#ident "$Id: elab_scope.cc,v 1.41 2006/06/02 04:48:50 steve Exp $"
 #endif

-# include "config.h"
-
+# include  "config.h"
+# include  "compiler.h"
+# include  "netmisc.h"
 # include  <iostream>
+# include  <stdio.h>

 /*
 * Elaboration happens in two passes, generally. The first scans the
@@ -35,14 +37,23 @@
 # include  "PEvent.h"
 # include  "PExpr.h"
 # include  "PGate.h"
+# include  "PGenerate.h"
 # include  "PTask.h"
 # include  "PWire.h"
 # include  "Statement.h"
 # include  "netlist.h"
+# include  "util.h"
 # include  <typeinfo>
+# include  <assert.h>

-bool Module::elaborate_scope(Design*des, NetScope*scope) const
+bool Module::elaborate_scope(Design*des, NetScope*scope,
+			     const replace_t&replacements) const
 {
+      if (debug_scopes) {
+	    cerr << get_line() << ": debug: Elaborate scope "
+		 << scope->name() << "." << endl;
+      }
+
 	// Generate all the parameters that this instance of this
 	// module introduces to the design. This loop elaborates the
 	// parameters, but doesn't evaluate references to
@@ -54,7 +65,7 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 	// the pform and just place a NetEParam placeholder in the
 	// place of the elaborated expression.

-      typedef map<string,param_expr_t>::const_iterator mparm_it_t;
+      typedef map<perm_string,param_expr_t>::const_iterator mparm_it_t;
      typedef map<hname_t,PExpr*>::const_iterator hparm_it_t;


@@ -65,8 +76,8 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 		 ; cur != parameters.end() ;  cur ++) {

 	    NetEParam*tmp = new NetEParam;
-	    if ((*cur).second.msb)
-		  tmp->cast_signed( (*cur).second.signed_flag );
+	    tmp->set_line(*((*cur).second.expr));
+	    tmp->cast_signed( (*cur).second.signed_flag );

 	    scope->set_parameter((*cur).first, tmp, 0, 0, false);
      }
@@ -75,6 +86,7 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 		 ; cur != localparams.end() ;  cur ++) {

 	    NetEParam*tmp = new NetEParam;
+	    tmp->set_line(*((*cur).second.expr));
 	    if ((*cur).second.msb)
 		  tmp->cast_signed( (*cur).second.signed_flag );

@@ -93,6 +105,67 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 	    PExpr*ex = (*cur).second.expr;
 	    assert(ex);

+	    NetExpr*val = ex->elaborate_pexpr(des, scope);
+	    NetExpr*msb = 0;
+	    NetExpr*lsb = 0;
+	    bool signed_flag = (*cur).second.signed_flag;
+
+	      /* If the parameter declaration includes msb and lsb,
+		 then use them to calculate a width for the
+		 result. Then make sure the constant expression of the
+		 parameter value is coerced to have the correct
+		 and defined width. */
+	    if ((*cur).second.msb) {
+		  msb = (*cur).second.msb ->elaborate_pexpr(des, scope);
+		  assert(msb);
+		  lsb = (*cur).second.lsb ->elaborate_pexpr(des, scope);
+	    }
+
+	    if (signed_flag) {
+		    /* If explicitly signed, then say so. */
+		  val->cast_signed(true);
+	    } else if ((*cur).second.msb) {
+		    /* If there is a range, then the signedness comes
+		       from the type and not the expression. */
+		  val->cast_signed(signed_flag);
+	    } else {
+		    /* otherwise, let the expression describe
+		       itself. */
+		  signed_flag = val->has_sign();
+	    }
+
+	    val = scope->set_parameter((*cur).first, val,
+				       msb, lsb, signed_flag);
+	    assert(val);
+	    delete val;
+      }
+
+	/* run parameter replacements that were collected from the
+	   containing scope and meant for me. */
+      for (replace_t::const_iterator cur = replacements.begin()
+		 ; cur != replacements.end() ;  cur ++) {
+
+	    NetExpr*val = (*cur).second;
+	    if (debug_scopes) {
+		  cerr << get_line() << ": debug: "
+		       << "Replace " << (*cur).first
+		       << " with expression " << *val
+		       << " from " << val->get_line() << "." << endl;
+	    }
+	    bool flag = scope->replace_parameter((*cur).first, val);
+	    if (! flag) {
+		  cerr << val->get_line() << ": warning: parameter "
+		       << (*cur).first << " not found in "
+		       << scope->name() << "." << endl;
+	    }
+      }
+
+      for (mparm_it_t cur = localparams.begin()
+		 ; cur != localparams.end() ;  cur ++) {
+
+	    PExpr*ex = (*cur).second.expr;
+	    assert(ex);
+
 	    NetExpr*val = ex->elaborate_pexpr(des, scope);
 	    NetExpr*msb = 0;
 	    NetExpr*lsb = 0;
@@ -117,18 +190,6 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 	    delete val;
      }

-      for (mparm_it_t cur = localparams.begin()
-		 ; cur != localparams.end() ;  cur ++) {
-
-	    PExpr*ex = (*cur).second.expr;
-	    assert(ex);
-
-	    NetExpr*val = ex->elaborate_pexpr(des, scope);
-	    val = scope->set_parameter((*cur).first, val, 0, 0, false);
-	    assert(val);
-	    delete val;
-      }
-
 	// Run through the defparams for this module, elaborate the
 	// expressions in this context and save the result is a table
 	// for later final override.
@@ -136,7 +197,7 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 	// It is OK to elaborate the expressions of the defparam here
 	// because Verilog requires that the expressions only use
 	// local parameter names. It is *not* OK to do the override
-	// here becuase the parameter receiving the assignment may be
+	// here because the parameter receiving the assignment may be
 	// in a scope not discovered by this pass.

      for (hparm_it_t cur = defparms.begin()
@@ -150,18 +211,39 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 	    scope->defparams[(*cur).first] = val;
      }

+	// Evaluate the attributes. Evaluate them in the scope of the
+	// module that the attribute is attached to. Is this correct?
+      unsigned nattr;
+      attrib_list_t*attr = evaluate_attributes(attributes, nattr, des, scope);
+
+      for (unsigned idx = 0 ;  idx < nattr ;  idx += 1)
+	    scope->attribute(attr[idx].key, attr[idx].val);
+
+      delete[]attr;
+
+	// Generate schemes can create new scopes in the form of
+	// generated code. Scan the generate schemes, and *generate*
+	// new scopes, which is slightly different from simple
+	// elaboration.
+
+      typedef list<PGenerate*>::const_iterator generate_it_t;
+      for (generate_it_t cur = generate_schemes.begin()
+		 ; cur != generate_schemes.end() ; cur ++ ) {
+	    (*cur) -> generate_scope(des, scope);
+      }
+

 	// Tasks introduce new scopes, so scan the tasks in this
 	// module. Create a scope for the task and pass that to the
 	// elaborate_scope method of the PTask for detailed
 	// processing.

-      typedef map<string,PTask*>::const_iterator tasks_it_t;
+      typedef map<perm_string,PTask*>::const_iterator tasks_it_t;

      for (tasks_it_t cur = tasks_.begin()
 		 ; cur != tasks_.end() ;  cur ++ ) {

-	    NetScope*task_scope = new NetScope(scope, (*cur).first.c_str(),
+	    NetScope*task_scope = new NetScope(scope, (*cur).first,
 					       NetScope::TASK);
 	    (*cur).second->elaborate_scope(des, task_scope);
      }
@@ -171,12 +253,12 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 	// perspective of scopes. So handle them exactly the same
 	// way.

-      typedef map<string,PFunction*>::const_iterator funcs_it_t;
+      typedef map<perm_string,PFunction*>::const_iterator funcs_it_t;

      for (funcs_it_t cur = funcs_.begin()
 		 ; cur != funcs_.end() ;  cur ++ ) {

-	    NetScope*func_scope = new NetScope(scope, (*cur).first.c_str(),
+	    NetScope*func_scope = new NetScope(scope, (*cur).first,
 					       NetScope::FUNC);
 	    (*cur).second->elaborate_scope(des, func_scope);
      }
@@ -186,7 +268,6 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 	// scan all of them to create those scopes.

      typedef list<PGate*>::const_iterator gates_it_t;
-
      for (gates_it_t cur = gates_.begin()
 		 ; cur != gates_.end() ;  cur ++ ) {

@@ -211,7 +292,7 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 	// elaboration, so do it now. This allows for normal
 	// elaboration to reference these events.

-      for (map<string,PEvent*>::const_iterator et = events.begin()
+      for (map<perm_string,PEvent*>::const_iterator et = events.begin()
 		 ; et != events.end() ;  et ++ ) {

 	    (*et).second->elaborate_scope(des, scope);
@@ -220,6 +301,107 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
      return des->errors == 0;
 }

+bool PGenerate::generate_scope(Design*des, NetScope*container)
+{
+      switch (scheme_type) {
+	  case GS_LOOP:
+	    return generate_scope_loop_(des, container);
+
+	  default:
+	    cerr << get_line() << ": sorry: Generate of this sort"
+		 << " is not supported yet!" << endl;
+	    return false;
+      }
+}
+
+/*
+ * This is the elaborate scope method for a generate loop.
+ */
+bool PGenerate::generate_scope_loop_(Design*des, NetScope*container)
+{
+	// We're going to need a genvar...
+      int genvar;
+
+	// The initial value for the genvar does not need (nor can it
+	// use) the genvar itself, so we can evaluate this expression
+	// the same way any other paramter value is evaluated.
+      NetExpr*init_ex = elab_and_eval(des, container, loop_init, -1);
+      NetEConst*init = dynamic_cast<NetEConst*> (init_ex);
+      if (init == 0) {
+	    cerr << get_line() << ": error: Cannot evaluate genvar"
+		 << " init expression: " << *loop_init << endl;
+	    des->errors += 1;
+	    return false;
+      }
+
+      genvar = init->value().as_long();
+      delete init_ex;
+
+      if (debug_elaborate)
+	    cerr << get_line() << ": debug: genvar init = " << genvar << endl;
+
+      container->genvar_tmp = loop_index;
+      container->genvar_tmp_val = 0;
+      NetExpr*test_ex = elab_and_eval(des, container, loop_test, -1);
+      NetEConst*test = dynamic_cast<NetEConst*>(test_ex);
+      assert(test);
+      while (test->value().as_long()) {
+
+	      // The actual name of the scope includes the genvar so
+	      // that each instance has a unique name in the
+	      // container. The format of using [] is part of the
+	      // Verilog standard.
+	    char name_buf[128];
+	    snprintf(name_buf, sizeof name_buf,
+		     "%s[%d]", scope_name.str(), genvar);
+	    perm_string use_name = lex_strings.make(name_buf);
+
+	    if (debug_elaborate)
+		  cerr << get_line() << ": debug: "
+		       << "Create generated scope " << use_name << endl;
+
+	    NetScope*scope = new NetScope(container, use_name,
+					  NetScope::GENBLOCK);
+
+	      // Set in the scope a localparam for the value of the
+	      // genvar within this instance of the generate
+	      // block. Code within this scope thus has access to the
+	      // genvar as a constant.
+	    {
+		  verinum genvar_verinum(genvar);
+		  genvar_verinum.has_sign(true);
+		  NetEConstParam*gp = new NetEConstParam(scope,
+							 loop_index,
+							 genvar_verinum);
+		  scope->set_localparam(loop_index, gp);
+	    }
+
+	    scope_list_.push_back(scope);
+
+	      // Calculate the step for the loop variable.
+	    NetExpr*step_ex = elab_and_eval(des, container, loop_step, -1);
+	    NetEConst*step = dynamic_cast<NetEConst*>(step_ex);
+	    assert(step);
+	    if (debug_elaborate)
+		  cerr << get_line() << ": debug: genvar step from "
+		       << genvar << " to " << step->value().as_long() << endl;
+
+	    genvar = step->value().as_long();
+	    container->genvar_tmp_val = genvar;
+	    delete step;
+	    delete test_ex;
+	    test_ex = elab_and_eval(des, container, loop_test, -1);
+	    test = dynamic_cast<NetEConst*>(test_ex);
+	    assert(test);
+      }
+
+	// Clear the genvar_tmp field in the scope to reflect that the
+	// genvar is no longer value for evaluating expressions.
+      container->genvar_tmp = perm_string();
+
+      return true;
+}
+
 void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
 {
      if (get_name() == "") {
@@ -236,7 +418,7 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
 	// about to create, and if I find it then somebody beat me to
 	// it.

-      if (NetScope*tmp = sc->child(get_name())) {
+      if (sc->child(get_name())) {
 	    cerr << get_line() << ": error: Instance/Scope name " <<
 		  get_name() << " already used in this context." <<
 		  endl;
@@ -266,79 +448,145 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
 	    return;
      }

-	// Create the new scope as a MODULE with my name.
-      NetScope*my_scope = new NetScope(sc, get_name().c_str(), NetScope::MODULE);
-      my_scope->set_module_name(mod->mod_name());
+      NetExpr*mse = msb_ ? elab_and_eval(des, sc, msb_, -1) : 0;
+      NetExpr*lse = lsb_ ? elab_and_eval(des, sc, lsb_, -1) : 0;
+      NetEConst*msb = dynamic_cast<NetEConst*> (mse);
+      NetEConst*lsb = dynamic_cast<NetEConst*> (lse);

-	// Set time units and precision.
-      my_scope->time_unit(mod->time_unit);
-      my_scope->time_precision(mod->time_precision);
-      des->set_precision(mod->time_precision);
+      assert( (msb == 0) || (lsb != 0) );

-	// This call actually arranges for the description of the
-	// module type to process this instance and handle parameters
-	// and sub-scopes that might occur. Parameters are also
-	// created in that scope, as they exist. (I'll override them
-	// later.)
-      mod->elaborate_scope(des, my_scope);
+      long instance_low  = 0;
+      long instance_high = 0;
+      long instance_count  = 1;
+      bool instance_array = false;

-	// Look for module parameter replacements. The "replace" map
-	// maps parameter name to replacement expression that is
-	// passed. It is built up by the ordered overrices or named
-	// overrides.
+      if (msb) {
+	    instance_array = true;
+	    instance_high = msb->value().as_long();
+	    instance_low  = lsb->value().as_long();
+	    if (instance_high > instance_low)
+		  instance_count = instance_high - instance_low + 1;
+	    else
+		  instance_count = instance_low - instance_high + 1;

-      typedef map<string,PExpr*>::const_iterator mparm_it_t;
-      map<string,PExpr*> replace;
+	    delete mse;
+	    delete lse;
+      }

+      NetScope::scope_vec_t instances (instance_count);
+      if (debug_scopes) {
+	    cerr << get_line() << ": debug: Create " << instance_count
+		 << " instances of " << get_name()
+		 << "." << endl;
+      }

-	// Positional parameter overrides are matched to parameter
-	// names by using the param_names list of parameter
-	// names. This is an ordered list of names so the first name
-	// is parameter 0, the second parameter 1, and so on.
+	// Run through the module instances, and make scopes out of
+	// them. Also do parameter overrides that are done on the
+	// instantiation line.
+      for (int idx = 0 ;  idx < instance_count ;  idx += 1) {

-      if (overrides_) {
-	    assert(parms_ == 0);
-	    list<string>::const_iterator cur = mod->param_names.begin();
-	    unsigned idx = 0;
-	    for (;;) {
-		  if (idx >= overrides_->count())
-			break;
-		  if (cur == mod->param_names.end())
-			break;
+	    perm_string use_name = get_name();

-		  replace[*cur] = (*overrides_)[idx];
+	    if (instance_array) {
+		  char name_buf[128];
+		  int instance_idx = idx;
+		  if (instance_low < instance_high)
+			instance_idx = instance_low + idx;
+		  else
+			instance_idx = instance_low - idx;

-		  idx += 1;
-		  cur ++;
+		  snprintf(name_buf, sizeof name_buf,
+			   "%s[%d]", get_name().str(), instance_idx);
+		  use_name = lex_strings.make(name_buf);
 	    }
-      }

-	// Named parameter overrides carry a name with each override
-	// so the mapping into the replace list is much easier.
-      if (parms_) {
-	    assert(overrides_ == 0);
-	    for (unsigned idx = 0 ;  idx < nparms_ ;  idx += 1)
-		  replace[parms_[idx].name] = parms_[idx].parm;
-
-      }
-
-
-	// And here we scan the replacements we collected. Elaborate
-	// the expression in my context, then replace the sub-scope
-	// parameter value with the new expression.
-
-      for (mparm_it_t cur = replace.begin()
-		 ; cur != replace.end() ;  cur ++ ) {
-
-	    PExpr*tmp = (*cur).second;
-	    NetExpr*val = tmp->elaborate_pexpr(des, sc);
-	    bool flag = my_scope->replace_parameter((*cur).first, val);
-	    if (! flag) {
-		  cerr << val->get_line() << ": warning: parameter "
-		       << (*cur).first << " not found in "
-		       << sc->name() << "." << endl;
+	    if (debug_scopes) {
+		  cerr << get_line() << ": debug: Module instance " << use_name
+		       << " becomes child of " << sc->name()
+		       << "." << endl;
 	    }
+
+	      // Create the new scope as a MODULE with my name.
+	    NetScope*my_scope = new NetScope(sc, use_name, NetScope::MODULE);
+	    my_scope->set_module_name(mod->mod_name());
+	    my_scope->default_nettype(mod->default_nettype);
+
+	    instances[idx] = my_scope;
+
+	      // Set time units and precision.
+	    my_scope->time_unit(mod->time_unit);
+	    my_scope->time_precision(mod->time_precision);
+	    des->set_precision(mod->time_precision);
+
+	      // Look for module parameter replacements. The "replace" map
+	      // maps parameter name to replacement expression that is
+	      // passed. It is built up by the ordered overrides or named
+	      // overrides.
+
+	    typedef map<perm_string,PExpr*>::const_iterator mparm_it_t;
+	    map<perm_string,PExpr*> replace;
+
+
+	      // Positional parameter overrides are matched to parameter
+	      // names by using the param_names list of parameter
+	      // names. This is an ordered list of names so the first name
+	      // is parameter 0, the second parameter 1, and so on.
+
+	    if (overrides_) {
+		  assert(parms_ == 0);
+		  list<perm_string>::const_iterator cur
+			= mod->param_names.begin();
+		  unsigned idx = 0;
+		  for (;;) {
+			if (idx >= overrides_->count())
+			      break;
+			if (cur == mod->param_names.end())
+			      break;
+
+			replace[*cur] = (*overrides_)[idx];
+
+			idx += 1;
+			cur ++;
+		  }
+	    }
+
+	      // Named parameter overrides carry a name with each override
+	      // so the mapping into the replace list is much easier.
+	    if (parms_) {
+		  assert(overrides_ == 0);
+		  for (unsigned idx = 0 ;  idx < nparms_ ;  idx += 1)
+			replace[parms_[idx].name] = parms_[idx].parm;
+
+	    }
+
+
+	    Module::replace_t replace_net;
+
+	      // And here we scan the replacements we collected. Elaborate
+	      // the expression in my context, then replace the sub-scope
+	      // parameter value with the new expression.
+
+	    for (mparm_it_t cur = replace.begin()
+		       ; cur != replace.end() ;  cur ++ ) {
+
+		  PExpr*tmp = (*cur).second;
+		  NetExpr*val = tmp->elaborate_pexpr(des, sc);
+		  replace_net[(*cur).first] = val;
+	    }
+
+	      // This call actually arranges for the description of the
+	      // module type to process this instance and handle parameters
+	      // and sub-scopes that might occur. Parameters are also
+	      // created in that scope, as they exist. (I'll override them
+	      // later.)
+	    mod->elaborate_scope(des, my_scope, replace_net);
+
      }
+
+	/* Stash the instance array of scopes into the parent
+	   scope. Later elaboration passes will use this vector to
+	   further elaborate the array. */
+      sc->instance_arrays[get_name()] = instances;
 }

 /*
@@ -357,6 +605,10 @@ void PEvent::elaborate_scope(Design*des, NetScope*scope) const

 void PFunction::elaborate_scope(Design*des, NetScope*scope) const
 {
+      assert(scope->type() == NetScope::FUNC);
+
+      if (statement_)
+	    statement_->elaborate_scope(des, scope);
 }

 void PTask::elaborate_scope(Design*des, NetScope*scope) const
@@ -386,8 +638,8 @@ void PBlock::elaborate_scope(Design*des, NetScope*scope) const
 {
      NetScope*my_scope = scope;

-      if (name_ != "") {
-	    my_scope = new NetScope(scope, name_.c_str(), bl_type_==BL_PAR
+      if (name_ != 0) {
+	    my_scope = new NetScope(scope, name_, bl_type_==BL_PAR
 				    ? NetScope::FORK_JOIN
 				    : NetScope::BEGIN_END);
      }
@@ -398,7 +650,7 @@ void PBlock::elaborate_scope(Design*des, NetScope*scope) const
 }

 /*
- * The case statement itseof does not introduce scope, but contains
+ * The case statement itself does not introduce scope, but contains
 * other statements that may be named blocks. So scan the case items
 * with the elaborate_scope method.
 */
@@ -496,6 +748,84 @@ void PWhile::elaborate_scope(Design*des, NetScope*scope) const

 /*
 * $Log: elab_scope.cc,v $
+ * Revision 1.41  2006/06/02 04:48:50  steve
+ *  Make elaborate_expr methods aware of the width that the context
+ *  requires of it. In the process, fix sizing of the width of unary
+ *  minus is context determined sizes.
+ *
+ * Revision 1.40  2006/04/12 05:05:03  steve
+ *  Use elab_and_eval to evaluate genvar expressions.
+ *
+ * Revision 1.39  2006/04/10 00:37:42  steve
+ *  Add support for generate loops w/ wires and gates.
+ *
+ * Revision 1.38  2006/03/30 01:49:07  steve
+ *  Fix instance arrays indexed by overridden parameters.
+ *
+ * Revision 1.37  2006/03/18 22:53:38  steve
+ *  Support more parameter syntax.
+ *
+ * Revision 1.36  2005/07/11 16:56:50  steve
+ *  Remove NetVariable and ivl_variable_t structures.
+ *
+ * Revision 1.35  2004/09/10 00:15:17  steve
+ *  Missing stdio.h header for warnings.
+ *
+ * Revision 1.34  2004/09/05 17:44:41  steve
+ *  Add support for module instance arrays.
+ *
+ * Revision 1.33  2004/08/26 04:02:03  steve
+ *  Add support for localparam ranges.
+ *
+ * Revision 1.32  2004/06/13 04:56:54  steve
+ *  Add support for the default_nettype directive.
+ *
+ * Revision 1.31  2004/05/25 19:21:06  steve
+ *  More identifier lists use perm_strings.
+ *
+ * Revision 1.30  2004/02/20 06:22:56  steve
+ *  parameter keys are per_strings.
+ *
+ * Revision 1.29  2004/02/19 07:06:57  steve
+ *  LPM, logic and Variables have perm_string names.
+ *
+ * Revision 1.28  2004/02/18 17:11:55  steve
+ *  Use perm_strings for named langiage items.
+ *
+ * Revision 1.27  2003/09/13 01:01:51  steve
+ *  Spelling fixes.
+ *
+ * Revision 1.26  2003/08/28 04:11:17  steve
+ *  Spelling patch.
+ *
+ * Revision 1.25  2003/06/24 01:38:02  steve
+ *  Various warnings fixed.
+ *
+ * Revision 1.24  2003/06/20 00:53:19  steve
+ *  Module attributes from the parser
+ *  through to elaborated form.
+ *
+ * Revision 1.23  2003/06/16 00:34:08  steve
+ *  Functions can have sub-scope.
+ *
+ * Revision 1.22  2003/06/13 19:10:46  steve
+ *  Properly manage real variables in subscopes.
+ *
+ * Revision 1.21  2003/05/30 02:55:32  steve
+ *  Support parameters in real expressions and
+ *  as real expressions, and fix multiply and
+ *  divide with real results.
+ *
+ * Revision 1.20  2003/03/06 00:28:41  steve
+ *  All NetObj objects have lex_string base names.
+ *
+ * Revision 1.19  2003/01/27 05:09:17  steve
+ *  Spelling fixes.
+ *
+ * Revision 1.18  2003/01/26 21:15:58  steve
+ *  Rework expression parsing and elaboration to
+ *  accommodate real/realtime values and expressions.
+ *
 * Revision 1.17  2002/10/19 22:59:49  steve
 *  Redo the parameter vector support to allow
 *  parameter names in range expressions.
@@ -515,48 +845,5 @@ void PWhile::elaborate_scope(Design*des, NetScope*scope) const
 * Revision 1.12  2001/12/03 04:47:14  steve
 *  Parser and pform use hierarchical names as hname_t
 *  objects instead of encoded strings.
- *
- * Revision 1.11  2001/10/20 05:21:51  steve
- *  Scope/module names are char* instead of string.
- *
- * Revision 1.10  2001/10/09 02:01:04  steve
- *  Tasks can have sub-scopes.
- *
- * Revision 1.9  2001/07/25 03:10:49  steve
- *  Create a config.h.in file to hold all the config
- *  junk, and support gcc 3.0. (Stephan Boettcher)
- *
- * Revision 1.8  2001/04/28 23:18:08  steve
- *  UDP instances need not have user supplied names.
- *
- * Revision 1.7  2000/12/16 01:45:48  steve
- *  Detect recursive instantiations (PR#2)
- *
- * Revision 1.6  2000/07/30 18:25:43  steve
- *  Rearrange task and function elaboration so that the
- *  NetTaskDef and NetFuncDef functions are created during
- *  signal enaboration, and carry these objects in the
- *  NetScope class instead of the extra, useless map in
- *  the Design class.
- *
- * Revision 1.5  2000/07/22 22:09:03  steve
- *  Parse and elaborate timescale to scopes.
- *
- * Revision 1.4  2000/04/09 17:44:30  steve
- *  Catch event declarations during scope elaborate.
- *
- * Revision 1.3  2000/03/12 17:09:41  steve
- *  Support localparam.
- *
- * Revision 1.2  2000/03/11 03:25:52  steve
- *  Locate scopes in statements.
- *
- * Revision 1.1  2000/03/08 04:36:53  steve
- *  Redesign the implementation of scopes and parameters.
- *  I now generate the scopes and notice the parameters
- *  in a separate pass over the pform. Once the scopes
- *  are generated, I can process overrides and evalutate
- *  paremeters before elaboration begins.
- *
 */

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2004 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_sig.cc,v 1.25 2002/08/12 01:34:59 steve Exp $"
+#ident "$Id: elab_sig.cc,v 1.42 2006/06/02 04:48:50 steve Exp $"
 #endif

 # include "config.h"
@@ -27,8 +27,10 @@
 # include  "Module.h"
 # include  "PExpr.h"
 # include  "PGate.h"
+# include  "PGenerate.h"
 # include  "PTask.h"
 # include  "PWire.h"
+# include  "compiler.h"
 # include  "netlist.h"
 # include  "netmisc.h"
 # include  "util.h"
@@ -157,6 +159,16 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
 		  des->errors += 1;
 	    }

+      }
+
+	// Run through all the generate schemes to enaborate the
+	// signals that they hold. Note that the generate schemes hold
+	// the scopes that they instantiated, so we don't pass any
+	// scope in.
+      typedef list<PGenerate*>::const_iterator generate_it_t;
+      for (generate_it_t cur = generate_schemes.begin()
+		 ; cur != generate_schemes.end() ; cur ++ ) {
+	    (*cur) -> elaborate_sig(des);
      }

 	// Get all the gates of the module and elaborate them by
@@ -174,7 +186,7 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
      }


-      typedef map<string,PFunction*>::const_iterator mfunc_it_t;
+      typedef map<perm_string,PFunction*>::const_iterator mfunc_it_t;

      for (mfunc_it_t cur = funcs_.begin()
 		 ; cur != funcs_.end() ;  cur ++) {
@@ -195,7 +207,7 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
 	// elaborate the ports of the tasks defined within this
 	// module. Run through them now.

-      typedef map<string,PTask*>::const_iterator mtask_it_t;
+      typedef map<perm_string,PTask*>::const_iterator mtask_it_t;

      for (mtask_it_t cur = tasks_.begin()
 		 ; cur != tasks_.end() ;  cur ++) {
@@ -210,31 +222,80 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
 bool PGModule::elaborate_sig_mod_(Design*des, NetScope*scope,
 				  Module*rmod) const
 {
-	// Missing module instance names have already been rejected.
-      assert(get_name() != "");
+      bool flag = true;
+
+      NetScope::scope_vec_t instance = scope->instance_arrays[get_name()];
+
+      for (unsigned idx = 0 ;  idx < instance.count() ;  idx += 1) {
+	      // I know a priori that the elaborate_scope created the scope
+	      // already, so just look it up as a child of the current scope.
+	    NetScope*my_scope = instance[idx];
+	    assert(my_scope);
+
+	    if (my_scope->parent() != scope) {
+		  cerr << get_line() << ": internal error: "
+		       << "Instance " << my_scope->name()
+		       << " is in parent " << my_scope->parent()->name()
+		       << " instead of " << scope->name()
+		       << endl;
+	    }
+	    assert(my_scope->parent() == scope);
+
+	    if (! rmod->elaborate_sig(des, my_scope))
+		  flag = false;

-      if (msb_) {
-	    cerr << get_line() << ": sorry: Module instantiation arrays "
-		  "are not yet supported." << endl;
-	    des->errors += 1;
-	    return false;
      }

-
-	// I know a priori that the elaborate_scope created the scope
-	// already, so just look it up as a child of the current scope.
-      NetScope*my_scope = scope->child(get_name());
-      assert(my_scope);
-
-      return rmod->elaborate_sig(des, my_scope);
+      return flag;
 }

+bool PGenerate::elaborate_sig(Design*des) const
+{
+      bool flag = true;
+
+      typedef list<NetScope*>::const_iterator scope_list_it_t;
+      for (scope_list_it_t cur = scope_list_.begin()
+		 ; cur != scope_list_.end() ; cur ++ ) {
+
+	    if (debug_elaborate)
+		  cerr << get_line() << ": debug: Elaborate nets in "
+		       << "scope " << (*cur)->name() << endl;
+	    flag = elaborate_sig_(des, *cur) & flag;
+      }
+
+      return flag;
+}
+
+bool PGenerate::elaborate_sig_(Design*des, NetScope*scope) const
+{
+	// Scan the declared PWires to elaborate the obvious signals
+	// in the current scope.
+      typedef map<hname_t,PWire*>::const_iterator wires_it_t;
+      for (wires_it_t wt = wires.begin()
+		 ; wt != wires.end() ;  wt ++ ) {
+
+	    PWire*cur = (*wt).second;
+
+	    if (debug_elaborate)
+		  cerr << get_line() << ": debug: Elaborate PWire "
+		       << cur->path() << " in scope " << scope->name() << endl;
+
+	    cur->elaborate_sig(des, scope);
+      }
+
+      return true;
+}
+
+
 /*
- * A function definition exists within an elaborated module.
+ * A function definition exists within an elaborated module. This
+ * matters when elaborating signals, as the ports of the function are
+ * created as signals/variables for each instance of the
+ * function. That is why PFunction has an elaborate_sig method.
 */
 void PFunction::elaborate_sig(Design*des, NetScope*scope) const
 {
-      string fname = scope->basename();
+      perm_string fname = scope->basename();
      assert(scope->type() == NetScope::FUNC);

 	/* Make sure the function has at least one input port. If it
@@ -248,21 +309,86 @@ void PFunction::elaborate_sig(Design*des, NetScope*scope) const
 	    des->errors += 1;
      }

-      svector<NetNet*>ports (ports_? ports_->count()+1 : 1);
+      NetNet*ret_sig = 0;

-	/* Get the reg for the return value. I know the name of the
-	   reg variable, and I know that it is in this scope, so look
-	   it up directly. */
-      ports[0] = scope->find_signal(scope->basename());
-      if (ports[0] == 0) {
-	    cerr << get_line() << ": internal error: function scope "
-		 << scope->name() << " is missing return reg "
-		 << fname << "." << endl;
-	    scope->dump(cerr);
-	    des->errors += 1;
-	    return;
+	/* Create the signals/variables of the return value and write
+	   them into the function scope. */
+      switch (return_type_.type) {
+
+	  case PTF_REG:
+	    if (return_type_.range) {
+		  NetExpr*me = elab_and_eval(des, scope,
+					     (*return_type_.range)[0], -1);
+		  assert(me);
+		  NetExpr*le = elab_and_eval(des, scope,
+					     (*return_type_.range)[1], -1);
+		  assert(le);
+
+		  long mnum = 0, lnum = 0;
+		  if (NetEConst*tmp = dynamic_cast<NetEConst*>(me)) {
+			mnum = tmp->value().as_long();
+		  } else {
+			cerr << me->get_line() << ": error: "
+			      "Unable to evaluate constant expression "
+			     << *me << "." << endl;
+			des->errors += 1;
+		  }
+
+		  if (NetEConst*tmp = dynamic_cast<NetEConst*>(le)) {
+			lnum = tmp->value().as_long();
+		  } else {
+			cerr << le->get_line() << ": error: "
+			      "Unable to evaluate constant expression "
+			     << *le << "." << endl;
+			des->errors += 1;
+		  }
+
+		  ret_sig = new NetNet(scope, fname, NetNet::REG, mnum, lnum);
+
+	    } else {
+		  ret_sig = new NetNet(scope, fname, NetNet::REG);
+	    }
+	    ret_sig->set_line(*this);
+	    ret_sig->port_type(NetNet::POUTPUT);
+	    ret_sig->data_type(IVL_VT_LOGIC);
+	    break;
+
+	  case PTF_INTEGER:
+	    ret_sig = new NetNet(scope, fname, NetNet::REG, INTEGER_WIDTH);
+	    ret_sig->set_line(*this);
+	    ret_sig->set_signed(true);
+	    ret_sig->set_isint(true);
+	    ret_sig->port_type(NetNet::POUTPUT);
+	    ret_sig->data_type(IVL_VT_LOGIC);
+	    break;
+
+	  case PTF_TIME:
+	    ret_sig = new NetNet(scope, fname, NetNet::REG, 64);
+	    ret_sig->set_line(*this);
+	    ret_sig->set_signed(false);
+	    ret_sig->set_isint(false);
+	    ret_sig->port_type(NetNet::POUTPUT);
+	    ret_sig->data_type(IVL_VT_LOGIC);
+	    break;
+
+	  case PTF_REAL:
+	  case PTF_REALTIME:
+	    ret_sig = new NetNet(scope, fname, NetNet::REG, 1);
+	    ret_sig->set_line(*this);
+	    ret_sig->set_signed(true);
+	    ret_sig->set_isint(false);
+	    ret_sig->port_type(NetNet::POUTPUT);
+	    ret_sig->data_type(IVL_VT_REAL);
+	    break;
+
+	  default:
+	    cerr << get_line() << ": internal error: I don't know how "
+		 << "to deal with return type of function "
+		 << scope->basename() << "." << endl;
      }

+      svector<NetNet*>ports (ports_? ports_->count() : 0);
+
      if (ports_)
 	    for (unsigned idx = 0 ;  idx < ports_->count() ;  idx += 1) {

@@ -271,8 +397,8 @@ void PFunction::elaborate_sig(Design*des, NetScope*scope) const
 		       as two components: <func>.<port>. */

 		  hname_t path = (*ports_)[idx]->path();
-		  string pname = path.peek_name(1);
-		  string ppath = path.peek_name(0);
+		  perm_string pname = lex_strings.make(path.peek_name(1));
+		  perm_string ppath = lex_strings.make(path.peek_name(0));

 		  if (ppath != scope->basename()) {
 			cerr << get_line() << ": internal error: function "
@@ -288,14 +414,18 @@ void PFunction::elaborate_sig(Design*des, NetScope*scope) const
 			     << scope->name() << " is missing port "
 			     << pname << "." << endl;
 			scope->dump(cerr);
+			cerr << get_line() << ": Continuing..." << endl;
 			des->errors += 1;
 		  }

-		  ports[idx+1] = tmp;
+		  ports[idx] = tmp;
 	    }


-      NetFuncDef*def = new NetFuncDef(scope, ports);
+      NetFuncDef*def = 0;
+      if (ret_sig)  def = new NetFuncDef(scope, ret_sig, ports);
+
+      assert(def);
      scope->set_func_def(def);
 }

@@ -360,12 +490,13 @@ bool PGate::elaborate_sig(Design*des, NetScope*scope) const
 /*
 * Elaborate a source wire. The "wire" is the declaration of wires,
 * registers, ports and memories. The parser has already merged the
- * multiple properties of a wire (i.e. "input wire") so come the
+ * multiple properties of a wire (i.e., "input wire") so come the
 * elaboration this creates an object in the design that represent the
 * defined item.
 */
 void PWire::elaborate_sig(Design*des, NetScope*scope) const
 {
+
 	/* The parser may produce hierarchical names for wires. I here
 	   follow the scopes down to the base where I actually want to
 	   elaborate the NetNet object. */
@@ -373,7 +504,13 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
        free(tmp_path.remove_tail_name());
 	for (unsigned idx = 0 ;  tmp_path.peek_name(idx) ;  idx += 1) {
 	      scope = scope->child(tmp_path.peek_name(idx));
-	      assert(scope);
+
+	      if (scope == 0) {
+		    cerr << get_line() << ": internal error: "
+			 << "Bad scope component for name "
+			 << hname_ << endl;
+		    assert(scope);
+	      }
 	}
      }

@@ -391,12 +528,12 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
 	    svector<long>mnum (msb_.count());
 	    svector<long>lnum (msb_.count());
 	      /* There may be places where the signal is declared as a
-		 scaler. Count those here, for consistency check
+		 scalar. Count those here, for consistency check
 		 later. */
 	    unsigned count_scalars = 0;

 	      /* There may be multiple declarations of ranges, because
-		 the symbol may have its range declared in i.e. input
+		 the symbol may have its range declared in e.g., input
 		 and reg declarations. Calculate *all* the numbers
 		 here. I will resolve the values later. */

@@ -411,7 +548,7 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
 		  }

 		  NetEConst*tmp;
-		  NetExpr*texpr = elab_and_eval(des, scope, msb_[idx]);
+		  NetExpr*texpr = elab_and_eval(des, scope, msb_[idx], -1);

 		  tmp = dynamic_cast<NetEConst*>(texpr);
 		  if (tmp == 0) {
@@ -425,7 +562,7 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
 		  mnum[idx] = tmp->value().as_long();
 		  delete texpr;

-		  texpr = elab_and_eval(des, scope, lsb_[idx]);
+		  texpr = elab_and_eval(des, scope, lsb_[idx], -1);
 		  tmp = dynamic_cast<NetEConst*>(texpr);
 		  if (tmp == 0) {
 			cerr << msb_[idx]->get_line() << ": error: "
@@ -479,15 +616,17 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
      attrib_list_t*attrib_list = evaluate_attributes(attributes, nattrib,
 						      des, scope);

+	/* If the ident has idx expressions, then this is a
+	   memory. It can only have the idx registers after the msb
+	   and lsb expressions are filled. And, if it has one index,
+	   it has both. */
      if (lidx_ || ridx_) {
 	    assert(lidx_ && ridx_);

-	      // If the register has indices, then this is a
-	      // memory. Create the memory object.
-	    verinum*lval = lidx_->eval_const(des, scope);
-	    verinum*rval = ridx_->eval_const(des, scope);
+	    NetExpr*lexp = elab_and_eval(des, scope, lidx_, -1);
+	    NetExpr*rexp = elab_and_eval(des, scope, ridx_, -1);

-	    if ((lval == 0) || (rval == 0)) {
+	    if ((lexp == 0) || (rexp == 0)) {
 		  cerr << get_line() << ": internal error: There is "
 		       << "a problem evaluating indices for ``"
 		       << hname_.peek_tail_name() << "''." << endl;
@@ -495,29 +634,85 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
 		  return;
 	    }

-	    assert(lval);
-	    assert(rval);
+	    NetEConst*lcon = dynamic_cast<NetEConst*> (lexp);
+	    NetEConst*rcon = dynamic_cast<NetEConst*> (rexp);

-	    string name = hname_.peek_tail_name();
+	    if ((lcon == 0) || (rcon == 0)) {
+		  cerr << get_line() << ": internal error: The indices "
+		       << "are not constant for memory ``"
+		       << hname_.peek_tail_name() << "''." << endl;
+		  des->errors += 1;
+		  return;
+	    }

-	    long lnum = lval->as_long();
-	    long rnum = rval->as_long();
-	    delete lval;
-	    delete rval;
-	    NetMemory*sig = new NetMemory(scope, name, wid, lnum, rnum);
+	    verinum lval = lcon->value();
+	    verinum rval = rcon->value();
+
+	    delete lexp;
+	    delete rexp;
+
+	    perm_string name = lex_strings.make(hname_.peek_tail_name());
+
+	    long lnum = lval.as_long();
+	    long rnum = rval.as_long();
+
+	    new NetMemory(scope, name, wid, lnum, rnum);
+	      // The constructor automatically adds the memory object
+	      // to the scope. Do I need to set line number information?

      } else {

-	      /* Make a hierarchical make for the signal. */
-	    string name = scope->name();
-	    name = name + "." + hname_.peek_tail_name();
+	      /* If the net type is supply0 or supply1, replace it
+		 with a simple wire with a pulldown/pullup with supply
+		 strength. In other words, transform:
+
+		 supply0 foo;
+
+		 to:
+
+		 wire foo;
+		 pulldown #(supply0) (foo);
+
+		 This reduces the backend burden, and behaves exactly
+		 the same. */
+
+	    NetLogic*pull = 0;
+	    if (wtype == NetNet::SUPPLY0 || wtype == NetNet::SUPPLY1) {
+		  NetLogic::TYPE pull_type = (wtype==NetNet::SUPPLY1)
+			? NetLogic::PULLUP
+			: NetLogic::PULLDOWN;
+		  pull = new NetLogic(scope, scope->local_symbol(),
+				      1, pull_type, wid);
+		  pull->set_line(*this);
+		  pull->pin(0).drive0(Link::SUPPLY);
+		  pull->pin(0).drive1(Link::SUPPLY);
+		  des->add_node(pull);
+		  wtype = NetNet::WIRE;
+
+		  if (debug_elaborate) {
+			cerr << get_line() << ": debug: "
+			     << "Generate a SUPPLY pulldown for the "
+			     << "supply0 net." << endl;
+		  }
+	    }
+
+	    perm_string name = lex_strings.make(hname_.peek_tail_name());
+	    if (debug_elaborate) {
+		  cerr << get_line() << ": debug: Create signal "
+		       << name << "["<<msb<<":"<<lsb<<"]"
+		       << " in scope " << scope->name() << endl;
+	    }

 	    NetNet*sig = new NetNet(scope, name, wtype, msb, lsb);
+	    sig->data_type(data_type_);
 	    sig->set_line(*this);
 	    sig->port_type(port_type_);
 	    sig->set_signed(get_signed());
 	    sig->set_isint(get_isint());

+	    if (pull)
+		  connect(sig->pin(0), pull->pin(0));
+
 	    for (unsigned idx = 0 ;  idx < nattrib ;  idx += 1)
 		  sig->attribute(attrib_list[idx].key, attrib_list[idx].val);
      }
@@ -525,6 +720,63 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const

 /*
 * $Log: elab_sig.cc,v $
+ * Revision 1.42  2006/06/02 04:48:50  steve
+ *  Make elaborate_expr methods aware of the width that the context
+ *  requires of it. In the process, fix sizing of the width of unary
+ *  minus is context determined sizes.
+ *
+ * Revision 1.41  2006/04/10 00:37:42  steve
+ *  Add support for generate loops w/ wires and gates.
+ *
+ * Revision 1.40  2005/07/11 16:56:50  steve
+ *  Remove NetVariable and ivl_variable_t structures.
+ *
+ * Revision 1.39  2005/07/07 16:22:49  steve
+ *  Generalize signals to carry types.
+ *
+ * Revision 1.38  2005/02/13 01:15:07  steve
+ *  Replace supply nets with wires connected to pullup/down supply devices.
+ *
+ * Revision 1.37  2004/12/11 02:31:25  steve
+ *  Rework of internals to carry vectors through nexus instead
+ *  of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ *  down this path.
+ *
+ * Revision 1.36  2004/09/27 22:34:10  steve
+ *  Cleanup and factoring of autoconf.
+ *
+ * Revision 1.35  2004/09/05 17:44:41  steve
+ *  Add support for module instance arrays.
+ *
+ * Revision 1.34  2004/05/31 23:34:37  steve
+ *  Rewire/generalize parsing an elaboration of
+ *  function return values to allow for better
+ *  speed and more type support.
+ *
+ * Revision 1.33  2004/02/18 17:11:55  steve
+ *  Use perm_strings for named langiage items.
+ *
+ * Revision 1.32  2003/09/20 05:24:00  steve
+ *  Evaluate memory index constants using elab_and_eval.
+ *
+ * Revision 1.31  2003/07/15 03:49:22  steve
+ *  Spelling fixes.
+ *
+ * Revision 1.30  2003/06/24 01:38:02  steve
+ *  Various warnings fixed.
+ *
+ * Revision 1.29  2003/06/21 01:21:43  steve
+ *  Harmless fixup of warnings.
+ *
+ * Revision 1.28  2003/03/06 00:28:41  steve
+ *  All NetObj objects have lex_string base names.
+ *
+ * Revision 1.27  2003/01/30 16:23:07  steve
+ *  Spelling fixes.
+ *
+ * Revision 1.26  2003/01/27 05:09:17  steve
+ *  Spelling fixes.
+ *
 * Revision 1.25  2002/08/12 01:34:59  steve
 *  conditional ident string using autoconfig.
 *
@@ -577,46 +829,5 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
 * Revision 1.11  2001/02/10 20:29:39  steve
 *  In the context of range declarations, use elab_and_eval instead
 *  of the less robust eval_const methods.
- *
- * Revision 1.10  2001/01/13 22:20:08  steve
- *  Parse parameters within nested scopes.
- *
- * Revision 1.9  2001/01/07 07:00:31  steve
- *  Detect port direction attached to non-ports.
- *
- * Revision 1.8  2001/01/04 04:47:51  steve
- *  Add support for << is signal indices.
- *
- * Revision 1.7  2000/12/11 00:31:43  steve
- *  Add support for signed reg variables,
- *  simulate in t-vvm signed comparisons.
- *
- * Revision 1.6  2000/12/04 17:37:04  steve
- *  Add Attrib class for holding NetObj attributes.
- *
- * Revision 1.5  2000/11/20 00:58:40  steve
- *  Add support for supply nets (PR#17)
- *
- * Revision 1.4  2000/09/07 22:37:48  steve
- *  ack, detect when lval fails.
- *
- * Revision 1.3  2000/07/30 18:25:43  steve
- *  Rearrange task and function elaboration so that the
- *  NetTaskDef and NetFuncDef functions are created during
- *  signal enaboration, and carry these objects in the
- *  NetScope class instead of the extra, useless map in
- *  the Design class.
- *
- * Revision 1.2  2000/07/14 06:12:57  steve
- *  Move inital value handling from NetNet to Nexus
- *  objects. This allows better propogation of inital
- *  values.
- *
- *  Clean up constant propagation  a bit to account
- *  for regs that are not really values.
- *
- * Revision 1.1  2000/05/02 16:27:38  steve
- *  Move signal elaboration to a seperate pass.
- *
 */

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2005 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: emit.cc,v 1.69 2002/08/12 01:34:59 steve Exp $"
+#ident "$Id: emit.cc,v 1.87 2006/06/18 04:15:50 steve Exp $"
 #endif

 # include "config.h"
@@ -63,12 +63,6 @@ bool NetCaseCmp::emit_node(struct target_t*tgt) const
      return true;
 }

-bool NetCAssign::emit_node(struct target_t*tgt) const
-{
-      tgt->net_cassign(this);
-      return true;
-}
-
 bool NetCLShift::emit_node(struct target_t*tgt) const
 {
      tgt->lpm_clshift(this);
@@ -81,6 +75,11 @@ bool NetCompare::emit_node(struct target_t*tgt) const
      return true;
 }

+bool NetConcat::emit_node(struct target_t*tgt) const
+{
+      return tgt->concat(this);
+}
+
 bool NetConst::emit_node(struct target_t*tgt) const
 {
      return tgt->net_const(this);
@@ -98,10 +97,9 @@ bool NetFF::emit_node(struct target_t*tgt) const
      return true;
 }

-bool NetForce::emit_node(struct target_t*tgt) const
+bool NetLiteral::emit_node(struct target_t*tgt) const
 {
-      tgt->net_force(this);
-      return true;
+      return tgt->net_literal(this);
 }

 bool NetModulo::emit_node(struct target_t*tgt) const
@@ -122,12 +120,37 @@ bool NetMux::emit_node(struct target_t*tgt) const
      return true;
 }

+bool NetPartSelect::emit_node(struct target_t*tgt) const
+{
+      return tgt->part_select(this);
+}
+
 bool NetRamDq::emit_node(struct target_t*tgt) const
 {
      tgt->lpm_ram_dq(this);
      return true;
 }

+bool NetReplicate::emit_node(struct target_t*tgt) const
+{
+      return tgt->replicate(this);
+}
+
+bool NetSignExtend::emit_node(struct target_t*tgt) const
+{
+      return tgt->sign_extend(this);
+}
+
+bool NetUReduce::emit_node(struct target_t*tgt) const
+{
+      return tgt->ureduce(this);
+}
+
+bool NetSysFunc::emit_node(struct target_t*tgt) const
+{
+      return tgt->net_sysfunction(this);
+}
+
 bool NetUserFunc::emit_node(struct target_t*tgt) const
 {
      return tgt->net_function(this);
@@ -332,23 +355,27 @@ void NetScope::emit_scope(struct target_t*tgt) const
      }
 }

-void NetScope::emit_defs(struct target_t*tgt) const
+bool NetScope::emit_defs(struct target_t*tgt) const
 {
+      bool flag = true;

      switch (type_) {
 	  case MODULE:
 	    for (NetScope*cur = sub_ ;  cur ;  cur = cur->sib_)
-		  cur->emit_defs(tgt);
+		  flag &= cur->emit_defs(tgt);
 	    break;

 	  case FUNC:
-	    tgt->func_def(this);
+	    flag &= tgt->func_def(this);
 	    break;
 	  case TASK:
 	    tgt->task_def(this);
 	    break;
+	  default:  /* BEGIN_END and FORK_JOIN, do nothing */
+	    break;
      }

+      return flag;
 }

 void NetWhile::emit_proc_recurse(struct target_t*tgt) const
@@ -356,42 +383,50 @@ void NetWhile::emit_proc_recurse(struct target_t*tgt) const
      proc_->emit_proc(tgt);
 }

-bool Design::emit(struct target_t*tgt) const
+int Design::emit(struct target_t*tgt) const
 {
-      bool rc = true;
+      int rc = 0;

-      rc = rc && tgt->start_design(this);
-      if (rc == false)
-	    return false;
+      if (tgt->start_design(this) == false)
+	    return -2;

 	// enumerate the scopes
-      for (list<NetScope*>::const_iterator scope = root_scopes_.begin(); 
+      for (list<NetScope*>::const_iterator scope = root_scopes_.begin();
 	   scope != root_scopes_.end(); scope++)
 	    (*scope)->emit_scope(tgt);


 	// emit nodes
+      bool nodes_rc = true;
      if (nodes_) {
 	    NetNode*cur = nodes_->node_next_;
 	    do {
-		  rc = rc && cur->emit_node(tgt);
+		  nodes_rc = nodes_rc && cur->emit_node(tgt);
 		  cur = cur->node_next_;
 	    } while (cur != nodes_->node_next_);
      }


 	// emit task and function definitions
-      for (list<NetScope*>::const_iterator scope = root_scopes_.begin(); 
+      bool tasks_rc = true;
+      for (list<NetScope*>::const_iterator scope = root_scopes_.begin();
 	   scope != root_scopes_.end(); scope++)
-	    (*scope)->emit_defs(tgt);
+	    tasks_rc &= (*scope)->emit_defs(tgt);


 	// emit the processes
+      bool proc_rc = true;
      for (const NetProcTop*idx = procs_ ;  idx ;  idx = idx->next_)
-	    rc = rc && idx->emit(tgt);
+	    proc_rc &= idx->emit(tgt);

-      if (tgt->end_design(this) != 0)
-	    rc = false;
+      rc = tgt->end_design(this);
+
+      if (nodes_rc == false)
+	    return -1;
+      if (tasks_rc == false)
+	    return -2;
+      if (proc_rc == false)
+	  return -3;

      return rc;
 }
@@ -411,6 +446,21 @@ void NetEConst::expr_scan(struct expr_scan_t*tgt) const
      tgt->expr_const(this);
 }

+void NetEConstParam::expr_scan(struct expr_scan_t*tgt) const
+{
+      tgt->expr_param(this);
+}
+
+void NetECReal::expr_scan(struct expr_scan_t*tgt) const
+{
+      tgt->expr_creal(this);
+}
+
+void NetECRealParam::expr_scan(struct expr_scan_t*tgt) const
+{
+      tgt->expr_rparam(this);
+}
+
 void NetEMemory::expr_scan(struct expr_scan_t*tgt) const
 {
      tgt->expr_memory(this);
@@ -422,6 +472,11 @@ void NetEParam::expr_scan(struct expr_scan_t*tgt) const
 	   << endl;
 }

+void NetEEvent::expr_scan(struct expr_scan_t*tgt) const
+{
+      tgt->expr_event(this);
+}
+
 void NetEScope::expr_scan(struct expr_scan_t*tgt) const
 {
      tgt->expr_scope(this);
@@ -447,11 +502,6 @@ void NetESignal::expr_scan(struct expr_scan_t*tgt) const
      tgt->expr_signal(this);
 }

-void NetEBitSel::expr_scan(struct expr_scan_t*tgt) const
-{
-      tgt->expr_subsignal(this);
-}
-
 void NetETernary::expr_scan(struct expr_scan_t*tgt) const
 {
      tgt->expr_ternary(this);
@@ -462,7 +512,7 @@ void NetEUnary::expr_scan(struct expr_scan_t*tgt) const
      tgt->expr_unary(this);
 }

-bool emit(const Design*des, const char*type)
+int emit(const Design*des, const char*type)
 {
      for (unsigned idx = 0 ;  target_table[idx] ;  idx += 1) {
 	    const struct target*tgt = target_table[idx];
@@ -470,132 +520,78 @@ bool emit(const Design*des, const char*type)
 		  return des->emit(tgt->meth);

      }
+
+      cerr << "error: Code generator type " << type
+	   << " not found." << endl;
+      return -1;
 }


 /*
 * $Log: emit.cc,v $
- * Revision 1.69  2002/08/12 01:34:59  steve
- *  conditional ident string using autoconfig.
+ * Revision 1.87  2006/06/18 04:15:50  steve
+ *  Add support for system functions in continuous assignments.
 *
- * Revision 1.68  2002/06/05 03:44:25  steve
- *  Add support for memory words in l-value of
- *  non-blocking assignments, and remove the special
- *  NetAssignMem_ and NetAssignMemNB classes.
+ * Revision 1.86  2005/07/11 16:56:50  steve
+ *  Remove NetVariable and ivl_variable_t structures.
 *
- * Revision 1.67  2002/06/04 05:38:44  steve
- *  Add support for memory words in l-value of
- *  blocking assignments, and remove the special
- *  NetAssignMem class.
+ * Revision 1.85  2005/07/07 16:22:49  steve
+ *  Generalize signals to carry types.
 *
- * Revision 1.66  2002/03/09 02:10:22  steve
- *  Add the NetUserFunc netlist node.
+ * Revision 1.84  2005/05/24 01:44:27  steve
+ *  Do sign extension of structuran nets.
 *
- * Revision 1.65  2002/01/28 00:52:41  steve
- *  Add support for bit select of parameters.
- *  This leads to a NetESelect node and the
- *  vvp code generator to support that.
+ * Revision 1.83  2005/02/08 00:12:36  steve
+ *  Add the NetRepeat node, and code generator support.
 *
- * Revision 1.64  2002/01/19 19:02:08  steve
- *  Pass back target errors processing conditionals.
+ * Revision 1.82  2005/02/03 04:56:20  steve
+ *  laborate reduction gates into LPM_RED_ nodes.
 *
- * Revision 1.63  2001/10/19 21:53:24  steve
- *  Support multiple root modules (Philip Blundell)
+ * Revision 1.81  2005/01/24 05:28:30  steve
+ *  Remove the NetEBitSel and combine all bit/part select
+ *  behavior into the NetESelect node and IVL_EX_SELECT
+ *  ivl_target expression type.
 *
- * Revision 1.62  2001/08/25 23:50:02  steve
- *  Change the NetAssign_ class to refer to the signal
- *  instead of link into the netlist. This is faster
- *  and uses less space. Make the NetAssignNB carry
- *  the delays instead of the NetAssign_ lval objects.
+ * Revision 1.80  2005/01/22 01:06:55  steve
+ *  Change case compare from logic to an LPM node.
 *
- *  Change the vvp code generator to support multiple
- *  l-values, i.e. concatenations of part selects.
+ * Revision 1.79  2004/12/29 23:55:43  steve
+ *  Unify elaboration of l-values for all proceedural assignments,
+ *  including assing, cassign and force.
 *
- * Revision 1.61  2001/07/27 04:51:44  steve
- *  Handle part select expressions as variants of
- *  NetESignal/IVL_EX_SIGNAL objects, instead of
- *  creating new and useless temporary signals.
+ *  Generate NetConcat devices for gate outputs that feed into a
+ *  vector results. Use this to hande gate arrays. Also let gate
+ *  arrays handle vectors of gates when the outputs allow for it.
 *
- * Revision 1.60  2001/07/25 03:10:49  steve
- *  Create a config.h.in file to hold all the config
- *  junk, and support gcc 3.0. (Stephan Boettcher)
+ * Revision 1.78  2004/12/11 02:31:26  steve
+ *  Rework of internals to carry vectors through nexus instead
+ *  of single bits. Make the ivl, tgt-vvp and vvp initial changes
+ *  down this path.
 *
- * Revision 1.59  2001/04/22 23:09:46  steve
- *  More UDP consolidation from Stephan Boettcher.
+ * Revision 1.77  2004/10/04 01:10:53  steve
+ *  Clean up spurious trailing white space.
 *
- * Revision 1.58  2001/04/06 02:28:02  steve
- *  Generate vvp code for functions with ports.
+ * Revision 1.76  2004/05/31 23:34:37  steve
+ *  Rewire/generalize parsing an elaboration of
+ *  function return values to allow for better
+ *  speed and more type support.
 *
- * Revision 1.57  2001/04/02 02:28:12  steve
- *  Generate code for task calls.
+ * Revision 1.75  2003/09/13 01:30:07  steve
+ *  Missing case warnings.
 *
- * Revision 1.56  2001/03/27 03:31:06  steve
- *  Support error code from target_t::end_design method.
+ * Revision 1.74  2003/05/30 02:55:32  steve
+ *  Support parameters in real expressions and
+ *  as real expressions, and fix multiply and
+ *  divide with real results.
 *
- * Revision 1.55  2000/11/04 01:54:01  steve
- *  Modifications in support of gcc 2.96
+ * Revision 1.73  2003/04/22 04:48:29  steve
+ *  Support event names as expressions elements.
 *
- * Revision 1.54  2000/09/26 01:35:42  steve
- *  Remove the obsolete NetEIdent class.
+ * Revision 1.72  2003/03/10 23:40:53  steve
+ *  Keep parameter constants for the ivl_target API.
 *
- * Revision 1.53  2000/09/17 21:26:15  steve
- *  Add support for modulus (Eric Aardoom)
- *
- * Revision 1.52  2000/09/02 20:54:20  steve
- *  Rearrange NetAssign to make NetAssign_ separate.
- *
- * Revision 1.51  2000/08/14 04:39:56  steve
- *  add th t-dll functions for net_const, net_bufz and processes.
- *
- * Revision 1.50  2000/08/09 03:43:45  steve
- *  Move all file manipulation out of target class.
- *
- * Revision 1.49  2000/08/08 01:50:42  steve
- *  target methods need not take a file stream.
- *
- * Revision 1.48  2000/07/30 18:25:43  steve
- *  Rearrange task and function elaboration so that the
- *  NetTaskDef and NetFuncDef functions are created during
- *  signal enaboration, and carry these objects in the
- *  NetScope class instead of the extra, useless map in
- *  the Design class.
- *
- * Revision 1.47  2000/07/29 16:21:08  steve
- *  Report code generation errors through proc_delay.
- *
- * Revision 1.46  2000/07/27 05:13:44  steve
- *  Support elaboration of disable statements.
- *
- * Revision 1.45  2000/05/11 23:37:27  steve
- *  Add support for procedural continuous assignment.
- *
- * Revision 1.44  2000/05/04 03:37:58  steve
- *  Add infrastructure for system functions, move
- *  $time to that structure and add $random.
- *
- * Revision 1.43  2000/05/02 03:13:31  steve
- *  Move memories to the NetScope object.
- *
- * Revision 1.42  2000/05/02 00:58:12  steve
- *  Move signal tables to the NetScope class.
- *
- * Revision 1.41  2000/04/23 03:45:24  steve
- *  Add support for the procedural release statement.
- *
- * Revision 1.40  2000/04/22 04:20:19  steve
- *  Add support for force assignment.
- *
- * Revision 1.39  2000/04/12 04:23:58  steve
- *  Named events really should be expressed with PEIdent
- *  objects in the pform,
- *
- *  Handle named events within the mix of net events
- *  and edges. As a unified lot they get caught together.
- *  wait statements are broken into more complex statements
- *  that include a conditional.
- *
- *  Do not generate NetPEvent or NetNEvent objects in
- *  elaboration. NetEvent, NetEvWait and NetEvProbe
- *  take over those functions in the netlist.
+ * Revision 1.71  2003/01/26 21:15:58  steve
+ *  Rework expression parsing and elaboration to
+ *  accommodate real/realtime values and expressions.
 */

@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: eval.cc,v 1.32 2002/10/19 22:59:49 steve Exp $"
+#ident "$Id: eval.cc,v 1.43 2006/08/08 05:11:37 steve Exp $"
 #endif

 # include "config.h"
@@ -26,14 +26,15 @@

 # include  "PExpr.h"
 # include  "netlist.h"
+# include  "netmisc.h"
 # include  "compiler.h"

-verinum* PExpr::eval_const(const Design*, const NetScope*) const
+verinum* PExpr::eval_const(const Design*, NetScope*) const
 {
      return 0;
 }

-verinum* PEBinary::eval_const(const Design*des, const NetScope*scope) const
+verinum* PEBinary::eval_const(const Design*des, NetScope*scope) const
 {
      verinum*l = left_->eval_const(des, scope);
      if (l == 0) return 0;
@@ -47,9 +48,7 @@ verinum* PEBinary::eval_const(const Design*des, const NetScope*scope) const
      switch (op_) {
 	  case '+': {
 		if (l->is_defined() && r->is_defined()) {
-		      long lv = l->as_long();
-		      long rv = r->as_long();
-		      res = new verinum(lv+rv, l->len());
+		      res = new verinum(*l + *r);
 		} else {
 		      res = new verinum(verinum::Vx, l->len());
 		}
@@ -57,9 +56,7 @@ verinum* PEBinary::eval_const(const Design*des, const NetScope*scope) const
 	  }
 	  case '-': {
 		if (l->is_defined() && r->is_defined()) {
-		      long lv = l->as_long();
-		      long rv = r->as_long();
-		      res = new verinum(lv-rv, l->len());
+		      res = new verinum(*l - *r);
 		} else {
 		      res = new verinum(verinum::Vx, l->len());
 		}
@@ -67,9 +64,7 @@ verinum* PEBinary::eval_const(const Design*des, const NetScope*scope) const
 	  }
 	  case '*': {
 		if (l->is_defined() && r->is_defined()) {
-		      long lv = l->as_long();
-		      long rv = r->as_long();
-		      res = new verinum(lv * rv, l->len());
+		      res = new verinum(*l * *r);
 		} else {
 		      res = new verinum(verinum::Vx, l->len());
 		}
@@ -95,6 +90,26 @@ verinum* PEBinary::eval_const(const Design*des, const NetScope*scope) const
 		}
 		break;
 	  }
+	  case '>': {
+		if (l->is_defined() && r->is_defined()) {
+		      long lv = l->as_long();
+		      long rv = r->as_long();
+		      res = new verinum(lv > rv, l->len());
+		} else {
+		      res = new verinum(verinum::Vx, l->len());
+		}
+		break;
+	  }
+	  case '<': {
+		if (l->is_defined() && r->is_defined()) {
+		      long lv = l->as_long();
+		      long rv = r->as_long();
+		      res = new verinum(lv < rv, l->len());
+		} else {
+		      res = new verinum(verinum::Vx, l->len());
+		}
+		break;
+	  }
 	  case 'l': { // left shift (<<)
 		assert(r->is_defined());
 		unsigned long rv = r->as_ulong();
@@ -128,16 +143,51 @@ verinum* PEBinary::eval_const(const Design*des, const NetScope*scope) const
      delete r;
      return res;
 }
+verinum* PEConcat::eval_const(const Design*des, NetScope*scope) const
+{
+      verinum*accum = parms_[0]->eval_const(des, scope);
+      if (accum == 0)
+	    return 0;
+
+      for (unsigned idx = 1 ;  idx < parms_.count() ;  idx += 1) {
+
+	    verinum*tmp = parms_[idx]->eval_const(des, scope);
+	    if (tmp == 0) {
+		  delete accum;
+		  return 0;
+	    }
+	    assert(tmp);
+
+	    *accum = concat(*accum, *tmp);
+	    delete tmp;
+      }
+
+      return accum;
+}


 /*
 * Evaluate an identifier as a constant expression. This is only
 * possible if the identifier is that of a parameter.
 */
-verinum* PEIdent::eval_const(const Design*des, const NetScope*scope) const
+verinum* PEIdent::eval_const(const Design*des, NetScope*scope) const
 {
      assert(scope);
-      const NetExpr*expr = des->find_parameter(scope, path_);
+      NetNet*net;
+      NetMemory*mem;
+      NetEvent*eve;
+      const NetExpr*expr;
+
+	// Handle the special case that this ident is a genvar
+	// variable name. In that case, the genvar meaning preempts
+	// everything and we just return that value immediately.
+      if (scope->genvar_tmp
+	  && strcmp(path_.peek_tail_name(),scope->genvar_tmp) == 0) {
+	    return new verinum(scope->genvar_tmp_val);
+      }
+
+      NetScope*found_in = symbol_search(des, scope, path_,
+					net, mem, expr, eve);

      if (expr == 0)
 	    return 0;
@@ -159,23 +209,23 @@ verinum* PEIdent::eval_const(const Design*des, const NetScope*scope) const
      return new verinum(eval->value());
 }

-verinum* PEFNumber::eval_const(const Design*, const NetScope*) const
+verinum* PEFNumber::eval_const(const Design*, NetScope*) const
 {
      long val = value_->as_long();
      return new verinum(val);
 }

-verinum* PENumber::eval_const(const Design*, const NetScope*) const
+verinum* PENumber::eval_const(const Design*, NetScope*) const
 {
      return new verinum(value());
 }

-verinum* PEString::eval_const(const Design*, const NetScope*) const
+verinum* PEString::eval_const(const Design*, NetScope*) const
 {
      return new verinum(string(text_));
 }

-verinum* PETernary::eval_const(const Design*des, const NetScope*scope) const
+verinum* PETernary::eval_const(const Design*des, NetScope*scope) const
 {
      verinum*test = expr_->eval_const(des, scope);
      if (test == 0)
@@ -195,7 +245,7 @@ verinum* PETernary::eval_const(const Design*des, const NetScope*scope) const
      }
 }

-verinum* PEUnary::eval_const(const Design*des, const NetScope*scope) const
+verinum* PEUnary::eval_const(const Design*des, NetScope*scope) const
 {
      verinum*val = expr_->eval_const(des, scope);
      if (val == 0)
@@ -209,7 +259,7 @@ verinum* PEUnary::eval_const(const Design*des, const NetScope*scope) const
 		  /* We need to expand the value a bit if we are
 		     taking the 2's complement so that we are
 		     guaranteed to not overflow. */
-		verinum tmp (0UL, val->len()+1);
+		verinum tmp ((uint64_t)0, val->len()+1);
 		for (unsigned idx = 0 ;  idx < val->len() ;  idx += 1)
 		      tmp.set(idx, val->get(idx));

@@ -226,6 +276,40 @@ verinum* PEUnary::eval_const(const Design*des, const NetScope*scope) const

 /*
 * $Log: eval.cc,v $
+ * Revision 1.43  2006/08/08 05:11:37  steve
+ *  Handle 64bit delay constants.
+ *
+ * Revision 1.42  2006/05/19 04:07:24  steve
+ *  eval_const is not strict.
+ *
+ * Revision 1.41  2006/05/17 16:49:30  steve
+ *  Error message if concat expression cannot evaluate.
+ *
+ * Revision 1.40  2006/04/10 00:37:42  steve
+ *  Add support for generate loops w/ wires and gates.
+ *
+ * Revision 1.39  2005/12/07 04:04:23  steve
+ *  Allow constant concat expressions.
+ *
+ * Revision 1.38  2005/11/27 17:01:57  steve
+ *  Fix for stubborn compiler.
+ *
+ * Revision 1.37  2005/11/27 05:56:20  steve
+ *  Handle bit select of parameter with ranges.
+ *
+ * Revision 1.36  2003/06/21 01:21:43  steve
+ *  Harmless fixup of warnings.
+ *
+ * Revision 1.35  2003/04/14 03:40:21  steve
+ *  Make some effort to preserve bits while
+ *  operating on constant values.
+ *
+ * Revision 1.34  2003/03/26 06:16:18  steve
+ *  Evaluate > and < in constant expressions.
+ *
+ * Revision 1.33  2003/03/10 23:40:53  steve
+ *  Keep parameter constants for the ivl_target API.
+ *
 * Revision 1.32  2002/10/19 22:59:49  steve
 *  Redo the parameter vector support to allow
 *  parameter names in range expressions.
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2002-2004 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: eval_attrib.cc,v 1.5 2002/08/12 01:34:59 steve Exp $"
+#ident "$Id: eval_attrib.cc,v 1.8 2005/11/27 17:01:57 steve Exp $"
 #endif

 # include  "config.h"
@@ -29,14 +29,14 @@

 /*
 * The evaluate_attributes function evaluates the attribute
- * expressions from the map, and resturns a table in a form suitable
+ * expressions from the map, and returns a table in a form suitable
 * for passing to netlist devices.
 */

-attrib_list_t* evaluate_attributes(const map<string,PExpr*>&att,
+attrib_list_t* evaluate_attributes(const map<perm_string,PExpr*>&att,
 				   unsigned&natt,
 				   const Design*des,
-				   const NetScope*scope)
+				   NetScope*scope)
 {
      natt = att.size();
      if (natt == 0)
@@ -46,13 +46,13 @@ attrib_list_t* evaluate_attributes(const map<string,PExpr*>&att,

      unsigned idx = 0;

-      typedef map<string,PExpr*>::const_iterator iter_t;
+      typedef map<perm_string,PExpr*>::const_iterator iter_t;
      for (iter_t cur = att.begin() ;  cur != att.end() ;  cur ++, idx++) {
 	    table[idx].key = (*cur).first;
 	    PExpr*exp = (*cur).second;

 	      /* If the attribute value is given in the source, then
-		 evalulate it as a constant. If the value is not
+		 evaluate it as a constant. If the value is not
 		 given, then assume the value is 1. */
 	    verinum*tmp;
 	    if (exp)
@@ -74,6 +74,15 @@ attrib_list_t* evaluate_attributes(const map<string,PExpr*>&att,

 /*
 * $Log: eval_attrib.cc,v $
+ * Revision 1.8  2005/11/27 17:01:57  steve
+ *  Fix for stubborn compiler.
+ *
+ * Revision 1.7  2004/02/20 18:53:35  steve
+ *  Addtrbute keys are perm_strings.
+ *
+ * Revision 1.6  2003/01/27 05:09:17  steve
+ *  Spelling fixes.
+ *
 * Revision 1.5  2002/08/12 01:34:59  steve
 *  conditional ident string using autoconfig.
 *
@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
- *
- *    This source code is free software; you can redistribute it
- *    and/or modify it in source code form under the terms of the GNU
- *    General Public License as published by the Free Software
- *    Foundation; either version 2 of the License, or (at your option)
- *    any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-#ifdef HAVE_CVS_IDENT
-#ident "$Id: eval_rconst.cc,v 1.5 2002/08/12 01:34:59 steve Exp $"
-#endif
-
-# include "config.h"
-
-# include  "PExpr.h"
-
-verireal* PExpr::eval_rconst(const Design*, const NetScope*) const
-{
-      return 0;
-}
-
-verireal* PEFNumber::eval_rconst(const Design*, const NetScope*) const
-{
-      verireal*res = new verireal;
-      *res = *value_;
-      return res;
-}
-
-verireal* PENumber::eval_rconst(const Design*, const NetScope*) const
-{
-      verireal*res = new verireal(value_->as_long());
-      return res;
-}
-
-verireal* PEBinary::eval_rconst(const Design*des, const NetScope*scope) const
-{
-      verireal*lef = left_->eval_rconst(des, scope);
-      verireal*rig = right_->eval_rconst(des, scope);
-      verireal*res = 0;
-
-      switch (op_) {
-	  case '*':
-	    if (lef == 0)
-		  break;
-	    if (rig == 0)
-		  break;
-	    res = new verireal;
-	    *res = (*lef) * (*rig);
-	    break;
-
-	  default:
-	    break;
-      }
-
-      delete lef;
-      delete rig;
-      return res;
-}
-
-
-verireal* PEIdent::eval_rconst(const Design*des, const NetScope*scope) const
-{
-      verinum* val = eval_const(des, scope);
-      if (val == 0)
-	    return 0;
-
-      verireal*res = new verireal(val->as_long());
-      delete val;
-      return res;
-}
-
-/*
- * $Log: eval_rconst.cc,v $
- * Revision 1.5  2002/08/12 01:34:59  steve
- *  conditional ident string using autoconfig.
- *
- * Revision 1.4  2001/11/07 04:01:59  steve
- *  eval_const uses scope instead of a string path.
- *
- * Revision 1.3  2001/11/06 06:11:55  steve
- *  Support more real arithmetic in delay constants.
- *
- * Revision 1.2  2001/07/25 03:10:49  steve
- *  Create a config.h.in file to hold all the config
- *  junk, and support gcc 3.0. (Stephan Boettcher)
- *
- * Revision 1.1  2001/01/14 23:04:56  steve
- *  Generalize the evaluation of floating point delays, and
- *  get it working with delay assignment statements.
- *
- *  Allow parameters to be referenced by hierarchical name.
- *
- */
-
@@ -218,11 +218,11 @@ output 	[1:48] k;
 wire 	[1:56] YY;

        assign YY[1:28]=c;         assign YY[29:56]=d;
-        
+
        assign k[1]=YY[14];   assign k[2]=YY[17];   assign k[3]=YY[11];   assign k[4]=YY[24];   assign k[5]=YY[1];    assign k[6]=YY[5];
        assign k[7]=YY[3];    assign k[8]=YY[28];   assign k[9]=YY[15];   assign k[10]=YY[6];   assign k[11]=YY[21];  assign k[12]=YY[10];
-        assign k[13]=YY[23];  assign k[14]=YY[19];  assign k[15]=YY[12];  assign k[16]=YY[4];   assign k[17]=YY[26];  assign k[18]=YY[8]; 
-        assign k[19]=YY[16];  assign k[20]=YY[7];   assign k[21]=YY[27];  assign k[22]=YY[20];  assign k[23]=YY[13];  assign k[24]=YY[2]; 
+        assign k[13]=YY[23];  assign k[14]=YY[19];  assign k[15]=YY[12];  assign k[16]=YY[4];   assign k[17]=YY[26];  assign k[18]=YY[8];
+        assign k[19]=YY[16];  assign k[20]=YY[7];   assign k[21]=YY[27];  assign k[22]=YY[20];  assign k[23]=YY[13];  assign k[24]=YY[2];
        assign k[25]=YY[41];  assign k[26]=YY[52];  assign k[27]=YY[31];  assign k[28]=YY[37];  assign k[29]=YY[47];  assign k[30]=YY[55];
        assign k[31]=YY[30];  assign k[32]=YY[40];  assign k[33]=YY[51];  assign k[34]=YY[45];  assign k[35]=YY[33];  assign k[36]=YY[48];
        assign k[37]=YY[44];  assign k[38]=YY[49];  assign k[39]=YY[39];  assign k[40]=YY[56];  assign k[41]=YY[34];  assign k[42]=YY[53];
@@ -252,13 +252,13 @@ input 	[1:64] key;
 output 	[1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x;
 wire 	[1:28] c0x,c1x,c2x,c3x,c4x,c5x,c6x,c7x,c8x,c9x,c10x,c11x,c12x,c13x,c14x,c15x,c16x;
 wire 	[1:28] d0x,d1x,d2x,d3x,d4x,d5x,d6x,d7x,d8x,d9x,d10x,d11x,d12x,d13x,d14x,d15x,d16x;
-  
+
 pc1 pc1(key, c0x, d0x);

 rol1 rc1(c1x, c0x); rol1 rd1(d1x, d0x);
 rol1 rc2(c2x, c1x); rol1 rd2(d2x, d1x);
 rol2 rc3(c3x, c2x); rol2 rd3(d3x, d2x);
-rol2 rc4(c4x, c3x); rol2 rd4(d4x, d3x);  
+rol2 rc4(c4x, c3x); rol2 rd4(d4x, d3x);
 rol2 rc5(c5x, c4x); rol2 rd5(d5x, d4x);
 rol2 rc6(c6x, c5x); rol2 rd6(d6x, d5x);
 rol2 rc7(c7x, c6x); rol2 rd7(d7x, d6x);
@@ -272,7 +272,7 @@ rol2 rce(c14x, c13x); rol2 rde(d14x, d13x);
 rol2 rcf(c15x, c14x); rol2 rdf(d15x, d14x);
 rol1 rcg(c16x, c15x); rol1 rdg(d16x, d15x);

-        
+
 pc2 pc2x1(c1x,d1x,k1x);
 pc2 pc2x2(c2x,d2x,k2x);
 pc2 pc2x3(c3x,d3x,k3x);
@@ -913,7 +913,7 @@ assign l0x[17]=pt[62];        assign l0x[18]=pt[54];        assign l0x[19]=pt[46
 assign l0x[21]=pt[30];        assign l0x[22]=pt[22];        assign l0x[23]=pt[14];        assign l0x[24]=pt[6];
 assign l0x[25]=pt[64];        assign l0x[26]=pt[56];        assign l0x[27]=pt[48];        assign l0x[28]=pt[40];
 assign l0x[29]=pt[32];        assign l0x[30]=pt[24];        assign l0x[31]=pt[16];        assign l0x[32]=pt[8];
-        
+
 assign r0x[1]=pt[57];         assign r0x[2]=pt[49];         assign r0x[3]=pt[41];         assign r0x[4]=pt[33];
 assign r0x[5]=pt[25];         assign r0x[6]=pt[17];         assign r0x[7]=pt[9];          assign r0x[8]=pt[1];
 assign r0x[9]=pt[59];         assign r0x[10]=pt[51];        assign r0x[11]=pt[43];        assign r0x[12]=pt[35];
@@ -935,7 +935,7 @@ assign e[9]=ri[6];    assign e[10]=ri[7];   assign e[11]=ri[8];   assign e[12]=r
 assign e[17]=ri[12];  assign e[18]=ri[13];  assign e[19]=ri[12];  assign e[20]=ri[13];  assign e[21]=ri[14];  assign e[22]=ri[15];  assign e[23]=ri[16];  assign e[24]=ri[17];
 assign e[25]=ri[16];  assign e[26]=ri[17];  assign e[27]=ri[18];  assign e[28]=ri[19];  assign e[29]=ri[20];  assign e[30]=ri[21];  assign e[31]=ri[20];  assign e[32]=ri[21];
 assign e[33]=ri[22];  assign e[34]=ri[23];  assign e[35]=ri[24];  assign e[36]=ri[25];  assign e[37]=ri[24];  assign e[38]=ri[25];  assign e[39]=ri[26];  assign e[40]=ri[27];
-assign e[41]=ri[28];  assign e[42]=ri[29];  assign e[43]=ri[28];  assign e[44]=ri[29];  assign e[45]=ri[30];  assign e[46]=ri[31];  assign e[47]=ri[32];  assign e[48]=ri[1]; 
+assign e[41]=ri[28];  assign e[42]=ri[29];  assign e[43]=ri[28];  assign e[44]=ri[29];  assign e[45]=ri[30];  assign e[46]=ri[31];  assign e[47]=ri[32];  assign e[48]=ri[1];

 endmodule

@@ -26,21 +26,21 @@
  *  Compile this program with the command:
  *
  *      iverilog -ohello hello.vl
-  *  
+  *
  *  After churning for a little while, the program will create the output
  *  file "hello" which is compiled, linked and ready to run. Run this
  *  program like so:
-  *  
-  *      ./hello
-  *  
+  *
+  *      vvp hello
+  *
  *  and the program will print the message to its output. Easy! For
  *  more on how to make the iverilog command work, see the iverilog
  *  manual page.
  */

 module main();
- 
-initial 
+
+initial
  begin
    $display("Hello, World");
    $finish ;
@@ -26,21 +26,21 @@
  *  Compile this program with the command:
  *
  *      iverilog -ohello_vpi hello_vpi.vl
-  *  
+  *
  *  After churning for a little while, the program will create the output
  *  file "hello" which is compiled, linked and ready to run. Run this
  *  program like so:
-  *  
+  *
  *      vvp -M. -mhello_vpi hello_vpi
-  *  
+  *
  *  and the program will print the message to its output. Easy! For
  *  more on how to make the iverilog command work, see the iverilog
  *  manual page.
  */

 module main();
- 
-initial 
+
+initial
  begin
     $my_hello;
     $finish ;
@@ -20,36 +20,36 @@
 /*
  *  This example program simulates a 16x1 ram, and is used as an
  *  example for using VCD output and waveform viewers.
-  *  
+  *
  *  Like any other Verilog simulation, compile this program with the
  *  command:
-  *  
+  *
  *      iverilog show_vcd.vl
-  *  
+  *
  *  This will generate the show_vcd command in the current directory.
  *  When you run the command, you will see the output from all the
  *  calls to $display, but also there will be a dump file ``show_vcd.vcd''.
  *  The name of this file is set by the statement:
  *
  *      $dumpfile("show_vcd.vcd");
-  *  
+  *
  *  in the main module. The output file uses the standard VCD file format
  *  so can be viewed using off-the-shelf waveform viewers. The remaining
  *  steps describe how to use GTKWave to view the file. If you are using
  *  a different viewer, see the documentation for that tool.
-  *  
+  *
  *  To view the output generated by running show_vcd, start the GTKWave
  *  viewer with the command:
-  *  
+  *
  *      gtkwave show_vcd.vcd
-  *  
+  *
  *  The GTKWave program will display its main window, and show in a small
  *  status box (upper left corner) that it succeeded in loading the dump
  *  file. However, there are no waveforms displayed yet. Select signals to
  *  add to the waveform display using the menu selection:
  *
  *      "Search --> Signal Search Tree"
-  *  
+  *
  *  This will bring up a dialog box that shows in directory tree format
  *  the signals of the program. Select the signals you wish to view, and
  *  click one of the buttons on the bottom of the dialog box to display
@@ -60,7 +60,7 @@
  *  $dumpvars system tasks. The $dumpfile task tells the simulation where
  *  to write the VCD output. This task must be called once before the
  *  $dumpvars task is called.
-  *  
+  *
  *  The $dumpvars task tells the simulation what variables to write to
  *  the VCD output. The first parameter is how far to descend while
  *  scanning a scope, and the remaining paramters are signals or scope
@@ -77,7 +77,7 @@ module ram16x1 (q, d, a, we, wclk);
   input wclk;

   reg mem[15:0];
-   
+
   assign q = mem[a];
   always @(posedge wclk) if (we) mem[a] = d;

@@ -88,7 +88,7 @@ module main;
   reg d;
   reg [3:0] a;
   reg we, wclk;
-    
+
   ram16x1 r1 (q, d, a, we, wclk);

   initial begin
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ *
+ *   $Id: sqrt-virtex.v,v 1.4 2003/11/25 18:35:31 steve Exp $"
+ */
+
+/*
+ * This module is a synthesizeable square-root function. It is also a
+ * detailed example of how to target Xilinx Virtex parts using
+ * Icarus Verilog. In fact, for no particular reason other then to
+ * be excessively specific, I will step through the process of
+ * generating a design for a Spartan-II XC2S15-VQ100, and also how to
+ * generate a generic library part for larger Virtex designs.
+ *
+ * In addition to Icarus Verilog, you will need implementation
+ * software from Xilinx. As of this writing, this example was tested
+ * with Foundation 4.2i, but it should work the same with ISE and
+ * Webpack software.
+ *
+ * This example source contains all the Verilog needed to do
+ * everything described below. We use conditional compilation to
+ * select the bits of Verilog that are needed to perform each specific
+ * task.
+ *
+ * SIMULATE THE DESIGN
+ *
+ * This source file includes a simulation test bench. To compile the
+ * program to include this test bench, use the command line:
+ *
+ *    iverilog -DSIMULATE=1 -oa.out sqrt-virtex.v
+ *
+ * This generates the file "a.out" that can then be executed with the
+ * command:
+ *
+ *    vvp a.out
+ *
+ * This causes the simulation to run a long set of example sqrt
+ * calculations. Each result is checked by the test bench to assure
+ * that the result is valid. When it is done, the program prints
+ * "PASSED" and finishes the simulation.
+ *
+ * When you take a close look at the "main" module below, you will see
+ * that it uses Verilog constructs that are not synthesizeable. This
+ * is fine, as we will never try to synthesize it.
+ *
+ * LIBRARY PARTS
+ *
+ * One can use the sqrt32 module to generate an EDIF file suitable for
+ * use as a library part. This part can be imported to the Xilinx
+ * schematic editor, then placed like any other pre-existing
+ * macro. One can also pass the generated EDIF as a precompiled macro
+ * that other designers may use as they see fit.
+ *
+ * To make an EDIF file from the sqrt32 module, execute the command:
+ *
+ *    iverilog -osqrt32.edf -tfpga -parch=virtex sqrt-virtex.v
+ *
+ * The -parch=virtex tells the code generator to generate code for the
+ * virtex architecture family (we don't yet care what specific part)
+ * and the -osqrt32.edf places the output into the file
+ * sqrt32.edf.
+ *
+ * Without any preprocessor directives, the only module is the sqrt32
+ * module, so sqrt32 is compiled as the root. The ports of the module
+ * are automatically made into ports of the sqrt32.edf netlist, and
+ * the contents of the sqrt32 module are connected approprately.
+ *
+ * COMPLETE CHIP DESIGNS
+ *
+ * To make a complete chip design, there are other bits that need to
+ * be accounted for. Signals must be assigned to pins, and some
+ * special devices may need to be created. We also want to write into
+ * the EDIF file complete part information so that the implementation
+ * tools know how to route the complete design. The command to compile
+ * for our target part is:
+ *
+ *    iverilog -ochip.edf -tfpga \
+ *           -parch=virtex -ppart=XC2S15-VQ100 \
+ *           -DMAKE_CHIP=1 sqrt-virtex.v
+ *
+ * This command uses the "chip" module as the root. This module in
+ * turn has ports that are destined to be the pins of the completed
+ * part. The -ppart= option gives complete part information, that is
+ * in turn written into the EDIF file. This saves us the drudgery of
+ * repeating that part number for later commands.
+ *
+ * The next steps involve Xilinx software, and to talk to Xilinx
+ * software, the netlist must be in the form of an "ngd" file, a
+ * binary netlist format. The command:
+ *
+ *    ngdbuild chip.edf chip.ngd
+ *
+ * does the trick. The input to ngdbuild is the chip.edf file created
+ * by Icarus Verilog, and the output is the chip.ngd file that the
+ * implementation tools may read. From this point, it is best to refer
+ * to Xilinx documentation for the software you are using, but the
+ * quick summary is:
+ *
+ *    map -o map.ncd chip.ngd
+ *    par -w map.ncd chip.ncd
+ *
+ * The result of this sequence of commands is the chip.ncd file that
+ * is ready to be viewed by FPGA Edit, or converted to a bit stream,
+ * or whatever.
+ *
+ * POST MAP SIMULATION
+ *
+ * Warm fuzzies are good, and retesting your design after the part
+ * is mapped by the Xilinx backend tools is a cheap source of fuzzies.
+ * The command to make a Verilog file out of the mapped design is:
+ *
+ *    ngd2ver chip.ngd chip_root.v
+ *
+ * This command creates from the chip.ngd the file "chip_root.v" that
+ * contains Verilog code that simulates the mapped design. This output
+ * Verilog has the single root module "chip_root", which came from the
+ * name of the root module when we were making hte EDIF file in the
+ * first place. The module has ports named just line the ports of the
+ * chip_root module below.
+ *
+ * The generated Verilog uses the library in the directory
+ * $(XILINX)/verilog/src/simprims. This directory comes with the ISE
+ * WebPACK installation that you are using. Icarus Verilog is able to
+ * simulate using that library.
+ *
+ * To compile a post-map simulation of the chip_root.v, use the
+ * command:
+ *
+ *    iverilog -DSIMULATE -DPOST_MAP -ob.out \
+ *             -y $(XILINX)/verilog/src/simprims \
+ *             sqrt-virtex.v chip_root.v \
+ *             $(XILINX)/verilog/src/glbl.v
+ *
+ * This command line generates b.out from the source files
+ * sqrt-virtex.v and chip_root.v (the latter from ngd2ver)
+ * and the "-y <path>" flag specifies the library directory that will
+ * be needed. The glbl.v source file is also included to provide the
+ * GSR and related signals.
+ *
+ * The POST_MAP compiler directive causes the GSR manipulations
+ * included in the test bench to be compiled in, to simulate the chip
+ * startup. Other then that, the test bench runs the post-map design
+ * the same way the pre-synthesis design works.
+ *
+ * Run this design with the command:
+ *
+ *    vvp b.out
+ *
+ * And there you go.
+ */
+
+`ifndef POST_MAP
+ /*
+  * This module approximates the square root of an unsigned 32bit
+  * number. The algorithm works by doing a bit-wise binary search.
+  * Starting from the most significant bit, the accumulated value
+  * tries to put a 1 in the bit position. If that makes the square
+  * too big for the input, the bit is left zero, otherwise it is set
+  * in the result. This continues for each bit, decreasing in
+  * significance, until all the bits are calculated or all the
+  * remaining bits are zero.
+  *
+  * Since the result is an integer, this function really calculates
+  * value of the expression:
+  *
+  *      x = floor(sqrt(y))
+  *
+  * where sqrt(y) is the exact square root of y and floor(N) is the
+  * largest integer <= N.
+  *
+  * For 32bit numbers, this will never run more then 16 iterations,
+  * which amounts to 16 clocks.
+  */
+
+module sqrt32(clk, rdy, reset, x, .y(acc));
+   input  clk;
+   output rdy;
+   input  reset;
+
+   input [31:0] x;
+   output [15:0] acc;
+
+
+   // acc holds the accumulated result, and acc2 is the accumulated
+   // square of the accumulated result.
+   reg [15:0] acc;
+   reg [31:0] acc2;
+
+   // Keep track of which bit I'm working on.
+   reg [4:0]  bitl;
+   wire [15:0] bit = 1 << bitl;
+   wire [31:0] bit2 = 1 << (bitl << 1);
+
+   // The output is ready when the bitl counter underflows.
+   wire rdy = bitl[4];
+
+   // guess holds the potential next values for acc, and guess2 holds
+   // the square of that guess. The guess2 calculation is a little bit
+   // subtle. The idea is that:
+   //
+   //      guess2 = (acc + bit) * (acc + bit)
+   //             = (acc * acc) + 2*acc*bit + bit*bit
+   //             = acc2 + 2*acc*bit + bit2
+   //             = acc2 + 2 * (acc<<bitl) + bit
+   //
+   // This works out using shifts because bit and bit2 are known to
+   // have only a single bit in them.
+   wire [15:0] guess  = acc | bit;
+   wire [31:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
+
+   (* ivl_synthesis_on *)
+   always @(posedge clk or posedge reset)
+      if (reset) begin
+	 acc = 0;
+	 acc2 = 0;
+	 bitl = 15;
+      end else begin
+	 if (guess2 <= x) begin
+	    acc  <= guess;
+	    acc2 <= guess2;
+	 end
+	 bitl <= bitl - 5'd1;
+      end
+
+endmodule // sqrt32
+
+`endif //  `ifndef POST_MAP
+
+`ifdef SIMULATE
+ /*
+  * This module is a test bench for the sqrt32 module. It runs some
+  * test input values through the sqrt32 module, and checks that the
+  * output is valid. If an invalid output is generated, print and
+  * error message and stop immediately. If all the tested values pass,
+  * then print PASSED after the test is complete.
+  */
+module main;
+
+   reg [31:0] x;
+   reg 	      clk, reset;
+
+   wire [15:0] y;
+   wire        rdy;
+
+`ifdef POST_MAP
+   chip_root dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));
+`else
+   sqrt32 dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));
+`endif
+
+   (* ivl_synthesis_off *)
+   always #5 clk = !clk;
+
+   task reset_dut;
+      begin
+	 reset = 1;
+	 @(posedge clk) ;
+	 #1 reset = 0;
+	 @(negedge clk) ;
+      end
+   endtask // reset_dut
+
+   task crank_dut;
+      begin
+	 while (rdy == 0) begin
+	    @(posedge clk) /* wait */;
+	 end
+      end
+   endtask // crank_dut
+
+`ifdef POST_MAP
+   reg        GSR;
+   assign      glbl.GSR = GSR;
+`endif
+
+   integer idx;
+
+   (* ivl_synthesis_off *)
+   initial begin
+      reset = 0;
+      clk = 0;
+
+      /* If doing a post-map simulation, when we need to wiggle
+         The GSR bit to simulate chip power-up. */
+`ifdef POST_MAP
+      GSR = 1;
+      #100 GSR = 0;
+`endif
+      #100 x = 1;
+      reset_dut;
+      crank_dut;
+      $display("x=%d, y=%d", x, y);
+
+      x = 3;
+      reset_dut;
+      crank_dut;
+      $display("x=%d, y=%d", x, y);
+
+      x = 4;
+      reset_dut;
+      crank_dut;
+      $display("x=%d, y=%d", x, y);
+
+      for (idx = 0 ;  idx < 200 ;  idx = idx + 1) begin
+	 x = $random;
+	 reset_dut;
+	 crank_dut;
+	 $display("x=%d, y=%d", x, y);
+
+	 if (x < (y * y)) begin
+	    $display("ERROR: y is too big");
+	    $finish;
+	 end
+
+	 if (x > ((y + 1)*(y + 1))) begin
+	    $display("ERROR: y is too small");
+	    $finish;
+	 end
+      end
+
+      $display("PASSED");
+      $finish;
+   end
+
+endmodule // main
+`endif
+
+`ifdef MAKE_CHIP
+ /*
+  * This module represents the chip packaging that we intend to
+  * generate. We bind pins here, and route the clock to the global
+  * clock buffer.
+  */
+module chip_root(clk, rdy, reset, x, y);
+   input  clk;
+   output rdy;
+   input  reset;
+
+   input [31:0] x;
+   output [15:0] y;
+
+   wire 	 clk_int;
+
+   (* cellref="BUFG:O,I" *)
+   buf gbuf (clk_int, clk);
+
+   sqrt32 dut(.clk(clk_int), .reset(reset), .rdy(rdy), .x(x), .y(y));
+
+   /* Assign the clk to GCLK0, which is on pin P39. */
+   $attribute(clk, "PAD", "P39");
+
+   // We don't care where the remaining pins go, so set the pin number
+   // to 0. This tells the implementation tools that we want a PAD,
+   // but we don't care which. Also note the use of a comma (,)
+   // separated list to assign pins to the bits of a vector.
+   $attribute(rdy, "PAD", "0");
+   $attribute(reset, "PAD", "0");
+   $attribute(x, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
+   $attribute(y, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
+
+endmodule // chip_root
+
+`endif
@@ -16,7 +16,7 @@
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 *
- *   $Id: sqrt.vl,v 1.3 2000/11/04 01:53:24 steve Exp $"
+ *   $Id: sqrt.vl,v 1.4 2004/10/04 01:10:56 steve Exp $"
 */

 /*
@@ -97,8 +97,8 @@ module sqrt32(clk, rdy, reset, x, .y(acc));
 	 bitl = 15;
      end
   endtask
-   
-   initial clear;   
+
+   initial clear;

   always @(reset or posedge clk)
      if (reset)
@@ -121,14 +121,14 @@ module main;
   wire rdy;

   sqrt32 root(.clk(clk), .rdy(rdy), .reset(reset), .x(value), .y(result));
-   
+
   always #5 clk = ~clk;

   always @(posedge rdy) begin
      $display("sqrt(%d) --> %d", value, result);
      $finish;
   end
-   
+

   initial begin
      clk = 0;
@@ -72,8 +72,8 @@ module main;
   // These attribute commands assign pins to the listed wires.
   // This can be done to wires and registers, as internally both
   // are treated as named signals. It doesn't work (yet) on vectors,
-   // though, so break out the vectors with scaler assignments.
-   
+   // though, so break out the vectors with scalar assignments.
+
   assign a[0] = a0;
   assign a[1] = a1;
   assign a[2] = a2;
@@ -28,7 +28,7 @@ module ram16x1 (q, d, a, we, wclk);
   input wclk;

   reg mem[15:0];
-   
+
   assign q = mem[a];
   always @(posedge wclk) if (we) mem[a] = d;

@@ -39,7 +39,7 @@ module main;
   reg d;
   reg [3:0] a;
   reg we, wclk;
-    
+
   ram16x1 r1 (q, d, a, we, wclk);

   initial begin
@@ -0,0 +1,84 @@
+
+Icarus Verilog Extensions
+
+Icarus Verilog supports certain extensions to the baseline IEEE1364
+standard. Some of these are picked from extended variants of the
+language, such as SystemVerilog, and some are expressions of internal
+behavior of Icarus Verilog, made available as a tool debugging aid.
+
+* Builtin System Functions
+
+** Extended Verilog Data Types
+
+This feature is turned off if the generation flag "-g" is set to other
+then the default "2x".  For example, "iverilog -g2x" enables extended
+data types, and "iverilog -g2" disables them.
+
+Icarus Verilog adds support for extended data types. This extended
+type syntax is based on a proposal by Cadence Design Systems,
+originally as an update to the IEEE1364. That original proposal has
+apparently been absorbed by the IEEE1800 SystemVerilog
+standard. Icarus Verilog currently only takes the new primitive types
+from the proposal.
+
+Extended data types separates the concept of net/variable from the
+data type. Both nets and variables can declared with any data
+type. The primitive types available are:
+
+    logic  - The familiar 0, 1, x and z, optionally with strength.
+    bool   - Limited to only 0 and 1
+    real   - 64bit real values
+
+Nets with logic type may have multiple drivers with strength, and the
+value is resolved the usual way. Only logic values may be driven to
+logic nets, so bool values driven onto logic nets are implicitly
+converted to logic.
+
+Nets with any other type may not have multiple drivers. The compiler
+should detect the multiple drivers and report an error.
+
+- Declarations
+
+The declaration of a net is extended to include the type of the wire,
+with the syntax:
+
+    wire <type> <wire-assignment-list>... ;
+
+The <type>, if omitted, is taken to be logic. The "wire" can be any of
+the net keywords. Wires can be logic, bool, real, or vectors of logic
+or bool. Some valid examples:
+
+    wire real foo = 1.0;
+    tri logic bus[31:0];
+    wire bool addr[23:0];
+    ... and so on.
+
+The declarations of variables is similar. The "reg" keyword is used to
+specify that this is a variable. Variables can have the same data
+types as nets.
+
+- Ports
+
+Module and task ports in standard verilog are restricted to logic
+types. This extension removes that restriction, allowing any type to
+pass through the port consistent with the continuous assignment
+connectivity that is implied by the type.
+
+- Expressions
+
+Expressions in the face of real values is covered by the baseline
+Verilog standard.
+
+The bool type supports the same operators as the logic type, with the
+obvious differences imposed by the limited domain.
+
+Comparison operators (not case compare) return logic if either of
+their operands is logic. If both are bool or real (including mix of
+bool and real) then the result is bool. This is because comparison of
+bools and reals always return exactly true or false.
+
+Case comparison returns bool. This differs from baseline Verilog,
+which strictly speaking returns a logic, but only 0 or 1 values.
+
+All the arithmetic operators return bool if both of their operands are
+bool or real. Otherwise, they return logic.
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2002 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2005 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -17,7 +17,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: functor.cc,v 1.31 2002/08/16 05:18:27 steve Exp $"
+#ident "$Id: functor.cc,v 1.35 2005/07/07 16:22:49 steve Exp $"
 #endif

 # include "config.h"
@@ -59,6 +59,10 @@ void functor_t::lpm_divide(class Design*, class NetDivide*)
 {
 }

+void functor_t::lpm_literal(class Design*, class NetLiteral*)
+{
+}
+
 void functor_t::lpm_modulo(class Design*, class NetModulo*)
 {
 }
@@ -79,6 +83,14 @@ void functor_t::lpm_mux(class Design*, class NetMux*)
 {
 }

+void functor_t::sign_extend(class Design*, class NetSignExtend*)
+{
+}
+
+void functor_t::lpm_ureduce(class Design*, class NetUReduce*)
+{
+}
+

 void NetScope::run_functor(Design*des, functor_t*fun)
 {
@@ -114,7 +126,7 @@ void NetScope::run_functor(Design*des, functor_t*fun)
 void Design::functor(functor_t*fun)
 {
 	// Scan the scopes
-      for (list<NetScope*>::const_iterator scope = root_scopes_.begin(); 
+      for (list<NetScope*>::const_iterator scope = root_scopes_.begin();
 	   scope != root_scopes_.end(); scope++)
 	    (*scope)->run_functor(this, fun);

@@ -186,6 +198,11 @@ void NetFF::functor_node(Design*des, functor_t*fun)
      fun->lpm_ff(des, this);
 }

+void NetLiteral::functor_node(Design*des, functor_t*fun)
+{
+      fun->lpm_literal(des, this);
+}
+
 void NetLogic::functor_node(Design*des, functor_t*fun)
 {
      fun->lpm_logic(des, this);
@@ -206,6 +223,16 @@ void NetMux::functor_node(Design*des, functor_t*fun)
      fun->lpm_mux(des, this);
 }

+void NetSignExtend::functor_node(Design*des, functor_t*fun)
+{
+      fun->sign_extend(des, this);
+}
+
+void NetUReduce::functor_node(Design*des, functor_t*fun)
+{
+      fun->lpm_ureduce(des, this);
+}
+
 proc_match_t::~proc_match_t()
 {
 }
@@ -267,6 +294,18 @@ int proc_match_t::event_wait(NetEvWait*)

 /*
 * $Log: functor.cc,v $
+ * Revision 1.35  2005/07/07 16:22:49  steve
+ *  Generalize signals to carry types.
+ *
+ * Revision 1.34  2005/05/24 01:44:27  steve
+ *  Do sign extension of structuran nets.
+ *
+ * Revision 1.33  2005/02/03 04:56:20  steve
+ *  laborate reduction gates into LPM_RED_ nodes.
+ *
+ * Revision 1.32  2004/10/04 01:10:53  steve
+ *  Clean up spurious trailing white space.
+ *
 * Revision 1.31  2002/08/16 05:18:27  steve
 *  Fix intermix of node functors and node delete.
 *
@@ -1,7 +1,7 @@
 #ifndef __functor_H
 #define __functor_H
 /*
- * Copyright (c) 1999-2000 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2005 Stephen Williams (steve@icarus.com)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
@@ -19,7 +19,7 @@
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: functor.h,v 1.20 2002/08/12 01:34:59 steve Exp $"
+#ident "$Id: functor.h,v 1.23 2005/07/07 16:22:49 steve Exp $"
 #endif

 /*
@@ -63,6 +63,9 @@ struct functor_t {
 	/* This method is called for each structural constant. */
      virtual void lpm_divide(class Design*des, class NetDivide*);

+	/* Constant literals. */
+      virtual void lpm_literal(class Design*des, class NetLiteral*);
+
 	/* This method is called for each structural constant. */
      virtual void lpm_modulo(class Design*des, class NetModulo*);

@@ -77,6 +80,11 @@ struct functor_t {

 	/* This method is called for each MUX. */
      virtual void lpm_mux(class Design*des, class NetMux*);
+
+	/* This method is called for each unary reduction gate. */
+      virtual void lpm_ureduce(class Design*des, class NetUReduce*);
+
+      virtual void sign_extend(class Design*des, class NetSignExtend*);
 };

 struct proc_match_t {
@@ -92,6 +100,15 @@ struct proc_match_t {

 /*
 * $Log: functor.h,v $
+ * Revision 1.23  2005/07/07 16:22:49  steve
+ *  Generalize signals to carry types.
+ *
+ * Revision 1.22  2005/05/24 01:44:27  steve
+ *  Do sign extension of structuran nets.
+ *
+ * Revision 1.21  2005/02/03 04:56:20  steve
+ *  laborate reduction gates into LPM_RED_ nodes.
+ *
 * Revision 1.20  2002/08/12 01:34:59  steve
 *  conditional ident string using autoconfig.
 *
@@ -203,6 +203,34 @@ interpreted as a loop head, and this is what Icarus Verilog does, as
 well as all the other major Verilog tools, but the standard does not
 say this.

+* UNSIZED NUMERIC CONSTANTS ARE NOT LIMITED TO 32 BITS
+
+The Verilog standard allows Verilog implementations to limit the size
+of unsized constants to a bit width of at least 32. That means that a
+constant 17179869183 (36'h3_ffff_ffff) may overflow some compilers. In
+fact, it is common to limit these values to 32bits. However, a
+compiler may just as easily choose another width limit, for example
+64bits. That value is equally good.
+
+However, it is not *required* that an implementation truncate at 32
+bits, and in fact Icarus Verilog does not truncate at all. It will
+make the unsized constant as big as it needs to be to hold the value
+accurately. This is especially useful in situations like this;
+
+	    reg [width-1:0] foo = 17179869183;
+
+The programmer wants the constant to take on the width of the reg,
+which in this example is parameterized. Since constant sizes cannot be
+parameterized, the programmer ideally gives an unsized constant, which
+the compiler then expands/contracts to match the l-value.
+
+Also, by choosing to not ever truncate, Icarus Verilog can handle code
+written for a 64bit compiler as easily as for a 32bit compiler. In
+particular, any constants that the user does not expect to be
+arbitrarily truncated by his compiler will also not be truncated by
+Icarus Verilog, no matter what that other compiler chooses as a
+truncation point.
+

 * UNSIZED EXPRESSIONS AS PARAMETERS TO CONCATENATION {}

@@ -404,8 +432,87 @@ parameter range (i.e. parameter [5:0] foo = 9;) so Icarus Verilog will
 (or should) use the explicitly declared vector dimensions to interpret
 bit and part selects.

-$Id: ieee1364-notes.txt,v 1.13 2002/08/20 04:11:53 steve Exp $
+
+* EDGES OF VECTORS
+
+Consider this example:
+
+   reg [ 5:0] clock;
+   always @(posedge clock) [do stuff]
+
+The IEEE1364 standard clearly states that the @(posedge clock) looks
+only at the bit clock[0] (the least significant bit) to search for
+edges. It has been pointed out by some that Verilog XL instead
+implements it as "@(posedge |clock)": it looks for a rise in the
+reduction or of the vector. Cadence Design Systems technical support
+has been rumored to claim that the IEEE1364 specification is wrong,
+but NC-Verilog behaves according to the specification, and thus
+different from XL.
+
+Icarus Verilog, therefore, takes the position that the specification
+is clear and correct, and it behaves as does NC-Verilog in this
+matter.
+
+
+* REAL VARIABLES IN $dumpoff DEAD-ZONES
+
+The IEEE1364 standard clearly states that in VCD files, the $dumpoff
+section checkpoints all the dumped variables as X values. For reg and
+wire bits/vectors, this obviously means 'bx values. Icarus Verilog
+does this, for example:
+
+    $dumpoff
+    x!
+    x"
+    $end
+
+Real variables can also be included in VCD dumps, but it is not at
+all obvious what is supposed to be dumped into the $dumpoff-$end
+section of the VCD file. Verilog-XL dumps "r0 !" to set the real
+variables to the dead-zone value of 0.0, whereas other tools, such as
+ModelTech, ignore real variables in this section.
+
+For example (from XL):
+
+    $dumpoff
+    r0 !
+    r0 "
+    $end
+
+Icarus Verilog dumps NaN values for real variables in the
+$dumpoff-$end section of the VCD file. The NaN value is the IEEE754
+equivalent of an unknown value, and so better reflects the unknown
+(during the dead zone) status of the variable, like this:
+
+    $dumpoff
+    rNaN !
+    rNaN "
+    $end
+
+It turns out that NaN is conventionally accepted by scanf functions,
+and viewers that support real variables support NaN values. So while
+the IEEE1364 doesn't require this behavior, and given the variety that
+already seems to exist amongst VCD viewers in the wild, this behavior
+seems to be acceptable according to the standard, is a better mirror
+of 4-value behavior in the dead zone, and appears more user friendly
+when viewed by reasonable viewers.
+
+
+$Id: ieee1364-notes.txt,v 1.17 2003/07/15 03:49:22 steve Exp $
 $Log: ieee1364-notes.txt,v $
+Revision 1.17  2003/07/15 03:49:22  steve
+ Spelling fixes.
+
+Revision 1.16  2003/04/14 03:40:21  steve
+ Make some effort to preserve bits while
+ operating on constant values.
+
+Revision 1.15  2003/02/16 23:39:08  steve
+ NaN in dead zones of VCD dumps.
+
+Revision 1.14  2003/02/06 17:51:36  steve
+ Edge of vectors notes.
+
 Revision 1.13  2002/08/20 04:11:53  steve
 Support parameters with defined ranges.

@@ -103,7 +103,7 @@ fi
 if [ x"$dir_arg" != x ]; then
 	dst=$src
 	src=""
-	
+
 	if [ -d $dst ]; then
 		instcmd=:
 	else
@@ -112,7 +112,7 @@ if [ x"$dir_arg" != x ]; then
 else

 # Waiting for this to be detected by the "$instcmd $src $dsttmp" command
-# might cause directories to be created, which would be especially bad 
+# might cause directories to be created, which would be especially bad
 # if $src (and thus $dsttmp) contains '*'.

 	if [ -f $src -o -d $src ]
@@ -122,7 +122,7 @@ else
 		echo "install:  $src does not exist"
 		exit 1
 	fi
-	
+
 	if [ x"$dst" = x ]
 	then
 		echo "install:	no destination specified"
@@ -150,7 +150,7 @@ dstdir=`echo $dst | sed -e 's,[^/]*$,,;s,/$,,;s,^$,.,'`

 # Skip lots of stat calls in the usual case.
 if [ ! -d "$dstdir" ]; then
-defaultIFS='	
+defaultIFS='
 '
 IFS="${IFS-${defaultIFS}}"

@@ -189,17 +189,17 @@ else

 # If we're going to rename the final executable, determine the name now.

-	if [ x"$transformarg" = x ] 
+	if [ x"$transformarg" = x ]
 	then
 		dstfile=`basename $dst`
 	else
-		dstfile=`basename $dst $transformbasename | 
+		dstfile=`basename $dst $transformbasename |
 			sed $transformarg`$transformbasename
 	fi

 # don't allow the sed command to completely eliminate the filename

-	if [ x"$dstfile" = x ] 
+	if [ x"$dstfile" = x ]
 	then
 		dstfile=`basename $dst`
 	else
@@ -230,7 +230,7 @@ else
 # Now rename the file to the real destination.

 	$doit $rmcmd -f $dstdir/$dstfile &&
-	$doit $mvcmd $dsttmp $dstdir/$dstfile 
+	$doit $mvcmd $dsttmp $dstdir/$dstfile

 fi &&

@@ -1,4 +1,4 @@
-.TH iverilog-vpi 1 "$Date: 2002/07/05 17:17:20 $" Version "$Date: 2002/07/05 17:17:20 $"
+.TH iverilog-vpi 1 "$Date: 2004/10/04 01:10:53 $" Version "$Date: 2004/10/04 01:10:53 $"
 .SH NAME
 iverilog-vpi - Compile front end for VPI modules

@@ -32,17 +32,91 @@ VPI modules to further reference external libraries.
 Normally, the output VPI module will be named after the first source
 file passed to the command. This flag sets the name (without the .vpi
 suffix) of the output vpi module.
+
+.TP 8
+.B --install-dir
+This flag causes the program to print the install directory for VPI
+modules, then exit. It is a convenience for makefiles or automated
+plug-in installers.
+
+.SH "PC-ONLY OPTIONS"
+
+The PC port of \fIiverilog-vpi\fP includes two special flags needed to
+support the more intractable development environment. These flags help
+the program locate parts that it needs.
+
+.TP 8
+.B -mingw=\fIpath\fP
+Tell the program the root of the Mingw compiler tool suite. The
+\fBvvp\fP runtime is compiled with this compiler, and this is the
+compiler that \fIiverilog-vpi\fP expects to use to compile your source
+code. This is normally not needed, and if you do use it, it is only
+needed once. The compiler will save the \fIpath\fP in the registry for
+use later.
+
+.TP 8
+.B -ivl=\fIpath\fP
+Set for the use during compilation the root if the Icarus Verilog
+install. This is the place where you installed Icarus Verilog when you
+ran the installer. This flag is also only needed once, and the path is
+stored in the registry for future use.
+
+.SH "UNIX-ONLY OPTIONS"
+
+The UNIX version of \fIiverilog-vpi\fP includes additional flags to
+let Makefile gurus peek at the configuration of the \fIiverilog\fP
+installation.  This way, Makefiles can be written that handle complex VPI
+builds natively, and without hard-coding values that depend on the
+system and installation.  If used at all, these options must be
+used one at a time, and without any other options or directives.
+
+.TP 8
+.B --cflags
+Print the compiler flags (CFLAGS or CXXFLAGS) needed to compile source
+code destined for a VPI module.
+
+.TP 8
+.B --ldflags
+Print the linker flags (LDFLAGS) needed to link a VPI module.
+
+.TP 8
+.B --ldlibs
+Print the libraries (LDLIBS) needed to link a VPI module.
+
+.TP 8
+.B -m32
+On 64bit systems that support it (and support vvp32) this flag
+requests a 32bit vpi binary instead of the default 64bit binary.
+
+.P
+Example GNU makefile that takes advantage of these flags:
+.IP "" 4
+CFLAGS = -Wall -O $(CFLAGS_$@)
+.br
+VPI_CFLAGS := $(shell iverilog-vpi --cflags)
+.br
+CFLAGS_messagev.o = $(VPI_CFLAGS)
+.br
+CFLAGS_fifo.o = $(VPI_CFLAGS)
+.br
+messagev.o fifo.o: transport.h
+.br
+messagev.vpi: messagev.o fifo.o
+.br
+	iverilog-vpi $^
+
 .SH "AUTHOR"
 .nf
 Steve Williams ([email protected])

 .SH SEE ALSO
 iverilog(1), vvp(1),
-.BR "<http://www.icarus.com/eda/verilog/>"
+.BR "<http://www.icarus.com/eda/verilog/>",
+.BR "<http://www.mingw.org>",

 .SH COPYRIGHT
 .nf
 Copyright \(co  2002 Stephen Williams

-This document can be freely redistributed according to the terms of the 
+This document can be freely redistributed according to the terms of the
 GNU General Public License version 2.0
--- a/Show More
+++ b/Show More