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1162 Commits

Author SHA1 Message Date
Matt Guthaus 851aeae8c4 Add pins_enclosed function to pin_group 2018-10-29 10:28:57 -07:00
Hunter Nichols 3bb8aa7e55 Fixed import errors with mux analytical delay model. 2018-10-26 17:37:25 -07:00
Matt Guthaus 0107e1c050 Reduce verbosity of utils 2018-10-26 13:02:31 -07:00
Matt Guthaus 7d74d34c53 Fix pin_layout contains bug 2018-10-26 10:40:43 -07:00
Matt Guthaus 4ce6b040fd Debugging missing enclosures 2018-10-26 09:25:10 -07:00
Hunter Nichols 98a00f985b Changed the analytical delay model to accept multiport options. Little substance to the values generated. 2018-10-26 00:08:13 -07:00
Hunter Nichols 6efe0f56c2 Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array. 2018-10-26 00:08:13 -07:00
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. 2018-10-26 00:08:12 -07:00
Matt Guthaus 9e5d78cfc2 Fix bug in duplicate remove indices 2018-10-25 14:40:39 -07:00
Matt Guthaus 3407163cf1 Combine adjacent power supply pins finished 2018-10-25 14:25:52 -07:00
Matt Guthaus 0544d02ca2 Refactor router to have pin_groups for pins and router_tech file 2018-10-25 13:36:35 -07:00
Matt Guthaus 3f17679000 Merge remote-tracking branch 'origin' into supply_routing 2018-10-25 09:36:03 -07:00
Matt Guthaus 57fb847d50 Fix check for missing simulator type in characterizer 2018-10-25 09:08:56 -07:00
Matt Guthaus 3d8aeaa732 Run delay and setup/hold tests in netlist_only mode 2018-10-25 09:07:00 -07:00
Matt Guthaus 58de655aac Split functional tests 2018-10-25 08:56:23 -07:00
Michael Timothy Grimes 3202e1eb09 Altering comment code in simulation.py to match the needs of delay.py 2018-10-25 00:58:01 -07:00
Michael Timothy Grimes 40450ac0f5 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-25 00:36:46 -07:00
Michael Timothy Grimes ceab1a5daf Adding debug comments to stim file for functional test and cleaning up comment code in simulation.py. Adding multiple tests for different mux configurations to functional unit tests. 2018-10-25 00:11:00 -07:00
Matt Guthaus b1f3bd97e5 Enable all the 1bank tests. Mostly work in SCMOS. 2018-10-24 17:01:00 -07:00
Matt Guthaus 88f43cc754 Add the minimum pin enclosure that has DRC correct pin connections. 2018-10-24 16:41:33 -07:00
Matt Guthaus 94e5050513 Move overlap functions to pin_layout 2018-10-24 16:13:07 -07:00
Matt Guthaus dc73e8cb60 Odd bug that instances were not properly rotated. 2018-10-24 16:12:27 -07:00
Matt Guthaus 7e2bef624e Continue routing rails in same layer after a blockage 2018-10-24 12:32:27 -07:00
Hunter Nichols a711a5823d Merged dev and fix conflicts in geometry.py 2018-10-24 10:52:22 -07:00
Matt Guthaus cccde193d0 Add ngspice equivalents of RUNLVL 2018-10-24 10:31:27 -07:00
Matt Guthaus 5f17525501 Added run-level option for write_control and enabled fast mode in functional tests 2018-10-24 09:32:44 -07:00
Matt Guthaus 33c716eda8 Rename psram bank test like sram bank testss 2018-10-24 09:08:54 -07:00
Matt Guthaus e90f9be6f5 Move replica bitcells to new bitcells subdir 2018-10-24 09:06:29 -07:00
Hunter Nichols 5c8a00ea1d Fixed pruned golden lib file from error in last commit. 2018-10-24 00:55:55 -07:00
Hunter Nichols da1b003d10 Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes. 2018-10-24 00:17:08 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Hunter Nichols 53cb4e7f5e Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-22 23:33:01 -07:00
Hunter Nichols 62439bdac6 Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00
Michael Timothy Grimes cda2e93cd7 Adding fix to netlist_only mode in geometry.py. Uncommenting functional tests and running both tests in netlist_only mode. 2018-10-22 09:17:03 -07:00
Michael Timothy Grimes 2053a1ca4d Improved debug comments for functional test 2018-10-22 01:09:38 -07:00
Michael Timothy Grimes 1a0568f244 Updating comments and cleaning up code for pbitcell. 2018-10-21 19:10:04 -07:00
Matt Guthaus ab7a83b7a5 Remove old setup.tcl and edit one in tech dir 2018-10-20 15:20:15 -07:00
Matt Guthaus e48e12e8cd Skip non-working 1bank tests for now. 2018-10-20 14:55:11 -07:00
Matt Guthaus 38a8c46034 Change non-preferred route costs. 2018-10-20 14:47:24 -07:00
Matt Guthaus 7591f25a2e Merge branch 'dev' into supply_routing 2018-10-20 14:29:19 -07:00
Matt Guthaus 5276943ba2 Remove temp log file 2018-10-20 14:26:30 -07:00
Matt Guthaus 4c25bb09df Fixed supply end-row via problem by restricting placement 2018-10-20 14:25:32 -07:00
Matt Guthaus f5e68c5c32 Move power pins in hierarchical decoder to be further. Strap rails instead for redundant vias. 2018-10-20 12:54:12 -07:00
Matt Guthaus f9738253c6 Remove warning of track space and floor the space function. 2018-10-20 11:53:52 -07:00
Matt Guthaus a1f2a5befe Convert supply tracks to sets for simpler algorithms. 2018-10-20 10:33:10 -07:00
Matt Guthaus 0aad61892b Supply router working except for off by one rail via error 2018-10-19 14:21:03 -07:00
Matt Guthaus 233a1425e4 Flatten bitcell array in netgen for now. See issue 52 2018-10-19 09:13:17 -07:00
jcirimel 74b806fa38
Merge pull request #54 from VLSIDA/datasheet_gen 
flask_table check fix
 2018-10-18 15:12:04 -07:00
Jesse Cirimelli-Low 1b4383b945 moved flask_table warning from sram.py to datasheet_gen.py 2018-10-18 09:58:19 -07:00
Jesse Cirimelli-Low b9990609bf provides warning on missing flask packages, does not generate html on missing packages 2018-10-18 07:21:03 -07:00
Michael Timothy Grimes a06a0975db Removed L shaped routing from gnd contact to wordlines in replica bitline. Corrected slight DRC errors. Optimizations to pbitcell. 2018-10-18 07:05:47 -07:00
Jesse Cirimelli-Low ab6afb7ca8 fixed html typos, added logo, added placeholder timing and current, began ports section 2018-10-17 19:27:09 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Matt Guthaus 5d6944953b Fix char_result rename collision 2018-10-17 09:38:26 -07:00
Michael Timothy Grimes d6a9ea48ac Working out bugs in psram functional test for SCMOS. Commenting out for now. 2018-10-17 07:45:24 -07:00
Michael Timothy Grimes a27cdb4fbc Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-17 07:32:03 -07:00
Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell. 2018-10-17 07:28:56 -07:00
Michael Timothy Grimes 69a1560186 Changing the location of the vdd contact in precharge to avoid drc errors when the bitlines are close to the edge of the cell. Correcting replica bitcell function in pbitcell. 2018-10-16 06:57:53 -07:00
Matt Guthaus 5cb3a24b19 Fix supply rail step size to place alternating rails 2018-10-15 13:58:40 -07:00
Matt Guthaus e2cfd382b9 Fix print check regression 2018-10-15 13:23:31 -07:00
Matt Guthaus a165446fa7 First implementation of multiple track spacing wide DRCs in routing grid. 2018-10-15 11:25:51 -07:00
Matt Guthaus d60986e590 Don't skip grid format checks 2018-10-15 11:21:07 -07:00
Matt Guthaus d855d4f1a6 Moving wide metal spacing to routing grid level 2018-10-15 09:59:16 -07:00
Michael Timothy Grimes c8c70401ae Redesign of pbitcell for newer process technolgies. 2018-10-15 06:29:51 -07:00
Matt Guthaus 1c426aad29 Merge remote-tracking branch 'origin/datasheet_gen' into supply_routing 2018-10-12 20:55:57 -07:00
Matt Guthaus ce8c2d983d Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
Jesse Cirimelli-Low afba54a22d added analytical model support, added proper output with sram.py 2018-10-12 13:22:12 -07:00
Matt Guthaus 5e9fe65907 Remove banks from example configs 2018-10-12 10:23:34 -07:00
Matt Guthaus 4932d83afc Add design rules classes for complex design rules 2018-10-12 09:44:36 -07:00
Michael Timothy Grimes d1701b8a2a Removing extra functional test and changing name to a more general form. Spice exe can just be selected from the command line with -s. 2018-10-12 06:29:59 -07:00
Jesse Cirimelli-Low 50cc8023a4 deleted output file left in previous commit 2018-10-11 16:04:43 -07:00
Jesse Cirimelli-Low 35e0ba6fc4 fixed merge error 2018-10-11 16:03:05 -07:00
Jesse Cirimelli-Low cfb5921d98 reorganized code structure 2018-10-11 15:59:06 -07:00
Jesse Cirimelli-Low d142136735 rewrite of redirected print statements to file write 2018-10-11 12:09:50 -07:00
Jesse Cirimelli-Low bc54bc238f removed tabs and fixed bug in which datasheets generated without the characterizer running 2018-10-11 11:18:40 -07:00
Matt Guthaus 297ea81060 Change RBL size to 50% of row size. 2018-10-11 10:39:24 -07:00
Matt Guthaus 1333329dd4 Merge branch 'multiport' into supply_routing 2018-10-11 10:37:10 -07:00
Matt Guthaus f7d1df6ca7 Fix trim spice with new names 2018-10-11 10:36:49 -07:00
Matt Guthaus e759c9350b Skip psram 1 bank 2018-10-11 10:17:50 -07:00
Matt Guthaus a094db9077 Merge branch 'multiport' into supply_routing 2018-10-11 09:56:38 -07:00
Matt Guthaus 823cb04b80 Fix metal4 rules in FreePDK45. Multiport still needs updating. 2018-10-11 09:56:15 -07:00
Matt Guthaus e22e658090 Converted all submodules to use _bit notation instead of [bit] 2018-10-11 09:53:08 -07:00
Matt Guthaus 3f2b7b837d Skip multibank for now too 2018-10-10 16:57:42 -07:00
Matt Guthaus 22b5010734 Skip pmulti which has LVS fail 2018-10-10 16:01:55 -07:00
Matt Guthaus 96d3cacb9c Skip func tests that are failing 2018-10-10 16:00:21 -07:00
Matt Guthaus 9bb1c2bbcf Fix Future Warning for real 2018-10-10 15:58:16 -07:00
Matt Guthaus 13e83e0f1a Separate 1bank tests 2018-10-10 15:58:00 -07:00
Matt Guthaus fa4dd8881c Fix Future warnings comparison to None 2018-10-10 15:47:14 -07:00
Matt Guthaus 6bbf66d55b Rewrote pin enclosure code to better address off grid pins. 
Include only maximal pin enclosure shapes.
Add smallest area connector for off grid pins.
Fix decoder to use add_power_pin code.
Change permissions.
 2018-10-10 15:15:58 -07:00
Hunter Nichols f30e54f33c Cleaned up indexing in variable that records cycle times. 2018-10-10 00:02:03 -07:00
Hunter Nichols 3ac2d29940 Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation 2018-10-09 17:44:28 -07:00
Hunter Nichols a3bec5518c Put worst case test under the hierarchy of a delay test. Added option for pex option to worst case test. 2018-10-09 00:36:14 -07:00
Hunter Nichols fd806077d2 Added class and test for testing the delay of several bitcells. 2018-10-08 15:50:52 -07:00
Matt Guthaus a2b1d025ab Merge multiport 2018-10-08 11:45:50 -07:00
Matt Guthaus 3244e01ca1 Add copy power pin function 2018-10-08 09:56:39 -07:00
Matt Guthaus 280488b3ad Add M3 supply to pinvbuf 2018-10-08 09:24:16 -07:00
Michael Timothy Grimes 6ef1a3c755 Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail. 2018-10-08 06:34:36 -07:00
Jesse Cirimelli-Low 49268b025f fixed /tmp/ typo 2018-10-06 21:17:26 -07:00
Jesse Cirimelli-Low fa979e2d34 initial stages of html documentation generation 2018-10-06 21:15:54 -07:00
Matt Guthaus 06dc910390 Route supply after moving origin 2018-10-06 14:03:00 -07:00
Matt Guthaus 8499983cc2 Add supply router to top-level SRAM. Change get_pins to elegantly fail. 2018-10-06 08:30:38 -07:00
Matt Guthaus 83fd2c0512 Fix openram_temp directory 2018-10-06 08:08:01 -07:00
Matt Guthaus 94ab69ea16 Supply router working, perhaps not efficiently though. 2018-10-05 15:57:34 -07:00
Matt Guthaus eb2304944b Fix .magicrc file name 2018-10-05 08:48:25 -07:00
Matt Guthaus 12cb02a09f Add partial grids as pins. Add previous paths as routing targets. 2018-10-05 08:39:28 -07:00
Matt Guthaus c0ffa9cc7b Clean up magic config file copying. Add warning for missing files. 2018-10-05 08:36:12 -07:00
Matt Guthaus b3fa6b9d52 Make setup.tcl file a technology file 2018-10-05 08:30:25 -07:00
Matt Guthaus 19114fe47f Add commented extraction when running DRC only 2018-10-05 08:18:53 -07:00
Matt Guthaus bb83e5f1be Move clk up in dff arrays for supply pin access 2018-10-05 08:18:38 -07:00
Matt Guthaus 68b30d601e Move bitcells to their own directory in preparation for custom multiport cells. 2018-10-05 08:09:09 -07:00
Hunter Nichols 7b4e001885 Altered web to only be generated for rw ports. 2018-10-04 15:08:12 -07:00
Matt Guthaus c3cd76048b Removed prints. Fixed offset for single track enclosure. 2018-10-04 14:44:25 -07:00
Hunter Nichols 371a57339f Fixed bugs to allow characterization of multiple read ports. Improved some debug messages. 2018-10-04 14:09:09 -07:00
Hunter Nichols 6e0a1b8823 Fixed bugs in power simulations. Made regex raw strings to remove warnings 2018-10-04 14:09:09 -07:00
Hunter Nichols c876bbfe73 Changed characterizer control generation to match recent changes in multiport. 2018-10-04 14:09:09 -07:00
Hunter Nichols 2e322be7f7 Added changes the control logic PWL generation to match changes made in stimuli. 2018-10-04 14:09:09 -07:00
Hunter Nichols 88f2238e03 Multiport variable bug fix and removed unused code. 2018-10-04 14:09:09 -07:00
Hunter Nichols bb79d9a62d Added regex pattern matching to trim_spice to handle multiport. 2018-10-04 14:09:09 -07:00
Hunter Nichols e7f92e67d0 Fixed issues with inst_sram that prevented functional test from running after merge. 2018-10-04 14:09:01 -07:00
Hunter Nichols 6c537c4884 Made stim node names more ngspice friendly for interactive mode. Cleaned up cycle comments. Changed ground names in stim and added related comments. 2018-10-04 14:06:43 -07:00
Hunter Nichols 65edc70cfd Made global names for pins types. Fixed bugs in tests. 2018-10-04 14:06:43 -07:00
Hunter Nichols d2120d6910 Moved pin name creation from stimuli to delay and bug fix in find_feasible_period_one_port 2018-10-04 14:06:34 -07:00
Matt Guthaus 985d04d4b5 Cleanup of router. 
Made offsets in geometry snap to grid.
Changed gds_write to use list for visited flag.
Rewrite self.gds each call in case of any changes.
 2018-10-04 14:04:29 -07:00
Hunter Nichols 4586ed343f Edited lib to support port indexing. Edited tests in reaction to name dict name changes. Cleaned up measurement value generation in delay. 2018-10-04 14:04:08 -07:00
Hunter Nichols ab7d3510b5 Cleaned up result tables to be indexed by port and measurement name. Lib has not been updated, so it crashes there. 2018-10-04 14:04:08 -07:00
Hunter Nichols 346b188372 Improved on some hard coded values which determine the measurements. 2018-10-04 14:04:08 -07:00
Hunter Nichols cfe15d48a4 Added changes to make changing the names of the measurements simple in delay.py. Results in some hardcoded values which is TODO for a fix. 2018-10-04 14:04:08 -07:00
Hunter Nichols aa0d032c78 Cleaned the char_data to fit the previous style. Added print statements to load/slew sims. 2018-10-04 14:04:08 -07:00
Michael Timothy Grimes cf4b216888 Correcting functional inheritance from simulation. 2018-10-04 13:55:59 -07:00
Michael Timothy Grimes e258199fa3 Removing we_b signal from write ports since it is redundant. 2018-10-04 09:31:04 -07:00
Michael Timothy Grimes 34d8a19871 Adding simulation.py for common functions between functional and delay tests. Updating functional test. 2018-10-04 09:29:44 -07:00
Michael Timothy Grimes bea6b0b5dc Renaming functional tests to include spice exe used. Renaming pex test to separate functional tests from pex test. 2018-09-30 22:39:37 -07:00
Michael Timothy Grimes 6d83ebf50f updating debug messages in functional test 2018-09-30 22:10:11 -07:00
Michael Timothy Grimes 8a56dd2ac9 Finished functional test 2018-09-30 21:20:01 -07:00
Michael Timothy Grimes 26c6232564 Updating functional test. Test can now run a spice simulation and read the dout values from the timing files. 2018-09-28 23:38:48 -07:00
Michael Timothy Grimes a71486e22f Adding mutliport constants to design.py to reduce the need for copied code across multiple modules. 2018-09-28 00:11:39 -07:00
Michael Timothy Grimes 66933ed922 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-27 02:02:24 -07:00
Michael Timothy Grimes 19d68f613e Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport. 2018-09-27 02:01:32 -07:00
Michael Timothy Grimes 1ca0154027 Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port. 2018-09-26 19:10:24 -07:00
Michael Timothy Grimes 648e57d195 Altering bank select for port specific use. Altering bank select test to test different port types. Altering bank for control signal changes. 2018-09-26 14:53:55 -07:00
Michael Timothy Grimes f1560375fc Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport 2018-09-25 20:00:25 -07:00
Matt Guthaus a7246f5e7f Rename omits 0 size ports 2018-09-24 13:44:31 -07:00
Matt Guthaus 9b0142d6b9 Comment debug for possible performance issue 2018-09-24 11:44:32 -07:00
Matt Guthaus a3f13d6eab Remove banks from test configs 2018-09-24 11:41:51 -07:00
Matt Guthaus 2df9b79b28 Remove scn3me lib files. Remove bank references. 2018-09-24 11:28:43 -07:00
Matt Guthaus 7432192e5e Small change to test webhook 2018-09-24 09:11:44 -07:00
Matt Guthaus 922e3f4c13 Small change to test webhook 2018-09-21 15:05:46 -07:00
Matt Guthaus ade12c9dc2 Small change to test webhook 2018-09-21 15:03:16 -07:00
Matt Guthaus e1864a7a1e Small change to test webhook 2018-09-21 15:02:16 -07:00
Matt Guthaus 2b3b4bbee6 Small change to test webhook 2018-09-21 15:01:07 -07:00
Michael Timothy Grimes 934959952b Corrections to functional test that adds multiple cs_b signals per port 2018-09-21 09:59:44 -07:00
Matt Guthaus 87502374c5 DRC clean supply grid routing on control logic. 2018-09-20 16:00:13 -07:00
Michael Timothy Grimes 2641841e4c Making correction to replica bitline netlist for multiport 2018-09-20 15:21:22 -07:00
Michael Timothy Grimes 938ded3dd6 Adding functional test to characterizer and unit tests in both single and multiport 2018-09-20 15:04:59 -07:00
Michael Timothy Grimes fc5f163828 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
Matt Guthaus fd9ffe30d6 Add layer width options to route object 
Modify router to use track-width routes.
 2018-09-18 15:12:53 -07:00
Matt Guthaus 8d2804b9cb Supply router working except: 
Off grid pins. Some pins do now span enough of the routing track and must be patched.
  Route track width. Instead of minimum width route, it should be the track width.
 2018-09-18 12:57:39 -07:00
Matt Guthaus bfc8428df7 Convert router tests to scn4m_subm 2018-09-17 13:30:30 -07:00
Matt Guthaus 60cceab50a Merge branch 'dev' into supply_routing 2018-09-17 11:34:31 -07:00
Matt Guthaus a58b1906ad Convert unit tests to scn4m_subm 
Also, fixed isdiff for python3.
 2018-09-17 11:13:46 -07:00
Michael Timothy Grimes 43f5316eed Correcting format of replica_pbitcell. 2018-09-13 18:51:52 -07:00
Michael Timothy Grimes 9acc8a9532 Altering multiport checks across several unit tests. 2018-09-13 18:49:20 -07:00
Michael Timothy Grimes 332976dd73 s_en will be shared amongst the sense amps of different ports, so I'm removing the distinct s_en signals from several modules. 2018-09-13 18:46:43 -07:00
Michael Timothy Grimes 5fd484ee5a Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode. 2018-09-13 16:53:24 -07:00
Matt Guthaus e591176211 Change default to scn4m 2018-09-13 15:26:03 -07:00
Matt Guthaus 93ae7ebd00 Specify DRC,LVS,PEX tool for scn4m 2018-09-13 15:18:30 -07:00
Matt Guthaus 571dca5d5f Hard code flatten commands for the unique id precharge array 2018-09-13 15:15:41 -07:00
Matt Guthaus 4d328c5768 Fix hspice setuphold golden results 2018-09-13 14:41:15 -07:00
Matt Guthaus f4389bdd8f Add extra track spacings in some routes. 2018-09-13 14:12:24 -07:00
Matt Guthaus 63d0523228 Added scn4m_subm. 
Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.
 2018-09-13 12:53:35 -07:00
Matt Guthaus 3539887ee4 Updating ms_flop removal. 
Updated characterizer for dff.
Added new setup/hold results for dff instead of ms_flop.
Removed ms_flop references in sram-base.
Fixed syntax errors in SCN3ME tech file.
 2018-09-13 11:40:24 -07:00
Matt Guthaus 66cbe0966c Removed old ms_flop unit test 2018-09-13 11:15:33 -07:00
Matt Guthaus f8fc7c12b3 Remove ms_flop and replace with dff. Might break setup_hold tests. 2018-09-13 11:02:28 -07:00
Matt Guthaus 849293b95b Converting grid data structures to sets to reduce size. 2018-09-13 09:10:29 -07:00
Michael Timothy Grimes e0b9989d85 Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate. 2018-09-13 01:42:06 -07:00
Michael Timothy Grimes f03cd7c3ba Removing multiport_check option that diabled multiport portion of unit tests. Adding multiport checks to several other modules. 2018-09-12 20:22:12 -07:00
Michael Timothy Grimes 42719b8ec2 Fixing netlist_only errors. Removing netlist_only option from ptx because it must always generate layout for pbitcell. gds_write, drc check, and lvs check in local_check() are now in a 'if not OPTS.netlist_only' conditional. These functions will generate errors in netlist_only mode since there is no gds layout to write or check. 2018-09-12 01:53:41 -07:00
Michael Timothy Grimes 7dfd37f79c Altering control logic for multiport. Netlist changes only. 2018-09-12 00:59:07 -07:00
Michael Timothy Grimes bfc855b8b1 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-11 17:33:17 -07:00
Hunter Nichols ac3cc5c79b Merge branch 'dev' into multiport_characterization 2018-09-11 16:01:51 -07:00
Matt Guthaus a3c2b4384a Improve comments. Simplify function interface for channel route. 2018-09-11 15:53:12 -07:00
Hunter Nichols 676b6764c7 Merge branch 'dev' into multiport_characterization 2018-09-11 15:40:17 -07:00
Matt Guthaus 3587f90e94 Fix copy pasta error in create vertical channel route 2018-09-11 14:47:55 -07:00
Matt Guthaus 5e34233479 Finish new VCG testing. 
Reversed VCG graph edge directions.
Channel tracks get added left to right or top down like
normal left edge algorithm examples.
 2018-09-11 14:24:13 -07:00
Matt Guthaus fcc4a75295 Create VCG using nets as nodes rather than pins. 2018-09-11 13:28:28 -07:00
Matt Guthaus add0e3ad68 Add none option for verify wrapper with warning messages. 2018-09-11 10:17:24 -07:00
Hunter Nichols 91bbc556e8 Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports. 2018-09-10 22:06:50 -07:00
Hunter Nichols da6843af5b Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done. 2018-09-10 19:33:59 -07:00
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition. 2018-09-10 14:27:26 -07:00
Michael Timothy Grimes 38a1f35ff0 Correcting format of file (removing tabs) 2018-09-10 03:44:08 -07:00
Michael Timothy Grimes a7f03858e8 Adding 'multiport_check' option to OPTS. All of the unit tests that have multiport checks in them are now under this conditional. If you want to remove the multiport drc/lvs checks, you can set the option to False, and it will skip those portions. 2018-09-09 23:25:29 -07:00
Michael Timothy Grimes 5af56e5a3a Adding layout check for sram (1 bank) using pbitcell and 1RW port 2018-09-09 22:45:25 -07:00
Michael Timothy Grimes 0cdd3b99bf Generalized wl names using bitcell's list_all_wl_names function to accomodate multiport 2018-09-09 22:42:52 -07:00
Michael Timothy Grimes 586c72e4f7 Altering certain tests to include multiport checks. 2018-09-09 22:08:03 -07:00
Michael Timothy Grimes 27427d4192 Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary. 2018-09-09 22:06:29 -07:00
Michael Timothy Grimes 252ae1effa add trailing 0 to web 2018-09-09 15:16:53 -07:00
Michael Timothy Grimes 68c00d7467 Removing din and dout list names in exchange for a read index. Write ports will always be in order (they will not skip numbers. Read ports however will skip the numbers assigned to wirte ports so the index of the read ports must be tracked. 2018-09-09 14:14:26 -07:00
Michael Timothy Grimes 1429b9ab1a Commiting working version of multi-port that can generate a netlist on the sram level. Changes that will clean up the code are forthcoming. 2018-09-09 14:00:51 -07:00
Michael Timothy Grimes c91735b23b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-08 18:56:58 -07:00
Matt Guthaus 2d86492d91 Working on methodology of blockages, pins, and routing multiple pins. 2018-09-08 18:55:36 -07:00
Matt Guthaus 96c51f3464 Component shape functions. Find connected pins through overlaps. 2018-09-08 10:05:48 -07:00
Hunter Nichols 5cab786e21 Cleaned up analyze and some of its helper functions to be less cluttered. 2018-09-07 17:50:09 -07:00
Matt Guthaus 69261a0dc1 Routing and connecting rails with vias done. 
Refactored grid path class.
Added direction enum.
Does not route multi-track width wires in signal router.
 2018-09-07 14:46:58 -07:00
Hunter Nichols 83f6434476 Gave find_feasible_period a port input. 2018-09-07 00:53:11 -07:00
Hunter Nichols 8aaf1155d1 Fixed test 23_lib_sram_test. Fixed syntax in related golden lib files. 2018-09-06 22:51:34 -07:00
Hunter Nichols 0ff3b29b66 Fixed test 23_sram_prune test. Fixed syntax errors in golden lib files. 2018-09-06 22:06:23 -07:00
Michael Timothy Grimes 1a340c9c85 Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell. 2018-09-06 19:36:50 -07:00
Hunter Nichols bf34911f3f Test 21_ngspice now passing for scmos and freepdk45. 21_hspice has leakage power error (but it may be okay) 2018-09-06 18:40:21 -07:00
Hunter Nichols 1615de05e4 Fixed leakage power issue in test 21_hspice. Still requires more testing. 2018-09-06 18:26:08 -07:00
Michael Timothy Grimes 66a8a76fb0 Commiting changes to pbitcell that separate the routing into individual functions and rename. The bitlines and wordlines are also renamed. 2018-09-06 17:59:21 -07:00
Hunter Nichols a2bc82fe71 Fixed test 21_hspice. Leakage power is off. 2018-09-06 17:34:22 -07:00
Hunter Nichols dd22f9acd5 Fixed issues with analytical sram test. Changed syntax errors in golden lib file. 2018-09-06 17:01:10 -07:00
Matt Guthaus c2c17a33d2 Horizontal and vertical grid wires done. 2018-09-06 14:30:59 -07:00
Matt Guthaus cd987479b8 Updates to supply routing. 
Rename astar_grid to signal_grid to parallel supply routing.
Wave expansion for supply rails.
Pin addition for supply rails.
 2018-09-06 11:54:14 -07:00
Hunter Nichols f824d039c6 Merge branch 'dev' into multiport_characterization 2018-09-06 00:25:11 -07:00
Hunter Nichols 66c4782408 Fixed several syntax error regarding some multiport naming. Currently in debug mode. 2018-09-06 00:25:02 -07:00
Hunter Nichols ad235c02c6 Added debug code which skips characterization and goes straight to writing the lib. Fixed some syntax issues in the lib file. 2018-09-05 23:27:13 -07:00
Matt Guthaus 59956f1446 Update signal routing for new blockage and pins. 2018-09-05 16:01:11 -07:00
Matt Guthaus 7ead566154 Remove cell rename during DRC. Keep flatten. 2018-09-05 16:00:48 -07:00
Matt Guthaus b1c63a6c62 Add inflate blockages and remove pins from blockages. 2018-09-05 11:06:17 -07:00
Matt Guthaus 93b24d8c85 Merge remote-tracking branch 'origin/dev' into supply_routing 2018-09-05 11:05:41 -07:00
Matt Guthaus ba651d53ae Change options in pbitcell test to be global again. 2018-09-05 10:59:41 -07:00
Matt Guthaus 2a27fbc98e Fix temp directory preservation option. 
Make labels in freepdk45 replica bitcell lower case.
 2018-09-05 10:02:12 -07:00
Matt Guthaus 0f87ba742f Add back LEF blockages. Remove "absolute" flags from GDS output 2018-09-05 09:28:43 -07:00
Matt Guthaus 8ffdcdf277 Fixed bit shift amount error. Removed rotate flag for Calibre. 2018-09-04 17:27:50 -07:00
Matt Guthaus 5395f21be9 Remove unique id in contact that was used for debugging 2018-09-04 16:40:52 -07:00
Matt Guthaus 9d40cd4a03 Remove verbose print statement in add_power_pin 2018-09-04 16:39:13 -07:00
Matt Guthaus 378993ca22 Found rotate bug in transformCoordinate. Cleaned up transFlags. 2018-09-04 16:35:40 -07:00
Matt Guthaus 763f1e8dee Finish renaming replica bitcell and bitline pin names. 2018-09-04 14:03:15 -07:00
Matt Guthaus 6963a1092f Make bitcell width/height not static. Update modules to use it for pbitcell. 2018-09-04 11:55:22 -07:00
Matt Guthaus 0adfe66429 Add total_ port variables to sram base class. 2018-09-04 11:15:18 -07:00
Matt Guthaus de6f22aa3c Fix unit test permissions 2018-09-04 10:48:37 -07:00
Matt Guthaus 19c0e1638b Merge remote-tracking branch 'origin/multiport' into multiport 2018-09-04 10:47:55 -07:00
Matt Guthaus a346bddd88 Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
Hunter Nichols 3bde83bdbe Added initial structure changes to lib. Crashes when writing to lib file. 2018-09-04 00:43:44 -07:00
Michael Timothy Grimes af0756382f Merging changes and updating multiport syntax across several tests 2018-09-03 19:36:20 -07:00
Michael Timothy Grimes 774c14ad75 changing 19_psingle_bank_test to test layout for a single bank using pbitcell with 1 RW port (equivalent to using 6T cell) 2018-09-03 17:47:29 -07:00
Michael Timothy Grimes 341a3ee68d Adding multiport pin names to sram_base for netlist only use 2018-09-03 17:44:32 -07:00
Michael Timothy Grimes 1e5924d1b7 Adding multiported bank_sel pins 2018-09-03 17:35:00 -07:00
Michael Timothy Grimes d3441c7ba4 Altering wordline driver to size for any bitcell. Editting multi-port test cases for sense amp array, write driver array, and wordline driver to least number of ports as a better test of spacing betwwen amps/drivers 2018-09-03 17:31:12 -07:00
Hunter Nichols 1af5bb3758 Remove code bloat and simplified port logic in some cases. Crashes while writing to lib. 2018-09-01 00:10:40 -07:00
Michael Timothy Grimes f3cca7eea0 Altering sense amp array and write driver array so spacing between amps/drivers accomodates multiport. Also altering sense amp array and write driver array tests to include multiport cases. 2018-08-31 23:28:06 -07:00
Matt Guthaus 9d8d2b65e4 Fix delay test with new sram_config. Merge dev changes. 2018-08-31 13:01:17 -07:00
Matt Guthaus c3bd54696f Merge branch 'dev' into multiport 2018-08-31 12:56:25 -07:00
Matt Guthaus 563ff77d44 Add sram_config class. Rename port variables for better description. 2018-08-31 12:03:28 -07:00
Michael Timothy Grimes 75d77095d0 merging changes to magic.py 2018-08-31 09:01:15 -07:00
Hunter Nichols 4022f014b2 Merge branch 'dev' into multiport_characterization 2018-08-31 00:43:33 -07:00
Hunter Nichols 60088c2dfb Added changes to lib to allow the default to run. Will crash with multiport options. 2018-08-31 00:42:56 -07:00
Hunter Nichols 6614c3eb51 Altered min_period algorithm to work for multiport. Works for default config but mostly untested for multiport options. 2018-08-30 22:43:56 -07:00