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1447 Commits

Author SHA1 Message Date
Keith Rothman 8964ad3b53 Convert CLB/CLB_INT tilegrid fuzzer to workaround prohibited locations. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-03-09 13:47:03 -07:00
Keith Rothman 9e21e951c8 Fix remap on new 074 code. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-21 13:01:30 -08:00
Keith Rothman 89bc2008d8 Some more fixes around ignored tiles within a grid. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-20 11:33:12 -08:00
Keith Rothman 22e1a8f7c3 Refactor how part specific for part generic fuzzers are marked. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:55:53 -08:00
Keith Rothman 44eb914f8d Fill holes in excluded part of grid. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman fabae5eb64 Fix some bugs in makefile work tracking. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman 1f22d60160 Fix up Makefile dependences. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman bc00250f90 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman e626994d4d Add some samples for cfg_int to remove discrepancies. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman 61d4a43b3f Remove some unused targets from fuzzaddr/common.mk 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman 6a50598cdc Sort tilegrid_tdb.json for better debugging. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman 32833e6f93 Add diagnostic to find 005 instability. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman 850d16fa02 Don't clobber other parts build directories on run target. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman d6e4c28323 Report full untruncated log upon failure. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman 63ab362d2a Fix clean step update for 073. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman 3aeb1f120a Also clean log directories. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman ec6b1aa02d Fix some typo's. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman f4fd84625f Add part to run_fuzzer output. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman 80add259ed Fix some parallelism issues. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman 9f839a7a08 Attempt to parallelize 074 for additional parts. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman 44b79e1e85 Remap some timing models. 
This is an approximation, but it may work better.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:08 -08:00
Alessandro Comodi 073c976128 cleaning fuzzers before running roi_only target commands 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Keith Rothman 2bc72b5cce Increase number of processes allowed to run during final grid reduction. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:33:32 -08:00
Keith Rothman 4691ba3183 Remove temp files after 074 completes. 
- Remove unused imports.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 3f435ea30b 074-dump_all: fix bug when annotating wires speed model 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 43699a09ac 074-dump_all: fix bug in site pin delay addition 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 1257f9f855 074-dump_all: remove speed_index from tile_types 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi b24f5f5ad3 fuzzers: clean and do make fuzzer/run.ok when generating part_only 
This is necessary to have a clean output when building extra-parts

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi a2120b529e 074-dump_all: direct speed model tmp files to specimen directory 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 1004ad6633 074-dump_all: get vivado exec path from env variable 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 46c28ccb91 074-dump_all: continue if site_pin is NoneType 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 986ca05686 074-dump_all: remove unnecessary lines from jobtiles.tcl 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi c16b1233d5 074-dump_all: back annotation added to tile types 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:32:33 -08:00
Alessandro Comodi a3b8e56194 074-dump_all: added creation of json speed model file for backannotation 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:32:33 -08:00
Alessandro Comodi ce35c7c37c 074-dump_all: annotate only speed model index 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:32:33 -08:00
Alessandro Comodi 194cc230f1 fix possible concurrency issue 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:32:33 -08:00
litghost 84b1457b88
Merge pull request #1238 from litghost/remap_some_timing 
Remap some timing
 2020-02-19 16:31:44 -08:00
Keith Rothman 445934140e Fix up some comments. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 15:15:59 -08:00
Keith Rothman f7e3442f74 Remap some timing models. 
This is an approximation, but it may work better.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 09:27:12 -08:00
Keith Rothman 9aec0c8d9c Sort wire pairs using extract_numbers. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 09:11:03 -08:00
Keith Rothman 222eefcece Use extract_numbers for sort keys to preserve previous DB output. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-18 10:45:22 -08:00
litghost 66916fb787
Merge pull request #1245 from antmicro/fix_1234 
Fix for the lost IOB bits
 2020-02-18 09:58:46 -08:00
litghost c0289c5948
Merge pull request #1186 from antmicro/in_term_group 
Grouping of IN_TERM features
 2020-02-18 09:20:31 -08:00
Keith Rothman 89761c1102 Add some sorting to JSON outputs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-18 06:39:20 -08:00
Maciej Kurc 9183126bdd Fixed the 030 fuzzer to automatically detect where the PUDC_B site is. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-02-18 12:01:02 +01:00
litghost 541d88c999
Merge pull request #1229 from litghost/serdes_timing 
I/OSERDES BEL timing
 2020-02-13 07:41:43 -08:00
Maciej Kurc 014462de26 Ported tag grouping to dbfixup.py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-02-13 13:47:32 +01:00
Tim Ansell db14b30fdb
Merge pull request #1230 from litghost/sorting-fix 
Copy of #1226, remove use of xjson from `074`

>  - Rework how the `json` files are sorted (numbers are treated as numerics).
>  - Sort `csv` and `txt` files.
>  - Sort `segbits.*origin_info.db` files.
>  - Sort the grid file.
> 
> How this changes the output can be seen in https://github.com/SymbiFlow/prjxray-db/pull/11/files
 2020-02-12 19:26:08 -08:00
Keith Rothman 7dfd4adaa8 Remove xjson from 074. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-12 14:43:15 -08:00
Keith Rothman 49b5a8cde6 Handle weird bel pins that aren't really clocks. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-12 12:59:14 -08:00
Keith Rothman 2f388235e4 Update doctests. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:55:07 -08:00
Keith Rothman ec69db772d Remove progressbar 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:50:50 -08:00
Keith Rothman 0c1a404ab1 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:49:09 -08:00
Keith Rothman 564863ccad Refactor remaining function in tim2json.py 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:38:34 -08:00
Keith Rothman e17f9e8140 Refactor routines to read pins, props, and site pins. 
Also fix Makefile intermediate.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:38:27 -08:00
Keith Rothman b9f8f962f1 Start of SERDES timing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 16:52:12 -08:00
Maciej Kurc 1196f67f71 Moved the group.py script to the utils dir. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-02-11 12:24:34 +01:00
Maciej Kurc b20bae5341 Added grouping of IN_TERM features so they can be decoded unambigosly. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-02-11 12:24:34 +01:00
Keith Rothman 2678e7a3a7 Handle both jobserver-fds and jobserver-auth flags. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-10 14:50:46 -08:00
Tomasz Michalak de763a309c fuzzers: Add support for KiB, MiB and GiB units 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2020-01-29 12:33:13 +01:00
Maciej Kurc 45338f1af4 Reworked the PS7 port def. extractor so instead of a minitest its now a fuzzer. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-01-28 12:17:16 +01:00
litghost 3f0804a417
Merge pull request #1162 from antmicro/zynq_7020_tilegrid 
Tilegrid generation for Zynq 7020
 2020-01-27 19:24:07 -08:00
litghost e7667a8daf
Merge pull request #1212 from daveshah1/dspimprove 
fuzzers: Improve DSP fuzzer
 2020-01-27 07:18:21 -08:00
Alessandro Comodi 31cfa88344 generate both xc7010 and xc7020 parts 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-27 11:26:55 +01:00
Alessandro Comodi 5a8e10bba6 zynq: sorted and renamed ignored_wires in 074-dump_all fuzzer 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-27 11:26:55 +01:00
Tomasz Michalak ecab15cd39 zynq: 034-cmt-pll-pips: Remove Zynq specific workarounds 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2020-01-27 11:26:55 +01:00
David Shah 22213404a5 fuzzers: Improve DSP fuzzer 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-27 09:27:46 +00:00
Alessandro Comodi 895612c264 zynq: Add ignored wires for Zynq 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-27 10:21:38 +01:00
Alessandro Comodi b211908e26 zynq: fuzzers: Remove Zynq specific workarounds 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-27 10:21:38 +01:00
Alessandro Comodi fb26896dcb zynq: Allow LIOB baseaddr 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-27 10:21:38 +01:00
Tomasz Michalak 13ba74194a zynq: Add BRKH_INT_PSS tile type to fix assertion 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2020-01-27 10:20:22 +01:00
Alessandro Comodi 0b623982e5 divided harness and extra parts creation 
There is an issue with the roi_harness creation, for which the
multi-process make does not correctly works for roi_harness target

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 5ae155fd9c copy tileconn.json in the correct diretory 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 117f3e51b2 revert 074 and 072 to use previous Makefile configuration 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 4a0ca41077 roi_only: copy tilegrid and tileconn from equivalent part 
005-tilegrid fuzzer cannot run for some parts as some of the IOBs are
not available, therefore the fuzzer exits with errors.

Instead, the tilegrid is copied from the specified equivalent part.

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi dfb0717f2c fix makefile part_only dependencies 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 4849f49724 005-tilegrid: added comment on EXCLUDE_ROI env variable 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 5db213293c 072-ordered_wires: better handling of Lock 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 15d914f2c5 074-dump_all: changed ignored_wires location 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 90d88bc7a2 fix roi_only parts 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 88f7830456 addressed review comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 9a88b77620 run make format 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi e464172e03 074-dump_all: exclude tiles and node that are in the excluded roi 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi cb9944d392 005-tilegrid: use variable for dependencies 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 070931ec6e 074-dump_all: fix tilegrid location 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 61cd47dc36 043-clk-rebuf-pips: fixed missing argument 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 127412b5b9 fix wrong location of tilegrid and yaml 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi e84a1d63df 075-pins: create destination directory 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi e44027bcaf Move all part-specific files to dedicated directory 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 3865c726f2 074-dump_all: increase jobs and tiles per job 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 63bb8337f8 072-ordered_wires: increased parallel jobs. 
This changes also the way the ordered wires final files are generated.
In fact, now, with the help of a Lock, all the suprocesses directly
access the final files, updating them. Once the write completes, the
temporary file is deleted.

This saves up disk space.

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi c5a33cb161 005-tilegrid: further increasing to 6 number of specimens for mmcm 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi e8a2777a17 005-tilegrid: reduce number of specimens 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 5c829daa8c 005-tilegrid: fixed some over-specific settings in generate_full 
Also added specimens to make some rquired fuzzers find all necessary
features

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 93d1ae82f7 Enable the generation of extra part-dependents files 
This change affects the extra-db target, by adding also the generation
of other part-dependent files, such as tilegrid, tileconn, and others.

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Keith Rothman cce638930c Add clock_region to tilegrid.json for constructing clock networks. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-12-14 22:28:22 -08:00
litghost cc9e00da8f
Merge pull request #1174 from antmicro/zynq_ps7_clocks 
Zynq PS7 clocks
 2019-12-12 13:05:29 -08:00
litghost 0d0a38cf52
Merge pull request #1175 from antmicro/zynq_ps7_ppips 
Dumping PPIPs for Zynq PS7
 2019-12-12 08:50:12 -08:00
Maciej Kurc 810473ef46 Disabled initialization of LIOB3/LIOI33 segbit files for Zynq7 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-12 17:20:53 +01:00
Maciej Kurc ef8d405bdb Added dumping of PPIPs for Zynq PS7 tiles and interconnects. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-12 09:57:41 +01:00
Maciej Kurc 0507f92345 Ran make format 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-12 09:31:59 +01:00
Maciej Kurc 24ccfb3bb5 Automatic inference of CLK_HROW with PS7 clocks, use of todo list for PS7 clock sources. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-11 22:39:04 +01:00
Maciej Kurc fb65464c42 A little hacky but working version. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-11 19:05:04 +01:00
Maciej Kurc d84c28b38c Modified fuzzer 075 to dump IO bank number for each pin. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-11 17:10:41 +01:00
Maciej Kurc 6086e6d6f5 Modified fuzzer 041 to solve Zynq PS7 FCLK clocks. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-11 16:25:45 +01:00
Maciej Kurc 7bd13efdcb WIP 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-10 15:21:28 +01:00
Maciej Kurc a4a033226f Modified fuzzer 001 to include required features for Zynq parts. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-10 14:38:24 +01:00
Alessandro Comodi 9401d1c730 071-ppips: fix wrong ppip in ioi tiles 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-12-05 16:40:33 +01:00
Tomasz Michalak 24070da931 001-part-yaml: Add iobanks information to part's json 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-12-02 21:39:32 +01:00
Maciej Kurc cc7ba29c6b Added forcing of manual routing through "BB" pips to toggle more bits. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-11-15 12:14:06 +01:00
Maciej Kurc 03b0b9cefc Added separate clock inputs for PLLs. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-11-15 12:13:49 +01:00
Maciej Kurc 6fd00834b2 Fixed bit names formatting. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-11-14 16:09:44 +01:00
Alessandro Comodi 99d31d2e67 071-ppips: skip HCLK_IOI_CK_IGCLK0 ppips addition 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-11-07 15:03:44 +01:00
litghost 4cec0817ab
Merge pull request #1080 from JakeMercer/dsp 
DSP - Add Attribute Fuzzing
 2019-11-04 08:16:53 -08:00
Alessandro Comodi 827081b3b5 hlck-ioi: fix empty list bug in generate.tcl 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-11-04 11:02:52 +01:00
Jake Mercer 6a3db24da1 FUZZER - DSP - Fixes Following Review 
Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer 15cfb5bd46 FUZZER - DSP - Add Ports & ROI Module 
Added code for ports to the DSP48E1 instances.  Moved DSP instances
inside an ROI module and using the verilog top harness as in other
fuzzers.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer e0fb0c0cb1 FUZZER - DSP - Refactor 
Refactor the DSP Python scripts to be easier to manage.  Use JSON
instead of CSV.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer 596bb27e3b FUZZER - DSP - Add All Attributes 
Added the rest of the DSP attributes; there are still some issues with mapping the bits.
AREG/BREG mode 2 will require inputs to be connected.

Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer 8da263c502 FUZZER - DSP - Refactor for Readability & Extensibility 
Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer 624de250e8 FUZZER - DSP - Cleared Bits 
Changed some tags to be prefixed with 'Z'; these bits are cleared and need the prefix to indicate
the inversion so that they are resolved to the DB correctly.

Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer 78d64f7558 FUZZER - DSP - Add AUTORESET_PATDET Attribute Fuzzing 
Added fuzzing for the AUTORESET_PATDET attribute of the DSP48 block.  Values are RESET_MATCH,
NO_RESET, and RESET_NOT_MATCH; so this can be represented by 2 bits.

Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer c575adf8a0 FUZZER - DSP - Add A & B Input Attributes 
Adding `A_INPUT` and `B_INPUT` attribute fuzzing for the DSP48 tiles.

Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
 2019-11-02 11:43:12 +00:00
Alessandro Comodi 13361904ee hclk-ioi: make 047a dependent on 47 to avoid race condition on piplist 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 17:00:33 +01:00
Alessandro Comodi 949cf722d1 hclk-ioi: re-add IDELAYCTRL to exclude-RE 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 12:04:43 +01:00
Alessandro Comodi b057e35e73 hclk-ioi: addressed review comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 11:58:11 +01:00
Alessandro Comodi 0cf48f337a hclk-ioi: re-added whole top.py file to avoid having const1 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 11:58:11 +01:00
Alessandro Comodi 1ad84b2b44 hclk-ioi: reduce probability of using lut output as BUFR clock 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 11:58:11 +01:00
Alessandro Comodi 2fb40d0232 hclk-ioi: moved IDELAYCTRL to new parallel fuzzer 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 11:58:11 +01:00
Alessandro Comodi 127022c2a9 hclk-ioi: added IMUX to BEFORE_DIV pips 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 11:58:11 +01:00
litghost 78cf96be0f
Merge pull request #1122 from JakeMercer/whitespace 
Whitespace
 2019-10-29 15:04:39 -07:00
Maciej Kurc b99bd85fa4 Added handling of routing failure in the TCL script. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-29 18:20:50 +01:00
Maciej Kurc 0377b5fb4c Disabled reading PIPs and PPIPs for "R" version of CMT tiles for Zynq7. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-29 17:43:10 +01:00
Maciej Kurc 573ee1a38d Fixed bug in tag_groups.txt 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-29 11:55:03 +01:00
Maciej Kurc bf380f2bdd PIPs and PPIPs are now not read from the db. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-29 11:50:40 +01:00
Maciej Kurc 8267bcdaeb Updated regex for PIP todo list. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Maciej Kurc 5ab90a604d Inceased N 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Maciej Kurc 355a571400 Removed the INTERNAL_FEEDBACK tag as it is the same as the PLLE2.COMPENSATION.INTENAL 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Maciej Kurc 4a6930694f Reworked fuzzer, added README.md 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Maciej Kurc 73c8652858 Ran make format_py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Maciej Kurc 56258694aa Added rejection of conflicting features. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Maciej Kurc f88a1d54b8 Fixed makefile 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:58:58 +01:00
Maciej Kurc a4250c1487 Comments. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:58:58 +01:00
Maciej Kurc 205bc5c1df Code formatting. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:58:58 +01:00
Maciej Kurc 89abe7ad47 Modified 034 to manually force routing through specific PIPs and exclude PPIPs from segdata. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:57:22 +01:00
Jake Mercer c05b4b0406 MAKE - Format Trailing Whitespace 
Add `make format-trailing-ws`.  This recipe finds all _files_ (not
links) known to Git and uses `sed` to remove trailing whitespace.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-10-26 10:04:52 +01:00
litghost f1f86a02bf
Merge pull request #1118 from antmicro/more_ppips 
Dump PPIPs for additional clock related tiles.
 2019-10-25 08:06:36 -07:00
Alessandro Comodi 8914753211 run make format 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-24 17:45:04 +02:00
Maciej Kurc 7911d78a8f Removed dumping PPIPs for CLK_BUFG_REBUF. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-24 17:42:49 +02:00
Alessandro Comodi 04234ec75c 036-ologic: change OSERDESE prefix to OSERDES 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-24 17:34:31 +02:00
Alessandro Comodi 1d26c91d4a oserdese: fix wrong fasm prefix 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-24 15:56:18 +02:00
Maciej Kurc a88e73f65e Added dumping of PPIPs for additional clock routing related tiles. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-24 10:20:47 +02:00
Keith Rothman 97699e4e93 Add HCLK_[LR]_BOT_UTURN aliases. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-10-23 15:30:27 -07:00
litghost c94cb0224c
Revert "Whitespace" 2019-10-23 14:22:17 -07:00
Jake Mercer bf11f43390 FORMAT - Run `make format` 
Changes after running `make format`.  Future commits which add
whitespace should be caught by CI at the PR stage.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-10-22 19:35:24 +01:00
Keith Rothman c0b8aef3a9 Add pin functions to tilegrid. 
- Add support to emit PUDC_B pullup if unused (for A7 and Z7 fabrics).

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-10-14 16:38:02 -07:00
Keith Rothman 8813f16bb9 Actually use pin in foreach loop. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-10-07 10:45:19 -07:00
Keith Rothman d490b948e8 Add pin functions column to package pins output. 
This is required to know which pin is a PUDC pin, which requires special
handling.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-10-04 15:39:50 -07:00
Maciej Kurc 0922181488 Fixed bits.dbf for 034 to include "0" tags in db. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-26 14:38:29 +02:00
Tomasz Michalak 5238fed5b5 Add background to script's purpose 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-09-10 09:01:03 +02:00
Tomasz Michalak f71956225a fuzzers: 038-cfg: Add always on bit for Zynq 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-09-09 15:06:44 +02:00
litghost f5768c1ae7
Merge pull request #1017 from litghost/fix_int_maketodo 
Avoid failing on empty pip lists (which may occur).
 2019-08-09 20:57:32 -07:00
Keith Rothman 93f74cf7b0 Filter ILOGIC1 version of IMUX22. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-08-09 15:57:52 -07:00
Keith Rothman 8888134c01 Avoid failing on empty pip lists (which may occur). 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-08-08 12:23:30 -07:00
Keith Rothman a575059e69 Skip weird tiles on Kintex7 fuzzing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-08-08 12:14:35 -07:00
Keith Rothman 472583079a Add 039 fuzzer to master makefile. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-08-08 08:42:02 -07:00
litghost 779a70c3a0
Merge pull request #1007 from litghost/fix_ioi_pip_instability 
Refactor 037 to remove some unstable pips.
 2019-08-06 16:33:17 -07:00
litghost 66a60005fe
Merge pull request #1008 from litghost/bufr 
Add HCLK (BUFR) fuzzer and solve additional bits in CLK_HROW.
 2019-08-06 14:57:32 -07:00
Keith Rothman a08cd04aa5 Refactor 037 to remove some unstable pips. 
This does lose the IMUX->OCLKM pip, but I believe that is okay. That pip
was returning an incorrect solution anyways.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-08-06 11:30:56 -07:00
Keith Rothman 6f999ed3d1 Add HCLK (BUFR) fuzzer and solve additional bits in CLK_HROW. 
These fuzzer updates are required for use of BUFR for clock dividing.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-08-06 11:07:17 -07:00
Keith Rothman 21b0cc54f8 Split CCIO ACTIVE into two features. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-08-05 17:34:54 -07:00
Keith Rothman a84da31c0c Move ILOGIC and OLOGIC to IOI3 tiles for consistency. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-08-01 11:06:18 -07:00
litghost e0e4f549c0
Merge pull request #1005 from litghost/ologic_fuzzer 
Document some combo OSERDESE.DATA_WIDTH bits.
 2019-08-01 09:04:49 -07:00
Keith Rothman 9d476f726f Rename overlapping bit features for OSERDES. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-08-01 08:53:31 -07:00
litghost c25898e6dc
Merge pull request #1000 from litghost/iob_hclk_iostandard 
Add stepdown feature to HCLK_IOI.
 2019-08-01 05:16:26 -07:00
Karol Gugala c0bb3f5c0a
Merge pull request #1004 from litghost/ioi3_oclkm 
Solve OCLKM pips in IOI3
 2019-08-01 11:12:15 +02:00
Keith Rothman e81a2fb93d Document some combo DATA_WIDTH bits. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-31 15:59:52 -07:00
Keith Rothman d30a420bc4 Solve OCLKM pips. 
- Also relaxes pip list filtering to capture additional bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-31 13:21:41 -07:00
Keith Rothman 6d17580752 Add some missing ISERDES features. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-31 11:28:52 -07:00
litghost fb2071895d
Merge pull request #986 from litghost/iob_vref 
Add HCLK_IOI3.INTERNAL_VREF feature.
 2019-07-31 07:14:52 -07:00
litghost e231dd819b
Merge pull request #994 from litghost/fixup_clock_invert_bits 
Refactor clock invert tags for ISERDES/OSERDES.
 2019-07-31 07:14:01 -07:00
litghost dd64be807e
Merge pull request #999 from litghost/fix_int_maketodo 
Restore int_maketodo support for non-LR sides.
 2019-07-31 07:11:47 -07:00
litghost 4cba56602a
Merge pull request #993 from litghost/iserdes-width 
Add ISERDESE2.DATA_WIDTH's 2-8.
 2019-07-30 20:23:06 -07:00
Keith Rothman 4efb540d96 Add stepdown feature to HCLK_IOI. 
- Also narrow HCLK_IOI tilegrid size to avoid coupling into [RL]IOI3.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-30 16:03:25 -07:00
Keith Rothman f6e94a33d9 Restore int_maketodo support for non-LR sides. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-30 13:26:37 -07:00
Keith Rothman 48f97be0c7 Refactor clock invert tags for ISERDES/OSERDES. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-30 09:23:24 -07:00
Keith Rothman 39a52f8198 Relate pip filtering to find additional HCLK_IOI3 pip bits. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-30 08:39:29 -07:00
Keith Rothman 716e4ca785 Add ISERDESE2.DATA_WIDTH's 2-8. 
10 and 14 require ISERDESE2 MASTER/SLAVE which are not currently in use.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-30 08:38:47 -07:00
Keith Rothman e9dbc39e9c Add HCLK_IOI3.INTERNAL_VREF feature. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-30 07:40:40 -07:00
litghost 693c621e96
Merge pull request #981 from litghost/add_tsrtype 
Add TSRTYPE features to OLOGIC fuzzer
 2019-07-29 17:55:29 -07:00
litghost 11b5f39a78
Merge pull request #983 from litghost/iob_diff 
Add initial DIFF_ support to IOB fuzzer.
 2019-07-29 17:53:35 -07:00
litghost 9d0065a768
Merge pull request #934 from antmicro/ioi3-pips 
IOI3_INTER pips fuzzer
 2019-07-26 19:25:38 -07:00
Keith Rothman f723091e50 Add IN_TERM fuzzing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 14:21:40 -07:00
Keith Rothman 73b3342adb Add initial DIFF_ support to IOB fuzzer. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 13:59:12 -07:00
litghost 1de2a0a6bc
Merge pull request #979 from antmicro/ioi3_sing_alias 
Add alias for IOI3_SING tiles
 2019-07-26 12:41:47 -07:00
Keith Rothman 6911dd0439 Add TSRTYPE features. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 10:33:03 -07:00
litghost 963aba5b81
Merge pull request #976 from litghost/add_features_to_idelay 
Add additional features for IDELAY.
 2019-07-26 09:56:26 -07:00
litghost e8b98601b9
Merge pull request #977 from litghost/remove_ilogic_remove_clocks 
ISERDES FASM feature improvements
 2019-07-26 09:53:45 -07:00
Keith Rothman 8d4b7348c0 ISERDES FASM feature improvements 
- Add non-decimal prefixes to feature parts
 - Remove clocks in some samples to decouple ioi pips.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 09:53:06 -07:00
litghost 8e941468bd
Merge pull request #970 from litghost/update_iob_fuzzer 
Refactor IOB fuzzer.
 2019-07-26 09:49:20 -07:00
Tomasz Michalak 5de6e16b29 005-tilegrid: Add alias for IOI3_SING tiles 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-26 13:34:44 +02:00
Keith Rothman a724be9a08 Add additional features for IDELAY. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-25 15:40:04 -07:00
Alessandro Comodi 5409992f03 make format 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-07-25 18:57:03 +02:00
Alessandro Comodi fec82e9818 036-ologic: add IN_USE oserdes 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-07-25 18:48:34 +02:00
Keith Rothman 82df57c816 Add write_io_banks.tcl for listing IO banks. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-25 09:40:04 -07:00
litghost 4fd53f65a8
Merge pull request #971 from litghost/ologic_update 
Add some additional OLOGIC bits.
 2019-07-25 09:18:27 -07:00
Alessandro Comodi 702ae02655 pips: fix maketodo 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-07-25 15:06:12 +02:00
Alessandro Comodi 089b2c447e 037-ioi-pips: fixed and cleaned fuzzer 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-07-24 18:23:19 +02:00
Keith Rothman e3b5fe97f4 Make CLKB for ISERDES work correctly. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-24 18:23:19 +02:00
Keith Rothman b1780e76a0 Refactor 037 to capture non-inverted pips. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-24 18:23:19 +02:00
Alessandro Comodi e26a6432a4 iob-pips: initial attempt to document ioi pips 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-07-24 18:23:19 +02:00
Keith Rothman d364c689fd Add some additional OLOGIC bits. 
- Add OLOGIC D1 mux (for OLOGIC passthrough).
 - Add OQUSED, TQUSED features.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-24 08:43:30 -07:00
litghost b6b8dc19cd
Merge pull request #968 from antmicro/idelay-tbytesrc-tbyteterm 
Pushing bits for IOI3 to the DB also for TBYTESRC and TBYTETERM tiles
 2019-07-24 08:31:00 -07:00
Keith Rothman e217fbb7c7 Add print on success when checking single design. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 17:27:44 -07:00
litghost e3b58d631e
Merge pull request #969 from antmicro/calculate-carry-timings 
Calculate carry timings
 2019-07-23 17:23:46 -07:00
Keith Rothman fa2f61f914 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 17:21:26 -07:00
Keith Rothman 879e3c9eb9 Merge branch 'master' into update_iob_fuzzer 2019-07-23 13:45:58 -07:00
Keith Rothman a7ba547acb Filter out non-IOB bits. 
Also add output from LiteX to verify IOB FASM features.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 13:38:03 -07:00
Keith Rothman aa331131f2 Refactor IOB fuzzer. 
- Add SSTL135
 - Refactor process_rdb to handle varying SLEW by IOSTANDARD.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 08:36:38 -07:00
litghost 293074ee42
Merge pull request #967 from antmicro/036-iob-ologic-data-rate-oq 
036-iob-ologic: Solve bits for DATA_RATE_OQ
 2019-07-23 07:16:25 -07:00
Karol Gugala 2b93883d78 fuzzers: 007: run make format 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-23 14:50:10 +02:00
Karol Gugala 10e022140e fuzzers: 007: reorganize Makefiles 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-23 14:49:45 +02:00
Maciej Kurc ba486f8c71 Added pushing xIOI3 bits to the database also for [LR]IOI3_TBYTESRC and [LR]IOI3_TBYTETERM 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-23 13:35:21 +02:00
Tomasz Michalak 22c7925aa0 036-iob-ologic: Solve bits for DATA_RATE_OQ 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-23 11:50:19 +02:00
Lukasz Dalek 7665003311 fuzzers: 007-timing: Add CARRY4 [ABCD]CY muxes 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2019-07-23 10:21:02 +02:00
Keith Rothman ff4425b91a Update 035a using knowledge from #954 tool. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-22 10:34:02 -07:00
litghost ae526981a2
Merge pull request #946 from antmicro/idelay-fuzzer 
Fuzzer for IDELAY
 2019-07-22 10:04:36 -07:00
Maciej Kurc b659a168da Changed function for getting XY location of a site. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-21 20:30:09 +02:00
Maciej Kurc 4bf494b76e Fixed top.py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-19 09:19:56 +02:00
Tomasz Michalak 35ee0830a7 047-hclk-ioi-pips: Add targeted todo list routing to vivado script 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-19 08:19:00 +02:00
Tomasz Michalak 8aaef604cb 047-hclk-ioi-pips: Filter out PIPs that are not being solved currently 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-19 08:19:00 +02:00
Tomasz Michalak 727d5ca377 fuzzers: Add fuzzer for HCLK_IOI3 PIPs 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-19 08:19:00 +02:00
Maciej Kurc 813f3a8570 Fixed a bug in Makefile 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-18 09:17:24 +02:00
Maciej Kurc c935d44fdc Added fuzzing of local inverters 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-18 09:17:24 +02:00
Maciej Kurc c880707d27 Final fixes to the fuzzer. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-18 09:17:24 +02:00
Maciej Kurc 3c30f9f34a Fixes to the fuzzer 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-18 09:17:24 +02:00
Maciej Kurc bbc908d6d8 Initial IODELAY fuzzer 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-18 09:17:24 +02:00
litghost db785ed575
Merge pull request #945 from antmicro/loop_check_print_format 
int_loop_check.py: Fix output formatting
 2019-07-17 09:01:36 -07:00
Tomasz Michalak d750e4fb43 int_loop_check.py: Fix output formatting 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-15 10:08:45 +02:00
Tomasz Michalak f5ba30a81c 038-cfg: Add fuzzer for the CFG tile 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-13 07:10:18 +02:00
litghost 36af12c149
Merge pull request #933 from antmicro/016-doutmux-amc31 
Fuzzer for DOUTMUX.MC31 and DFFMUX.MC31
 2019-07-10 15:47:33 -07:00
litghost 2d13b11f13
Merge pull request #935 from litghost/more_ilogic_bits 
Expand ILOGIC fuzzer to document additional ISERDES bits.
 2019-07-10 11:21:08 -07:00
Maciej Kurc b7fc6734d2 Ran format-py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:15:28 +02:00
Maciej Kurc 1e6b85b8a8 Increased number of specimens and CLBs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:07:11 +02:00
Maciej Kurc e08ce61fbe Modified 015 to include DFFMUX.MC31 for SLICEM 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:06:07 +02:00
Maciej Kurc 56cb76e90f Added a makefile which allows to fuzz features for both SLICEM and SLICEL but separate them during database merge. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 15:06:58 +02:00
litghost 05ef773e60
Merge pull request #938 from antmicro/mmcme2-base-addr-fix 
fuzzers: tilegrid: mmcme: LOC mmcme2_adv instances
 2019-07-09 21:14:29 -07:00
Karol Gugala b989c2fc05 fuzzers: tilegrid: mmcme: LOC mmcme2_adv instances 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-09 18:42:04 +02:00
Keith Rothman 280191ce0e Attempt to fix fuzzer error. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 17:16:45 -07:00
Keith Rothman 2a242bbd62 Expand ILOGIC fuzzer to document additional ISERDES bits. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 17:00:06 -07:00