mirror of https://github.com/openXC7/prjxray.git
Merge pull request #1212 from daveshah1/dspimprove
fuzzers: Improve DSP fuzzer
This commit is contained in:
litghost
GitHub
commit
e7667a8daf
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@ -1,13 +1,14 @@
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#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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from prjxray.segmaker import Segmaker, add_site_group_zero
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from prjxray.verilog import to_int
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from prjxray.verilog import quote
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import json
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def add(segmk, site, dsp, tag, bit, value, invert):
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tag = "%s.%s%s[%u]" % (dsp, ('Z' if invert else ''), tag, bit)
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def add(segmk, site, dsp, tag, bit, value, invert, is_vector=True):
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tag = "%s.%s%s%s" % (
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dsp, ('Z' if invert else ''), tag, '[%u]' % bit if is_vector else '')
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value = (~value if invert else value)
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value >>= bit
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return segmk.add_site_tag(site, tag, value & 1)
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@ -20,32 +21,65 @@ def run():
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with open('params.json', 'r') as fp:
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data = json.load(fp)
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used_dsps = set()
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for params in data['instances']:
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dsp = "DSP_0" if params['SITE'][-1] in "02468" else "DSP_1"
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site = params['SITE']
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add(segmk, site, dsp, 'ADREG', 0, to_int(params['ADREG']), 0)
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if params['USE_DPORT'] == quote(
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"TRUE") and params['USE_MULT'] != quote("NONE"):
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add(segmk, site, dsp, 'ADREG', 0, to_int(params['ADREG']), 1)
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add(segmk, site, dsp, 'ALUMODEREG', 0, to_int(params['ALUMODEREG']), 1)
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for i in range(2):
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add(segmk, site, dsp, 'AREG', i, to_int(params['AREG']), 1)
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if params['A_INPUT'] == quote("DIRECT"):
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add(
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segmk, site, dsp, 'AREG_0', 0,
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int(to_int(params['AREG']) == 0), 0, False)
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add(
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segmk, site, dsp, 'AREG_2', 0,
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int(to_int(params['AREG']) == 2), 0, False)
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for i in range(2):
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add(segmk, site, dsp, 'ACASCREG', i, to_int(params['ACASCREG']), 1)
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if params['B_INPUT'] == quote("DIRECT"):
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add(
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segmk, site, dsp, 'BREG_0', 0,
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int(to_int(params['BREG']) == 0), 0, False)
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add(
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segmk, site, dsp, 'BREG_2', 0,
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int(to_int(params['BREG']) == 2), 0, False)
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for i in range(2):
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add(segmk, site, dsp, 'BREG', i, to_int(params['BREG']), 1)
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if params['A_INPUT'] == quote("CASCADE"):
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add(
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segmk, site, dsp, 'AREG_2_ACASCREG_1', 0,
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int(
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to_int(params['AREG']) == 2
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and to_int(params['ACASCREG']) == 1), 0, False)
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add(
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segmk, site, dsp, 'AREG_2_ACASCREG_1', 0,
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int(
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to_int(params['AREG']) == 2
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and to_int(params['ACASCREG']) == 1), 1, False)
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for i in range(2):
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add(segmk, site, dsp, 'BCASCREG', i, to_int(params['BCASCREG']), 1)
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if params['B_INPUT'] == quote("CASCADE"):
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add(
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segmk, site, dsp, 'BREG_2_BCASCREG_1', 0,
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int(
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to_int(params['BREG']) == 2
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and to_int(params['BCASCREG']) == 1), 0, False)
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add(
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segmk, site, dsp, 'BREG_2_BCASCREG_1', 0,
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int(
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to_int(params['BREG']) == 2
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and to_int(params['BCASCREG']) == 1), 1, False)
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add(segmk, site, dsp, 'CARRYINREG', 0, to_int(params['CARRYINREG']), 1)
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add(
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segmk, site, dsp, 'CARRYINSELREG', 0,
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to_int(params['CARRYINSELREG']), 1)
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add(segmk, site, dsp, 'CREG', 0, to_int(params['CREG']), 1)
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add(segmk, site, dsp, 'DREG', 0, to_int(params['DREG']), 0)
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if params['USE_DPORT'] == quote(
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"TRUE") and params['USE_MULT'] != quote("NONE"):
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add(segmk, site, dsp, 'DREG', 0, to_int(params['DREG']), 1)
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add(segmk, site, dsp, 'INMODEREG', 0, to_int(params['INMODEREG']), 1)
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add(segmk, site, dsp, 'OPMODEREG', 0, to_int(params['OPMODEREG']), 1)
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add(segmk, site, dsp, 'PREG', 0, to_int(params['PREG']), 1)
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@ -63,13 +97,12 @@ def run():
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add(segmk, site, dsp, 'USE_DPORT', 0, BOOL[params['USE_DPORT']], 0)
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SIMD = {}
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SIMD[quote('ONE48')] = 0
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SIMD[quote('TWO24')] = 1
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SIMD[quote('FOUR12')] = 2
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for i in range(2):
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add(segmk, site, dsp, 'USE_SIMD', i, SIMD[params['USE_SIMD']], 0)
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add(
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segmk, site, dsp, 'USE_SIMD_FOUR12', 0,
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params['USE_SIMD'] == quote("FOUR12"), 0, False)
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add(
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segmk, site, dsp, 'USE_SIMD_FOUR12_TWO24', 0,
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params['USE_SIMD'] in (quote("TWO24"), quote("FOUR12")), 0, False)
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MULT = {}
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MULT[quote('NONE')] = 0
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@ -87,11 +120,12 @@ def run():
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AUTORESET[quote('RESET_MATCH')] = 2
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add(
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segmk, site, dsp, 'AUTORESET_PATDET', 0,
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AUTORESET[params['AUTORESET_PATDET']], 0)
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segmk, site, dsp, 'AUTORESET_PATDET_RESET_NOT_MATCH', 0,
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params['AUTORESET_PATDET'] == quote("RESET_NOT_MATCH"), 0, False)
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add(
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segmk, site, dsp, 'AUTORESET_PATDET', 1,
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AUTORESET[params['AUTORESET_PATDET']], 1)
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segmk, site, dsp, 'AUTORESET_PATDET_RESET', 0,
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params['AUTORESET_PATDET'] in (
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quote("RESET_NOT_MATCH"), quote("RESET_MATCH")), 0, False)
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for i in range(48):
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add(segmk, site, dsp, 'MASK', i, to_int(params['MASK']), 0)
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@ -99,16 +133,12 @@ def run():
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for i in range(48):
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add(segmk, site, dsp, 'PATTERN', i, to_int(params['PATTERN']), 0)
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SEL_MASK = {}
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SEL_MASK[quote('MASK')] = 0
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SEL_MASK[quote('C')] = 1
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SEL_MASK[quote('ROUNDING_MODE1')] = 2
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SEL_MASK[quote('ROUNDING_MODE2')] = 3
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for i in range(2):
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add(
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segmk, site, dsp, 'SEL_MASK', i, SEL_MASK[params['SEL_MASK']],
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0)
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if params['USE_PATTERN_DETECT'] == quote("PATDET"):
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add_site_group_zero(
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segmk, site, dsp + ".", [
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"SEL_MASK_%s" % x
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for x in ["MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2"]
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], "SEL_MASK_MASK", "SEL_MASK_%s" % (params['SEL_MASK'][1:-1]))
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USE_PATTERN_DETECT = {}
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USE_PATTERN_DETECT[quote('NO_PATDET')] = 0
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@ -118,6 +148,21 @@ def run():
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segmk, site, dsp, 'USE_PATTERN_DETECT', 0,
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USE_PATTERN_DETECT[params['USE_PATTERN_DETECT']], 0)
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inv_ports = [
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("ALUMODE", 4),
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("CARRYIN", 1),
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("CLK", 1),
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("INMODE", 5),
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("OPMODE", 7),
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]
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for port, width in inv_ports:
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param = 'IS_{}_INVERTED'.format(port)
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for i in range(width):
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add(
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segmk, site, dsp, param, i, to_int(params[param]), 1,
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width > 1)
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segmk.compile()
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segmk.write()
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@ -49,14 +49,14 @@ def run():
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ports['A'] = '{30{1\'b1}}'
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ports['ACIN'] = '{30{1\'b1}}'
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ports['ACOUT'] = '30\'b0'
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ports['ALUMODE'] = '4\'b1'
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ports['ALUMODE'] = 'din[3:0]'
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ports['B'] = '{18{1\'b1}}'
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ports['BCIN'] = '{18{1\'b1}}'
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ports['BCOUT'] = '18\'b0'
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ports['C'] = '{48{1\'b1}}'
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ports['CARRYCASCIN'] = '1\'b1'
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ports['CARRYCASCOUT'] = '1\'b0'
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ports['CARRYIN'] = '1\'b1'
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ports['CARRYIN'] = 'din[4]'
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ports['CARRYINSEL'] = '3\'b000'
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ports['CARRYOUT'] = '4\'b0'
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ports['CEA1'] = '1\'b1'
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@ -72,12 +72,12 @@ def run():
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ports['CEINMODE'] = '1\'b1'
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ports['CEM'] = '1\'b1'
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ports['CEP'] = '1\'b1'
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ports['CLK'] = '1\'b1'
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ports['CLK'] = 'clk'
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ports['D'] = '{25{1\'b1}}'
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ports['INMODE'] = '5\'b11111'
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ports['INMODE'] = 'din[9:5]'
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#ports['MULTISIGNIN'] = '1\'b1'
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#ports['MULTISIGNOUT'] = '1\'b0'
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ports['OPMODE'] = '7\'b1111111'
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ports['OPMODE'] = 'din[16:10]'
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ports['OVERFLOW'] = '1\'b0'
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ports['P'] = '48\'b0'
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ports['PATTERNBDETECT'] = '1\'b0'
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@ -133,6 +133,12 @@ def run():
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params['USE_PATTERN_DETECT'] = verilog.quote(
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fuzz(('NO_PATDET', 'PATDET')))
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params['IS_ALUMODE_INVERTED'] = fuzz(4)
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params['IS_CARRYIN_INVERTED'] = fuzz((0, 1))
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params['IS_CLK_INVERTED'] = fuzz((0, 1))
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params['IS_INMODE_INVERTED'] = fuzz(5)
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params['IS_OPMODE_INVERTED'] = fuzz(7)
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verilog.instance(synthesis + ' ' + module, instance, ports, params)
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params['TILE'] = tile
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