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Document some combo DATA_WIDTH bits. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-07-31 15:32:09 -07:00
parent fb2071895d
commit e81a2fb93d
2 changed files with 16 additions and 5 deletions
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5
fuzzers/036-iob-ologic/bits.dbf
View File

@ -1,3 +1,6 @@
31_92,IOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE
30_35,IOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE
33_91 33_93
32_36 32_34
30_127 31_126 31_124 30_121 31_120 30_123 31_116
31_00 30_01 30_03 31_06 30_07 31_04 30_11

16
fuzzers/036-iob-ologic/generate.py
View File

@ -19,14 +19,22 @@ def handle_data_width(segmk, d):
if 'DATA_WIDTH' not in d:
return
if d['DATA_RATE_OQ'] == 'DDR':
return
for opt in [2, 3, 4, 5, 6, 7, 8, 10, 14]:
for opt in [2, 3, 4, 5, 6, 7, 8]:
segmk.add_site_tag(
d['site'], 'OSERDESE.DATA_WIDTH.W{}'.format(opt),
d['DATA_WIDTH'] == opt)
if verilog.unquote(d['DATA_RATE_OQ']) == 'DDR':
WEIRD_BIT = [6, 8]
segmk.add_site_tag(
d['site'], 'OSERDESE.DATA_WIDTH.DDR.W{}'.format(
'_'.join(map(str, WEIRD_BIT))), d['DATA_WIDTH'] in WEIRD_BIT)
else:
WEIRD_BIT = [2, 4, 5, 6]
segmk.add_site_tag(
d['site'], 'OSERDESE.DATA_WIDTH.SDR.W{}'.format(
'_'.join(map(str, WEIRD_BIT))), d['DATA_WIDTH'] in WEIRD_BIT)
def main():
print("Loading tags")