mirror of https://github.com/openXC7/prjxray.git
Added forcing of manual routing through "BB" pips to toggle more bits.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
03b0b9cefc
commit
cc7ba29c6b
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@ -10,9 +10,6 @@ def bitfilter(frame, word):
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if frame < 28:
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return False
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if frame == 25 and word == 3121:
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return False
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return True
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@ -69,15 +66,17 @@ def bus_tags(segmk, ps, site):
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site, 'COMP.' + opt + '_Z' + conn + '_' + ps['site'], opt_match
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and not conn_match)
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match = verilog.unquote(ps['COMPENSATION']) in ['BUF_IN', 'EXTERNAL']
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bufg_on_clkin = \
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'BUFG' in ps['clkin1_conn'] or \
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'BUFG' in ps['clkin2_conn']
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if not match:
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if verilog.unquote(ps['COMPENSATION']) == 'ZHOLD' and bufg_on_clkin:
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match = True
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segmk.add_site_tag(
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site, 'COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF', match)
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# This one is in conflict with some clock routing bits.
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# match = verilog.unquote(ps['COMPENSATION']) in ['BUF_IN', 'EXTERNAL']
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# if not match:
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# if verilog.unquote(ps['COMPENSATION']) == 'ZHOLD' and bufg_on_clkin:
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# match = True
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# segmk.add_site_tag(
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# site, 'COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF', match)
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match = verilog.unquote(ps['COMPENSATION']) in ['ZHOLD']
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segmk.add_site_tag(
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@ -98,7 +97,8 @@ def bus_tags(segmk, ps, site):
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site == "PLLE2_ADV_X0Y2"
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)
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for opt in ['ZHOLD', 'BUF_IN', 'EXTERNAL', 'INTERNAL']:
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# No INTERNAL as it has conflicting bits
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for opt in ['ZHOLD', 'BUF_IN', 'EXTERNAL']:
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if opt in ['BUF_IN', 'EXTERNAL']:
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if ps['clkfbin_conn'] not in ['', 'clk']:
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continue
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@ -115,9 +115,11 @@ def bus_tags(segmk, ps, site):
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site, 'COMPENSATION.Z_' + opt,
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verilog.unquote(ps['COMPENSATION']) != opt)
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segmk.add_site_tag(
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site, 'COMPENSATION.INTERNAL',
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verilog.unquote(ps['COMPENSATION']) in ['INTERNAL'])
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# This one has bits that are in conflict with clock routing
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# segmk.add_site_tag(
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# site, 'COMPENSATION.INTERNAL',
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# verilog.unquote(ps['COMPENSATION']) in ['INTERNAL'])
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for param in ['CLKFBOUT_MULT']:
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paramadj = int(ps[param])
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@ -1,11 +1,47 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc make_manual_routes {filename} {
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puts "MANROUTE: Loading routes from $filename"
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set fp [open $filename r]
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foreach line [split [read $fp] "\n"] {
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if {$line eq ""} {
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continue
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}
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puts "MANROUTE: Line: $line"
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# Parse the line
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set fields [split $line " "]
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set net_name [lindex $fields 0]
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set wire_name [lindex $fields 1]
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# Check if that net exist
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if {[get_nets $net_name] eq ""} {
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puts "MANROUTE: net $net_name does not exist"
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continue
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}
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# Make the route
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set status [route_via $net_name [list $wire_name] 0]
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# Failure, skip manual routing of this net
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if { $status != 1 } {
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puts "MANROUTE: Manual routing failed!"
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set net [get_nets $net_name]
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set_property -quiet FIXED_ROUTE "" $net
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set_property IS_ROUTE_FIXED 0 $net
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continue
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}
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puts "MANROUTE: Success!"
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}
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}
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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#set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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@ -13,11 +49,6 @@ set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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create_clock -period 10.00 [get_ports clkin1*]
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create_clock -period 10.00 [get_ports clkin2*]
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#set net [get_nets clk_IBUF]
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#if { [llength $net] > 0 } {
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# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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#}
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# Disable MMCM frequency etc sanity checks
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
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@ -33,7 +64,28 @@ set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
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set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
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place_design
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route_design
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write_checkpoint -force design_placed.dcp
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make_manual_routes routes.txt
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write_checkpoint -force design_pre_route.dcp
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route_design -directive Quick -preserve
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set unrouted_nets [get_nets -filter {ROUTE_STATUS!="ROUTED"}]
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if {[llength $unrouted_nets] ne 0} {
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puts "MANROUTE: Got unrouted nets: $unrouted_nets"
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puts "MANROUTE: Ripping up and starting again with no fixed routes"
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route_design -unroute
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set fixed_nets [get_nets -filter {IS_ROUTE_FIXED==1}]
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if {[llength $fixed_nets] ne 0} {
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set_property FIXED_ROUTE "" $fixed_nets
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set_property IS_ROUTE_FIXED 0 $fixed_nets
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}
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route_design -directive Quick
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}
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -18,7 +18,7 @@ def gen_sites():
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['PLLE2_ADV']:
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yield tile_type, site_name
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yield tile_name, tile_type, site_name
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def main():
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@ -30,7 +30,8 @@ def main():
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routes_file = open('routes.txt', 'w')
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print("""
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print(
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"""
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module top(
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input [{N}:0] clkin1,
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input [{N}:0] clkin2,
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@ -42,24 +43,22 @@ module top(
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LUT1 dummy();
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""".format(N=max_sites - 1))
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for tile_type, site in sorted(gen_sites()):
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for i, (
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tile_name,
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tile_type,
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site,
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) in enumerate(sorted(gen_sites())):
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params = {
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"site":
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site,
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'active':
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random.random() > .2,
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"clkin1_conn":
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random.choice((
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"clkfbout_mult_BUFG_" + site,
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"clkin1[{}]".format(i),
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""
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)),
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random.choice(
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("clkfbout_mult_BUFG_" + site, "clkin1[{}]".format(i), "")),
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"clkin2_conn":
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random.choice((
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"clkfbout_mult_BUFG_" + site,
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"clkin2[{}]".format(i),
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""
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)),
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random.choice(
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("clkfbout_mult_BUFG_" + site, "clkin2[{}]".format(i), "")),
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"dclk_conn":
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random.choice((
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"0",
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@ -143,30 +142,59 @@ module top(
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params['clkfbin_conn'] = random.choice(
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("", "clkfb[{}]".format(i), "clkfbout_mult_BUFG_" + site))
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params['clkin1_route'] = random.choice((
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"{}_CLKIN1",
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"{}_FREQ_BB0",
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"{}_FREQ_BB1",
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"{}_FREQ_BB2",
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"{}_FREQ_BB3",
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"{}_PLLE2_CLK_IN1_INT",
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)).format(tile_type)
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params['clkin1_route'] = random.choice(
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(
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"{}_CLKIN1",
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"{}_FREQ_BB0",
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"{}_FREQ_BB1",
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"{}_FREQ_BB2",
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"{}_FREQ_BB3",
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"{}_PLLE2_CLK_IN1_INT",
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)).format(tile_type)
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params['clkin2_route'] = random.choice((
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"{}_CLKIN2",
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"{}_FREQ_BB0",
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"{}_FREQ_BB1",
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"{}_FREQ_BB2",
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"{}_FREQ_BB3",
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"{}_PLLE2_CLK_IN2_INT",
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)).format(tile_type)
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params['clkin2_route'] = random.choice(
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(
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"{}_CLKIN2",
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"{}_FREQ_BB0",
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"{}_FREQ_BB1",
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"{}_FREQ_BB2",
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"{}_FREQ_BB3",
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"{}_PLLE2_CLK_IN2_INT",
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)).format(tile_type)
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f.write('%s\n' % (json.dumps(params, indent=1)))
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params['clkfbin_route'] = random.choice(
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(
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"{}_CLKFBOUT2IN",
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"{}_UPPER_T_FREQ_BB0",
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"{}_UPPER_T_FREQ_BB1",
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"{}_UPPER_T_FREQ_BB2",
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"{}_UPPER_T_FREQ_BB3",
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"{}_UPPER_T_PLLE2_CLK_FB_INT",
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)).format(tile_type.replace("_UPPER_T", ""))
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f.write('%s\n' % (json.dumps(params)))
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def make_ibuf_net(net):
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p = net.find('[')
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return net[:p] + '_IBUF' + net[p:]
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if params['clkin1_conn'] != "":
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routes_file.write('{} {}\n'.format(params['clkin1_conn'], params['clkin1_route']))
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net = make_ibuf_net(params['clkin1_conn'])
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wire = '{}/{}'.format(tile_name, params['clkin1_route'])
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routes_file.write('{} {}\n'.format(net, wire))
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if params['clkin2_conn'] != "":
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routes_file.write('{} {}\n'.format(params['clkin2_conn'], params['clkin2_route']))
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net = make_ibuf_net(params['clkin2_conn'])
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wire = '{}/{}'.format(tile_name, params['clkin2_route'])
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routes_file.write('{} {}\n'.format(net, wire))
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if params['clkfbin_conn'] != "" and\
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params['clkfbin_conn'] != ("clkfbout_mult_BUFG_" + site):
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net = params['clkfbin_conn']
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if "[" in net and "]" in net:
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net = make_ibuf_net(net)
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wire = '{}/{}'.format(tile_name, params['clkfbin_route'])
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routes_file.write('{} {}\n'.format(net, wire))
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if not params['active']:
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continue
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