mirror of https://github.com/openXC7/prjxray.git
Ran format-py
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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@ -67,17 +67,19 @@ for loc, muxes in cache.items():
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tag = "%sFFMUX.%s" % (which, src)
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segmk.add_site_tag(loc, tag, 0)
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def bitfilter(frame_idx, bit_idx):
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# Since the SRL32 is enabled along with DFFMUX.MC31, bits related to
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# SRL32 features are masked out.
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if (frame_idx, bit_idx) in [
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(30, 16), # ALUT.SRL
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( 1, 23), # WEMUX.CE
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(1, 23), # WEMUX.CE
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]:
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return False
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return util.bitfilter_clb_mux(frame_idx, bit_idx)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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@ -9,16 +9,19 @@ INCREMENT = os.getenv('CLBN', 0)
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CLBN = 600 + int(INCREMENT)
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print('//Requested CLBs: %s' % str(CLBN))
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def gen_slicels():
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['SLICEL']):
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yield site_name
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def gen_slicems():
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['SLICEM']):
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yield site_name
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DIN_N = CLBN * 8
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DOUT_N = CLBN * 8
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@ -37,7 +40,7 @@ for i in range(CLBN):
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if use_slicem:
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loc = next(slicems)
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variants = ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR', 'MC31']
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variants = ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR', 'MC31']
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else:
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loc = next(slicels)
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variants = ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR']
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@ -87,9 +87,9 @@ def bitfilter(frame_idx, bit_idx):
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(30, 19),
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(31, 19), # B5MA
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(30, 9),
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(31, 8), # A5MA
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(31, 8), # A5MA
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(30, 16), # ALUT.SRL
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( 1, 23), # WEMUX.CE
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(1, 23), # WEMUX.CE
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]:
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return False
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@ -9,6 +9,7 @@ INCREMENT = os.getenv('CLBN', 0)
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CLBN = 600 + int(INCREMENT)
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print('//Requested CLBs: %s' % str(CLBN))
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def gen_slicels():
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['SLICEL']):
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@ -20,6 +21,7 @@ def gen_slicems():
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['SLICEM']):
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yield site_name
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DIN_N = CLBN * 8
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DOUT_N = CLBN * 8
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