Ran format-py

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-07-10 16:15:28 +02:00
parent 1e6b85b8a8
commit b7fc6734d2
4 changed files with 12 additions and 5 deletions

View File

@ -67,17 +67,19 @@ for loc, muxes in cache.items():
tag = "%sFFMUX.%s" % (which, src)
segmk.add_site_tag(loc, tag, 0)
def bitfilter(frame_idx, bit_idx):
# Since the SRL32 is enabled along with DFFMUX.MC31, bits related to
# SRL32 features are masked out.
if (frame_idx, bit_idx) in [
(30, 16), # ALUT.SRL
( 1, 23), # WEMUX.CE
(1, 23), # WEMUX.CE
]:
return False
return util.bitfilter_clb_mux(frame_idx, bit_idx)
segmk.compile(bitfilter=bitfilter)
segmk.write()

View File

@ -9,16 +9,19 @@ INCREMENT = os.getenv('CLBN', 0)
CLBN = 600 + int(INCREMENT)
print('//Requested CLBs: %s' % str(CLBN))
def gen_slicels():
for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
['SLICEL']):
yield site_name
def gen_slicems():
for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
['SLICEM']):
yield site_name
DIN_N = CLBN * 8
DOUT_N = CLBN * 8
@ -37,7 +40,7 @@ for i in range(CLBN):
if use_slicem:
loc = next(slicems)
variants = ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR', 'MC31']
variants = ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR', 'MC31']
else:
loc = next(slicels)
variants = ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR']

View File

@ -87,9 +87,9 @@ def bitfilter(frame_idx, bit_idx):
(30, 19),
(31, 19), # B5MA
(30, 9),
(31, 8), # A5MA
(31, 8), # A5MA
(30, 16), # ALUT.SRL
( 1, 23), # WEMUX.CE
(1, 23), # WEMUX.CE
]:
return False

View File

@ -9,6 +9,7 @@ INCREMENT = os.getenv('CLBN', 0)
CLBN = 600 + int(INCREMENT)
print('//Requested CLBs: %s' % str(CLBN))
def gen_slicels():
for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
['SLICEL']):
@ -20,6 +21,7 @@ def gen_slicems():
['SLICEM']):
yield site_name
DIN_N = CLBN * 8
DOUT_N = CLBN * 8