mirror of https://github.com/openXC7/prjxray.git
litghost
GitHub
commit
9d0065a768
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@ -39,6 +39,10 @@ DB_SIMPLE=\
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$(addsuffix _r, $(DB_SIMPLE_LR) $(DB_SIMPLE_R)) \
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segbits_cmt_top_l_upper_t \
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segbits_cmt_top_r_upper_t \
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segbits_lioi3 \
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segbits_rioi3 \
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segbits_liob33 \
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segbits_riob33
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BLOCK_RAM_EXTRA_FOR=\
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mask_bram \
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@ -0,0 +1,50 @@
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export FUZDIR=$(shell pwd)
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PIP_TYPE?=ioi3
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PIPLIST_TCL=$(FUZDIR)/ioi3_pip_list.tcl
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TODO_RE="[LR]IOI3\.(IOI_([IO]LOGIC[01]_CLK(DIV|B)?)|(IOI_OCLK_[01]))\..*"
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EXCLUDE_RE=".*\..*\.(?=IOI_((PHASER)|(OCLK)|(IMUX22_1))).*"
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MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE) --sides "xr,xl" --exclude-re $(EXCLUDE_RE)
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N = 40
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A_PIPLIST=lioi3.txt
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SEGMATCH_FLAGS=-c -1 -m 20 -M 50
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SPECIMENS_DEPS=build/cmt_regions.csv
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include ../pip_loop.mk
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build/segbits_ioi3_x.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_ioi3_x.rdb \
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$(shell find build -name segdata_lioi3*.txt) $(shell find build -name segdata_rioi3*.txt)
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RDBS = build/segbits_ioi3_x.rdb
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database: ${RDBS}
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_ioi3_x.rdb \
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--seg-fn-out build/segbits_ioi3_x.db
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# Keep a copy to track iter progress
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cp build/segbits_ioi3_x.rdb build/$(ITER)/segbits_ioi3_x.rdb
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cp build/segbits_ioi3_x.db build/$(ITER)/segbits_ioi3_x.db
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# Clobber existing .db to eliminate potential conflicts
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cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db build/database/${XRAY_DATABASE}
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} lioi3 build/segbits_ioi3_x.db
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} rioi3 build/segbits_ioi3_x.db
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build/cmt_regions.csv: output_cmt.tcl
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mkdir -p build
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cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_cmt.tcl
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pushdb: database
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${XRAY_MERGEDB} lioi3 build/segbits_ioi3_x.db
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${XRAY_MERGEDB} rioi3 build/segbits_ioi3_x.db
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${XRAY_MERGEDB} lioi3_tbytesrc build/segbits_ioi3_x.db
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${XRAY_MERGEDB} rioi3_tbytesrc build/segbits_ioi3_x.db
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${XRAY_MERGEDB} lioi3_tbyteterm build/segbits_ioi3_x.db
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${XRAY_MERGEDB} rioi3_tbyteterm build/segbits_ioi3_x.db
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.PHONY: database pushdb
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@ -0,0 +1,104 @@
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#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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import os, re
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import os.path
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def bitfilter(frame, word):
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if frame < 28:
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return False
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return True
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def main():
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segmk = Segmaker("design.bits")
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tiledata = {}
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pipdata = {}
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ignpip = set()
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'ioi3', 'lioi3.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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pipdata[tile_type].append((src, dst))
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'ioi3', 'rioi3.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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pipdata[tile_type].append((src, dst))
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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if not tile.startswith('LIOI3') and not tile.startswith('RIOI3'):
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continue
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log = open("log.txt", "a")
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print(line, file=log)
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pip_prefix, _ = pip.split(".")
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tile_from_pip, tile_type = pip_prefix.split('/')
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_, src = src.split("/")
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_, dst = dst.split("/")
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pnum = int(pnum)
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pdir = int(pdir)
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if tile not in tiledata:
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tiledata[tile] = {
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"type": tile_type,
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"pips": set(),
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"srcs": set(),
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"dsts": set(),
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}
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tiledata[tile]["pips"].add((src, dst))
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tiledata[tile]["srcs"].add(src)
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tiledata[tile]["dsts"].add(dst)
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if pdir == 0:
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tiledata[tile]["srcs"].add(dst)
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tiledata[tile]["dsts"].add(src)
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if pnum == 1 or pdir == 0:
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print("Ignoring pip: {}".format(pip), file=log)
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ignpip.add((src, dst))
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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if tile_type.startswith('LIOI3'):
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tile_type = 'LIOI3'
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elif tile_type.startswith('RIOI3'):
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tile_type = 'RIOI3'
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pips = pips_srcs_dsts["pips"]
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for src, dst in pipdata[tile_type]:
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if (src, dst) in ignpip:
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pass
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if re.match(r'.*PHASER.*', src) or re.match(r'.*CLKDIV[PFB].*',
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dst):
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pass
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elif (src, dst) in tiledata[tile]["pips"]:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif dst not in tiledata[tile]["dsts"]:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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internal_feedback = False
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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if __name__ == "__main__":
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main()
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@ -0,0 +1,55 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc write_pip_txtdata {filename} {
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puts "FUZ([pwd]): Writing $filename."
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set fp [open $filename w]
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set nets [get_nets -hierarchical]
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set nnets [llength $nets]
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set neti 0
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foreach net $nets {
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incr neti
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if {($neti % 100) == 0 } {
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puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)"
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}
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foreach pip [get_pips -of_objects $net] {
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set tile [get_tiles -of_objects $pip]
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set src_wire [get_wires -uphill -of_objects $pip]
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set dst_wire [get_wires -downhill -of_objects $pip]
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set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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set dir_prop [get_property IS_DIRECTIONAL $pip]
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puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
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}
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}
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close $fp
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-74}]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-4}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-5}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-13}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-98}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-99}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-115}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-144}]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design
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write_checkpoint -force design_before_route.dcp
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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run
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@ -0,0 +1,39 @@
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proc print_tile_pips {tile_type filename} {
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set fp [open $filename w]
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set pips [dict create]
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foreach tile [get_tiles -filter "TYPE == $tile_type"] {
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puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
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foreach pip [lsort [get_pips -of_objects $tile]] {
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set src [get_wires -uphill -of_objects $pip]
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set dst [get_wires -downhill -of_objects $pip]
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# Skip pips with disconnected nodes
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set src_node [get_nodes -of_objects $src]
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if { $src_node == {} } {
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continue
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}
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set dst_node [get_nodes -of_objects $src]
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if { $dst_node == {} } {
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continue
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}
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if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
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set pip_string "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
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if ![dict exists $pips $pip_string] {
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puts $fp $pip_string
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dict set pips $pip_string 1
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}
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}
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}
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}
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close $fp
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}
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create_project -force -part $::env(XRAY_PART) design design
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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print_tile_pips LIOI3 lioi3.txt
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print_tile_pips RIOI3 rioi3.txt
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@ -0,0 +1,11 @@
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create_project -force -part $::env(XRAY_PART) design design
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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set fp [open "cmt_regions.csv" "w"]
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foreach site_type {MMCME2_ADV BUFHCE BUFR BUFMRCE BUFIO ILOGICE3 OLOGICE3 IDELAYE2 IDELAYCTRL PLLE2_ADV} {
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foreach site [get_sites -filter "SITE_TYPE == $site_type"] {
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puts $fp "$site,[get_property CLOCK_REGION $site]"
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}
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}
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close $fp
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@ -0,0 +1,345 @@
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import os
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import random
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import math
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray import lut_maker
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from prjxray.db import Database
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NOT_INCLUDED_TILES = ['LIOI3_SING', 'RIOI3_SING']
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SITE_TYPES = ['OLOGICE3', 'ILOGICE3']
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def read_site_to_cmt():
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""" Yields clock sources and which CMT they route within. """
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with open(os.path.join(os.getenv('FUZDIR'), 'build',
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'cmt_regions.csv')) as f:
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for l in f:
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site, cmt = l.strip().split(',')
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yield (site, cmt)
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def gen_sites():
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''' Return dict of ISERDES/OSERDES locations. '''
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db = Database(util.get_db_root())
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grid = db.grid()
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xy_fun = util.create_xy_fun('\S+')
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tiles = grid.tiles()
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for tile_name in sorted(tiles):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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tile_type = gridinfo.tile_type
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tile = {'tile': tile_name, 'tile_type': tile_type, 'ioi_sites': {}}
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for site_name, site_type in gridinfo.sites.items():
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if site_type in SITE_TYPES:
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xy = xy_fun(site_name)
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if xy not in tile['ioi_sites']:
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tile['ioi_sites'][xy] = {}
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tile['ioi_sites'][xy][site_type] = site_name
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yield tile
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class ClockSources(object):
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def __init__(self):
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self.site_to_cmt = dict(read_site_to_cmt())
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self.leaf_gclks = {}
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self.ioclks = {}
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self.rclks = {}
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self.selected_leaf_gclks = {}
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self.lut_maker = lut_maker.LutMaker()
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for cmt in set(self.site_to_cmt.values()):
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self.leaf_gclks[cmt] = []
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self.ioclks[cmt] = []
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self.rclks[cmt] = []
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def init_clocks(self):
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""" Initialize all IOI clock sources. """
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for site, cmt in self.site_to_cmt.items():
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clk = 'clk_' + site
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if 'BUFHCE' in site:
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print(
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"""
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wire {clk};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFH bufh_{site}(
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.O({clk})
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);
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""".format(
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clk=clk,
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site=site,
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))
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self.leaf_gclks[cmt].append(clk)
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if 'BUFIO' in site:
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print(
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"""
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wire {clk};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFIO bufio_{site}(
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.O({clk})
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);
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""".format(
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clk=clk,
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site=site,
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))
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self.ioclks[cmt].append(clk)
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if 'BUFR' in site:
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print(
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"""
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wire {clk};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFR bufr_{site}(
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.O({clk})
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);
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""".format(
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clk=clk,
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site=site,
|
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))
|
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|
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self.rclks[cmt].append(clk)
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# Choose 6 leaf_gclks to be used in each CMT.
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for cmt in self.leaf_gclks:
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self.selected_leaf_gclks[cmt] = random.sample(
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self.leaf_gclks[cmt], 6)
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def get_clock(
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self,
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site,
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allow_ioclks,
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allow_rclks,
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allow_fabric=True,
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allow_empty=True):
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cmt = self.site_to_cmt[site]
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choices = []
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if allow_fabric:
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choices.append('lut')
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if allow_empty:
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choices.append('')
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choices.extend(self.selected_leaf_gclks[cmt])
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||||
if allow_ioclks:
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choices.extend(self.ioclks[cmt])
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if allow_rclks:
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choices.extend(self.rclks[cmt])
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|
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clock = random.choice(choices)
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is_lut = False
|
||||
if clock == "lut":
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||||
clock = self.lut_maker.get_next_output_net()
|
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is_lut = True
|
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return clock, is_lut
|
||||
|
||||
|
||||
def add_port(ports, port, signal):
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ports.append('.{}({})'.format(port, signal))
|
||||
|
||||
|
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def run():
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print("module top();")
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||||
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||||
clocks = ClockSources()
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||||
clocks.init_clocks()
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"""
|
||||
|
||||
ISERDESE2 clock sources:
|
||||
|
||||
CLK/CLKB:
|
||||
- Allows LEAF_GCLK, IOCLKS, RCLKS and fabric
|
||||
- Dedicated pips
|
||||
|
||||
CLKDIV:
|
||||
- No dedicated pips, uses fabric clock in.
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||||
|
||||
CLKDIVP:
|
||||
- Has pips, MIG only, PHASER or fabric.
|
||||
|
||||
OCLK/OCLKB:
|
||||
- Allows LEAF_GCLK, IOCLKS, RCLKS and fabric
|
||||
- Must match OSERDESE2:CLK/CLKB
|
||||
|
||||
OSERDESE2 clock sources:
|
||||
|
||||
CLKDIV/CLKDIVB:
|
||||
- Allows LEAF_GCLK and RCLKS and fabric
|
||||
- Dedicated pips
|
||||
|
||||
CLKDIVF/CLKDIVFB:
|
||||
- Allows LEAF_GCLK and RCLKS and fabric
|
||||
- No explicit port, follows CLKDIV/CLKDIVB?
|
||||
"""
|
||||
|
||||
output = []
|
||||
|
||||
for tile in gen_sites():
|
||||
if tile['tile_type'] in NOT_INCLUDED_TILES:
|
||||
continue
|
||||
|
||||
for xy in tile['ioi_sites']:
|
||||
ilogic_site_type = random.choice([None, 'ISERDESE2', 'IDDR'])
|
||||
use_oserdes = random.randint(0, 1)
|
||||
|
||||
ilogic_site = tile['ioi_sites'][xy]['ILOGICE3']
|
||||
ologic_site = tile['ioi_sites'][xy]['OLOGICE3']
|
||||
|
||||
if use_oserdes:
|
||||
oclk, _ = clocks.get_clock(
|
||||
ologic_site, allow_ioclks=True, allow_rclks=True)
|
||||
|
||||
oclkb = oclk
|
||||
else:
|
||||
oclk, is_lut = clocks.get_clock(
|
||||
ilogic_site, allow_ioclks=True, allow_rclks=True)
|
||||
|
||||
if random.randint(0, 1):
|
||||
oclkb = oclk
|
||||
else:
|
||||
oclkb, _ = clocks.get_clock(
|
||||
ilogic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True,
|
||||
allow_fabric=not is_lut)
|
||||
|
||||
DATA_RATE = random.choice(['DDR', 'SDR'])
|
||||
clk, is_lut = clocks.get_clock(
|
||||
ilogic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True,
|
||||
allow_empty=DATA_RATE == 'SDR')
|
||||
if False:
|
||||
clkb = clk
|
||||
else:
|
||||
clkb = clk
|
||||
while clkb == clk:
|
||||
clkb, _ = clocks.get_clock(
|
||||
ilogic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True,
|
||||
allow_empty=False)
|
||||
|
||||
if ilogic_site_type is None:
|
||||
pass
|
||||
elif ilogic_site_type == 'ISERDESE2':
|
||||
INTERFACE_TYPE = random.choice(
|
||||
[
|
||||
'MEMORY',
|
||||
'MEMORY_DDR3',
|
||||
'MEMORY_QDR',
|
||||
'NETWORKING',
|
||||
'OVERSAMPLE',
|
||||
])
|
||||
ports = []
|
||||
|
||||
add_port(ports, 'CLK', clk)
|
||||
add_port(ports, 'CLKB', clkb)
|
||||
add_port(ports, 'OCLK', oclk)
|
||||
add_port(ports, 'OCLKB', oclkb)
|
||||
|
||||
output.append(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH, LOC="{site}" *)
|
||||
ISERDESE2 #(
|
||||
.DATA_RATE({DATA_RATE}),
|
||||
.INTERFACE_TYPE({INTERFACE_TYPE}),
|
||||
.IS_CLK_INVERTED({IS_CLK_INVERTED}),
|
||||
.IS_CLKB_INVERTED({IS_CLKB_INVERTED}),
|
||||
.INIT_Q1({INIT_Q1}),
|
||||
.INIT_Q2({INIT_Q2}),
|
||||
.INIT_Q3({INIT_Q3}),
|
||||
.INIT_Q4({INIT_Q4}),
|
||||
.SRVAL_Q1({SRVAL_Q1}),
|
||||
.SRVAL_Q2({SRVAL_Q2}),
|
||||
.SRVAL_Q3({SRVAL_Q3}),
|
||||
.SRVAL_Q4({SRVAL_Q4})
|
||||
) iserdes_{site}(
|
||||
{ports});""".format(
|
||||
site=ilogic_site,
|
||||
ports=',\n'.join(ports),
|
||||
DATA_RATE=verilog.quote(DATA_RATE),
|
||||
INTERFACE_TYPE=verilog.quote(INTERFACE_TYPE),
|
||||
IS_CLK_INVERTED=random.randint(0, 1),
|
||||
IS_CLKB_INVERTED=random.randint(0, 1),
|
||||
INIT_Q1=random.randint(0, 1),
|
||||
INIT_Q2=random.randint(0, 1),
|
||||
INIT_Q3=random.randint(0, 1),
|
||||
INIT_Q4=random.randint(0, 1),
|
||||
SRVAL_Q1=random.randint(0, 1),
|
||||
SRVAL_Q2=random.randint(0, 1),
|
||||
SRVAL_Q3=random.randint(0, 1),
|
||||
SRVAL_Q4=random.randint(0, 1),
|
||||
))
|
||||
elif ilogic_site_type == 'IDDR':
|
||||
ports = []
|
||||
add_port(ports, 'C', clk)
|
||||
add_port(ports, 'CB', clkb)
|
||||
|
||||
output.append(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH, LOC="{site}" *)
|
||||
IDDR_2CLK #(
|
||||
.INIT_Q1({INIT_Q1}),
|
||||
.INIT_Q2({INIT_Q2}),
|
||||
.SRTYPE({SRTYPE})
|
||||
) iserdes_{site}(
|
||||
{ports});""".format(
|
||||
site=ilogic_site,
|
||||
ports=',\n'.join(ports),
|
||||
INIT_Q1=random.randint(0, 1),
|
||||
INIT_Q2=random.randint(0, 1),
|
||||
SRTYPE=verilog.quote(random.choice(['ASYNC', 'SYNC'])),
|
||||
))
|
||||
else:
|
||||
assert False, ilogic_site_type
|
||||
|
||||
if use_oserdes:
|
||||
ports = []
|
||||
|
||||
add_port(
|
||||
ports, 'CLKDIV',
|
||||
clocks.get_clock(
|
||||
ologic_site,
|
||||
allow_ioclks=False,
|
||||
allow_rclks=True,
|
||||
)[0])
|
||||
|
||||
add_port(ports, 'CLK', oclk)
|
||||
|
||||
output.append(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
OSERDESE2 #(
|
||||
.DATA_RATE_OQ("SDR"),
|
||||
.DATA_RATE_TQ("SDR")
|
||||
) oserdes_{site} (
|
||||
{ports});""".format(
|
||||
site=ologic_site,
|
||||
ports=',\n'.join(ports),
|
||||
))
|
||||
|
||||
for s in clocks.lut_maker.create_wires_and_luts():
|
||||
print(s)
|
||||
|
||||
for s in output:
|
||||
print(s)
|
||||
|
||||
print("endmodule")
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
run()
|
||||
|
|
@ -88,6 +88,7 @@ $(eval $(call fuzzer,034-cmt-pll-pips,005-tilegrid))
|
|||
$(eval $(call fuzzer,035-iob-ilogic,005-tilegrid))
|
||||
$(eval $(call fuzzer,035a-iob-idelay,005-tilegrid))
|
||||
$(eval $(call fuzzer,036-iob-ologic,005-tilegrid))
|
||||
$(eval $(call fuzzer,037-iob-pips,005-tilegrid))
|
||||
$(eval $(call fuzzer,038-cfg,005-tilegrid))
|
||||
$(eval $(call fuzzer,040-clk-hrow-config,005-tilegrid))
|
||||
$(eval $(call fuzzer,041-clk-hrow-pips,005-tilegrid))
|
||||
|
|
|
|||
|
|
@ -209,12 +209,22 @@ def run(
|
|||
if side == "r" and not r:
|
||||
continue
|
||||
|
||||
if side != "":
|
||||
side = "_" + side
|
||||
if side == "xl":
|
||||
segfile = "l{}".format(seg_type)
|
||||
pipfile = "l{}".format(pip_type)
|
||||
elif side == "xr":
|
||||
segfile = "r{}".format(seg_type)
|
||||
pipfile = "r{}".format(pip_type)
|
||||
elif side == "l" or side == "r":
|
||||
segfile = "{}_{}".format(seg_type, side)
|
||||
pipfile = "{}_{}".format(pip_type, side)
|
||||
else:
|
||||
segfile = "{}".format(seg_type)
|
||||
pipfile = "{}".format(pip_type)
|
||||
|
||||
maketodo(
|
||||
"%s/%s%s.txt" % (pip_dir, pip_type, side),
|
||||
"%s/segbits_%s%s.db" % (db_dir, seg_type, side),
|
||||
"%s/%s.txt" % (pip_dir, pipfile),
|
||||
"%s/segbits_%s.db" % (db_dir, segfile),
|
||||
intre,
|
||||
exclude_re=exclude_re,
|
||||
balance_wire_re=balance_wire_re,
|
||||
|
|
|
|||
Loading…
Reference in New Issue