mirror of https://github.com/openXC7/prjxray.git
Merge pull request #983 from litghost/iob_diff
Add initial DIFF_ support to IOB fuzzer.
This commit is contained in:
litghost
GitHub
commit
11b5f39a78
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@ -22,8 +22,11 @@ import generate
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def process_parts(parts):
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if len(parts) == 0:
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return
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if parts[-1] == 'IN_ONLY':
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yield 'type', ['IBUF']
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yield 'type', ['IBUF', 'IBUFDS']
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if len(parts) > 2 and parts[-2] == 'SLEW':
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yield 'SLEW', verilog.quote(parts[-1])
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@ -35,6 +38,10 @@ def process_parts(parts):
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yield 'IOSTANDARDS', parts[0].split('_')
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yield 'IN', True
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if len(parts) > 1 and parts[1] == 'IN_DIFF':
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yield 'IOSTANDARDS', parts[0].split('_')
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yield 'IN_DIFF', True
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if len(parts) > 1 and parts[1] == 'DRIVE':
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yield 'IOSTANDARDS', parts[0].split('_')
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@ -47,6 +54,8 @@ def process_parts(parts):
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def create_sites_from_fasm(fasm_file):
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sites = {}
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diff_tiles = set()
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with open(fasm_file) as f:
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for l in f:
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if 'IOB33' not in l:
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@ -55,19 +64,27 @@ def create_sites_from_fasm(fasm_file):
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parts = l.strip().split('.')
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tile = parts[0]
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site = parts[1]
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if 'OUT_DIFF' == site:
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diff_tiles.add(tile)
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continue
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if (tile, site) not in sites:
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sites[(tile, site)] = {
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'tile': tile,
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'site_key': site,
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}
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if len(parts) > 3 and 'IN_DIFF' == parts[3]:
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diff_tiles.add(tile)
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for key, value in process_parts(parts[2:]):
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sites[(tile, site)][key] = value
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for key in sites:
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if 'type' not in sites[key]:
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if 'IOSTANDARDS' not in sites[key]:
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sites[key]['type'] = None
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sites[key]['type'] = [None]
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else:
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assert 'IOSTANDARDS' in sites[key], sites[key]
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assert 'DRIVES' in sites[key], sites[key]
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@ -77,15 +94,17 @@ def create_sites_from_fasm(fasm_file):
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else:
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sites[key]['type'] = [
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"OBUF",
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"OBUFDS",
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"OBUFTDS",
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"OBUFDS_DUAL_BUF",
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"OBUFTDS_DUAL_BUF",
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]
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return sites
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return sites, diff_tiles
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def process_specimen(fasm_file, params_json):
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sites = create_sites_from_fasm(fasm_file)
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sites, diff_tiles = create_sites_from_fasm(fasm_file)
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with open(params_json) as f:
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params = json.load(f)
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@ -107,8 +126,12 @@ def process_specimen(fasm_file, params_json):
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site_from_fasm = sites[(tile, site_key)]
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assert p['type'] in site_from_fasm['type'], (
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tile, site_key, p['type'], site_from_fasm['type'])
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if site_y == 0 or tile not in diff_tiles:
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assert p['type'] in site_from_fasm['type'], (
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tile, site_key, p['type'], site_from_fasm['type'])
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else:
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# Y1 on DIFF tiles is always none.
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assert p['type'] is None, p
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if p['type'] is None:
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continue
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@ -136,7 +159,7 @@ def process_specimen(fasm_file, params_json):
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site_from_fasm['IOSTANDARDS'],
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)
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if p['type'] != 'IBUF':
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if p['type'] not in ['IBUF', 'IBUFDS']:
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if verilog.unquote(p['SLEW']) == '':
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# Default is None.
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slew = verilog.quote('SLOW')
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@ -48,6 +48,7 @@ def drives_for_iostandard(iostandard):
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STEPDOWN_IOSTANDARDS = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'SSTL135']
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IBUF_LOW_PWR_SUPPORTED = ['SSTL135']
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def main():
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@ -61,18 +62,36 @@ def main():
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with open('params.json', 'r') as f:
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design = json.load(f)
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diff_pairs = set()
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for d in design['tiles']:
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iostandard = verilog.unquote(d['IOSTANDARD'])
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if iostandard.startswith('DIFF_'):
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diff_pairs.add(d['pair_site'])
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for d in design['tiles']:
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site = d['site']
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if skip_broken_tiles(d):
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continue
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if site in diff_pairs:
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continue
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iostandard = verilog.unquote(d['IOSTANDARD'])
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if iostandard.startswith('DIFF_'):
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iostandard = iostandard[5:]
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segmk.add_site_tag(
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site, '_'.join(STEPDOWN_IOSTANDARDS) + '.STEPDOWN',
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iostandard in STEPDOWN_IOSTANDARDS)
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if 'IN_TERM' in d:
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segmaker.add_site_group_zero(
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segmk, site, 'IN_TERM.', [
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'NONE', 'UNTUNED_SPLIT_40', 'UNTUNED_SPLIT_50',
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'UNTUNED_SPLIT_60'
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], 'NONE', d['IN_TERM'])
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if d['type'] is None:
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)
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@ -83,13 +102,43 @@ def main():
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN_DIFF'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 1)
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segmk.add_tile_tag(d['tile'], 'IN_DIFF', 0)
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if iostandard in IBUF_LOW_PWR_SUPPORTED:
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segmk.add_site_tag(site, 'IBUF_LOW_PWR', d['IBUF_LOW_PWR'])
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segmk.add_site_tag(
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site, 'ZIBUF_LOW_PWR', 1 ^ d['IBUF_LOW_PWR'])
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elif d['type'] == 'IBUFDS':
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN_DIFF'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 1)
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segmk.add_tile_tag(d['tile'], 'IN_DIFF', 1)
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elif d['type'] == 'OBUF':
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
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segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 0)
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elif d['type'] == 'OBUFDS':
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
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segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 1)
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segmk.add_tile_tag(d['tile'], 'OUT_TDIFF', 0)
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elif d['type'] == 'OBUFTDS':
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
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segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 1)
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segmk.add_tile_tag(d['tile'], 'OUT_TDIFF', 1)
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elif d['type'] == 'IOBUF_INTERMDISABLE':
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segmk.add_site_tag(site, 'INOUT', 1)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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@ -102,7 +151,7 @@ def main():
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("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
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verilog.unquote(d['PULLTYPE']))
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if d['type'] == 'IBUF' or d['type'] is None:
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if d['type'] in [None, 'IBUF', 'IBUFDS']:
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continue
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drive_opts = set()
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@ -44,6 +44,7 @@ proc loc_pins {} {
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set drive [lindex $line 4]
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set slew [lindex $line 5]
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set pulltype [lindex $line 6]
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set in_term [lindex $line 7]
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# Have: site
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# Want: pin for site
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@ -69,6 +70,10 @@ proc loc_pins {} {
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lappend props SLEW $slew
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}
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if {$in_term != "None"} {
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lappend props IN_TERM $in_term
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}
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puts $props
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set_property -dict "$props" $port
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@ -21,7 +21,7 @@ def get_site(l):
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def parse_bits(l):
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parts = l.strip().split(' ')
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if parts[1] == '<0':
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if parts[1] in ['<0', '<const0>']:
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return frozenset()
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else:
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return frozenset(parts[1:])
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@ -93,7 +93,8 @@ def main():
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if group in ['DRIVE', 'SLEW']:
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enum = feature_parts[4]
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sites[site][group][(iostandard, enum)] = bits
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elif group in ['IN', 'IN_ONLY', 'IN_USE', 'OUT', 'STEPDOWN']:
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elif group in ['IN', 'IN_DIFF', 'IN_ONLY', 'IN_USE', 'OUT',
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'STEPDOWN']:
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sites[site][group][(iostandard, None)] = bits
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else:
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assert False, group
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@ -124,6 +125,9 @@ def main():
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common_bits[(site, 'IN_ONLY')] |= common_bits[(site, 'DRIVE')]
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common_bits[(site, 'IN_ONLY')] -= common_bits[(site, 'STEPDOWN')]
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common_bits[(site, 'IN')] |= common_bits[(site, 'IN_DIFF')]
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common_bits[(site, 'IN_DIFF')] |= common_bits[(site, 'IN')]
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for iostandard, enum in sites[site]['DRIVE']:
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slew_in_drive = common_bits[
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(site, 'SLEW')] & sites[site]['DRIVE'][(iostandard, enum)]
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@ -142,10 +146,22 @@ def main():
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sites[site]['SLEW'][(iostandard,
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enum)] |= slew_in_drives[(site, iostandard)]
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for site in sites:
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for iostandard, enum in sites[site]['DRIVE']:
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sites[site]['DRIVE'][(iostandard, enum)] |= sites[site]['IN_USE'][(
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iostandard, None)]
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for iostandard, enum in sites[site]['IN']:
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if sites[site]['IN_DIFF'][(iostandard, enum)]:
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sites[site]['IN_DIFF'][(iostandard, enum)] |= \
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sites[site]['IN'][(iostandard, enum)]
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for site in sites:
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del sites[site]['OUT']
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del sites[site]['IN_USE']
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allow_zero = ['SLEW']
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for site in sites:
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for group in sites[site]:
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common_groups = {}
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@ -184,6 +200,9 @@ def main():
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group=group,
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)
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if not bits and group not in allow_zero:
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continue
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neg_bits = frozenset(
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'!{}'.format(b)
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for b in (common_bits[(site, group)] - bits))
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@ -22,9 +22,13 @@ def gen_sites():
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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sites = {}
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['IOB33S', 'IOB33M']:
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yield tile_name, site_name
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sites[site_type] = site_name
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if sites:
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yield tile_name, sites
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def write_params(params):
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@ -53,6 +57,24 @@ def run():
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'LVTTL',
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'SSTL135',
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]
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diff_map = {
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"SSTL135": ["DIFF_SSTL135"],
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}
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IN_TERM_ALLOWED = [
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'SSTL15',
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'SSTL15_R',
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'SSTL18',
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'SSTL18_R',
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'SSTL135',
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'SSTL135_R',
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'HSTL_I'
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'HSTL_I_18'
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'HSTL_II',
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'HSTL_II_18',
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]
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iostandard = random.choice(iostandards)
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if iostandard in ['LVTTL', 'LVCMOS18']:
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@ -93,70 +115,151 @@ def run():
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))
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any_idelay = False
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for tile, site in gen_sites():
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p = {}
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p['tile'] = tile
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p['site'] = site
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p['type'] = random.choice(tile_types)
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p['IOSTANDARD'] = verilog.quote(iostandard)
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p['PULLTYPE'] = verilog.quote(random.choice(pulls))
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for tile, sites in gen_sites():
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site_bels = {}
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for site_type in sites:
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if site_type.endswith('M'):
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if iostandard in diff_map:
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site_bels[site_type] = random.choice(
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tile_types + ['IBUFDS', 'OBUFDS', 'OBUFTDS'])
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else:
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site_bels[site_type] = random.choice(tile_types)
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is_m_diff = site_bels[site_type] is not None and site_bels[
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site_type].endswith('DS')
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else:
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site_bels[site_type] = random.choice(tile_types)
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if p['type'] is None:
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p['pad_wire'] = None
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elif p['type'] == 'IBUF':
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p['pad_wire'] = 'di[{}]'.format(i_idx)
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p['IDELAY_ONLY'] = random.randint(0, 1)
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if not p['IDELAY_ONLY']:
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if is_m_diff:
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site_bels['IOB33S'] = None
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for site_type, site in sites.items():
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p = {}
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p['tile'] = tile
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p['site'] = site
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p['type'] = site_bels[site_type]
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if p['type'] is not None and p['type'].endswith('DS'):
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iostandard_site = random.choice(diff_map[iostandard])
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p['pair_site'] = sites['IOB33S']
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else:
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iostandard_site = iostandard
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p['IOSTANDARD'] = verilog.quote(iostandard_site)
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p['PULLTYPE'] = verilog.quote(random.choice(pulls))
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if p['type'] is None:
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p['pad_wire'] = None
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elif p['type'] == 'IBUF':
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p['pad_wire'] = 'di[{}]'.format(i_idx)
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p['IDELAY_ONLY'] = random.randint(0, 1)
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if not p['IDELAY_ONLY']:
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p['owire'] = luts.get_next_input_net()
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else:
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any_idelay = True
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p['owire'] = 'idelay_{site}'.format(**p)
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p['DRIVE'] = None
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p['SLEW'] = None
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p['IBUF_LOW_PWR'] = random.randint(0, 1)
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if iostandard in IN_TERM_ALLOWED:
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p['IN_TERM'] = random.choice(
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(
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'NONE',
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'UNTUNED_SPLIT_40',
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'UNTUNED_SPLIT_50',
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'UNTUNED_SPLIT_60',
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))
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i_idx += 1
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elif p['type'] == 'IBUFDS':
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p['pad_wire'] = 'di[{}]'.format(i_idx)
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i_idx += 1
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p['bpad_wire'] = 'di[{}]'.format(i_idx)
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i_idx += 1
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p['IDELAY_ONLY'] = random.randint(0, 1)
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p['DIFF_TERM'] = random.randint(0, 1)
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if not p['IDELAY_ONLY']:
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p['owire'] = luts.get_next_input_net()
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else:
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any_idelay = True
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p['owire'] = 'idelay_{site}'.format(**p)
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p['DRIVE'] = None
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p['SLEW'] = None
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p['IBUF_LOW_PWR'] = random.randint(0, 1)
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elif p['type'] == 'OBUF':
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p['pad_wire'] = 'do[{}]'.format(o_idx)
|
||||
p['iwire'] = luts.get_next_output_net()
|
||||
if drives is not None:
|
||||
p['DRIVE'] = random.choice(drives)
|
||||
else:
|
||||
p['DRIVE'] = None
|
||||
p['SLEW'] = verilog.quote(random.choice(slews))
|
||||
|
||||
o_idx += 1
|
||||
elif p['type'] == 'OBUFDS':
|
||||
p['pad_wire'] = 'do[{}]'.format(o_idx)
|
||||
o_idx += 1
|
||||
p['bpad_wire'] = 'do[{}]'.format(o_idx)
|
||||
o_idx += 1
|
||||
p['iwire'] = luts.get_next_output_net()
|
||||
if drives is not None:
|
||||
p['DRIVE'] = random.choice(drives)
|
||||
else:
|
||||
p['DRIVE'] = None
|
||||
p['SLEW'] = verilog.quote(random.choice(slews))
|
||||
elif p['type'] == 'OBUFTDS':
|
||||
p['pad_wire'] = 'do[{}]'.format(o_idx)
|
||||
o_idx += 1
|
||||
p['bpad_wire'] = 'do[{}]'.format(o_idx)
|
||||
o_idx += 1
|
||||
p['tristate_wire'] = random.choice(
|
||||
('0', luts.get_next_output_net()))
|
||||
p['iwire'] = luts.get_next_output_net()
|
||||
if drives is not None:
|
||||
p['DRIVE'] = random.choice(drives)
|
||||
else:
|
||||
p['DRIVE'] = None
|
||||
p['SLEW'] = verilog.quote(random.choice(slews))
|
||||
elif p['type'] == 'IOBUF_INTERMDISABLE':
|
||||
p['pad_wire'] = 'dio[{}]'.format(io_idx)
|
||||
p['iwire'] = luts.get_next_output_net()
|
||||
p['owire'] = luts.get_next_input_net()
|
||||
else:
|
||||
any_idelay = True
|
||||
p['owire'] = 'idelay_{site}'.format(**p)
|
||||
if drives is not None:
|
||||
p['DRIVE'] = random.choice(drives)
|
||||
else:
|
||||
p['DRIVE'] = None
|
||||
p['SLEW'] = verilog.quote(random.choice(slews))
|
||||
p['tristate_wire'] = random.choice(
|
||||
('0', luts.get_next_output_net()))
|
||||
p['ibufdisable_wire'] = random.choice(
|
||||
('0', luts.get_next_output_net()))
|
||||
p['intermdisable_wire'] = random.choice(
|
||||
('0', luts.get_next_output_net()))
|
||||
io_idx += 1
|
||||
|
||||
p['DRIVE'] = None
|
||||
p['SLEW'] = None
|
||||
p['IBUF_LOW_PWR'] = random.randint(0, 1)
|
||||
if 'DRIVE' in p:
|
||||
if p['DRIVE'] is not None:
|
||||
p['DRIVE_STR'] = '.DRIVE({}),'.format(p['DRIVE'])
|
||||
else:
|
||||
p['DRIVE_STR'] = ''
|
||||
|
||||
i_idx += 1
|
||||
elif p['type'] == 'OBUF':
|
||||
p['pad_wire'] = 'do[{}]'.format(o_idx)
|
||||
p['iwire'] = luts.get_next_output_net()
|
||||
if drives is not None:
|
||||
p['DRIVE'] = random.choice(drives)
|
||||
else:
|
||||
p['DRIVE'] = None
|
||||
p['SLEW'] = verilog.quote(random.choice(slews))
|
||||
|
||||
o_idx += 1
|
||||
elif p['type'] == 'IOBUF_INTERMDISABLE':
|
||||
p['pad_wire'] = 'dio[{}]'.format(io_idx)
|
||||
p['iwire'] = luts.get_next_output_net()
|
||||
p['owire'] = luts.get_next_input_net()
|
||||
if drives is not None:
|
||||
p['DRIVE'] = random.choice(drives)
|
||||
else:
|
||||
p['DRIVE'] = None
|
||||
p['SLEW'] = verilog.quote(random.choice(slews))
|
||||
p['tristate_wire'] = random.choice(
|
||||
('0', luts.get_next_output_net()))
|
||||
p['ibufdisable_wire'] = random.choice(
|
||||
('0', luts.get_next_output_net()))
|
||||
p['intermdisable_wire'] = random.choice(
|
||||
('0', luts.get_next_output_net()))
|
||||
io_idx += 1
|
||||
|
||||
if 'DRIVE' in p:
|
||||
if p['DRIVE'] is not None:
|
||||
p['DRIVE_STR'] = '.DRIVE({}),'.format(p['DRIVE'])
|
||||
else:
|
||||
p['DRIVE_STR'] = ''
|
||||
|
||||
if p['type'] is not None:
|
||||
tile_params.append(
|
||||
(
|
||||
tile, site, p['pad_wire'], iostandard, p['DRIVE'],
|
||||
verilog.unquote(p['SLEW']) if p['SLEW'] else None,
|
||||
verilog.unquote(p['PULLTYPE'])))
|
||||
params['tiles'].append(p)
|
||||
if p['type'] is not None:
|
||||
tile_params.append(
|
||||
(
|
||||
tile,
|
||||
site,
|
||||
p['pad_wire'],
|
||||
iostandard_site,
|
||||
p['DRIVE'],
|
||||
verilog.unquote(p['SLEW']) if p['SLEW'] else None,
|
||||
verilog.unquote(p['PULLTYPE']),
|
||||
p['IN_TERM'] if 'IN_TERM' in p else None,
|
||||
))
|
||||
params['tiles'].append(p)
|
||||
|
||||
write_params(tile_params)
|
||||
|
||||
|
|
@ -209,6 +312,31 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
|
|||
);""".format(**p),
|
||||
file=connects)
|
||||
|
||||
elif p['type'] == 'IBUFDS':
|
||||
print(
|
||||
'''
|
||||
wire idelay_{site};
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
IBUFDS #(
|
||||
.IBUF_LOW_PWR({IBUF_LOW_PWR}),
|
||||
.DIFF_TERM({DIFF_TERM}),
|
||||
.IOSTANDARD({IOSTANDARD})
|
||||
) ibuf_{site} (
|
||||
.I({pad_wire}),
|
||||
.IB({bpad_wire}),
|
||||
.O({owire})
|
||||
);'''.format(**p),
|
||||
file=connects)
|
||||
if p['IDELAY_ONLY']:
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
IDELAYE2 idelay_site_{site} (
|
||||
.IDATAIN(idelay_{site})
|
||||
);""".format(**p),
|
||||
file=connects)
|
||||
|
||||
elif p['type'] == 'OBUF':
|
||||
print(
|
||||
'''
|
||||
|
|
@ -217,11 +345,40 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
|
|||
.IOSTANDARD({IOSTANDARD}),
|
||||
{DRIVE_STR}
|
||||
.SLEW({SLEW})
|
||||
) ibuf_{site} (
|
||||
) obuf_{site} (
|
||||
.O({pad_wire}),
|
||||
.I({iwire})
|
||||
);'''.format(**p),
|
||||
file=connects)
|
||||
elif p['type'] == 'OBUFDS':
|
||||
print(
|
||||
'''
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
OBUFDS #(
|
||||
.IOSTANDARD({IOSTANDARD}),
|
||||
{DRIVE_STR}
|
||||
.SLEW({SLEW})
|
||||
) obufds_{site} (
|
||||
.O({pad_wire}),
|
||||
.OB({bpad_wire}),
|
||||
.I({iwire})
|
||||
);'''.format(**p),
|
||||
file=connects)
|
||||
elif p['type'] == 'OBUFTDS':
|
||||
print(
|
||||
'''
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
OBUFTDS #(
|
||||
.IOSTANDARD({IOSTANDARD}),
|
||||
{DRIVE_STR}
|
||||
.SLEW({SLEW})
|
||||
) obufds_{site} (
|
||||
.O({pad_wire}),
|
||||
.OB({bpad_wire}),
|
||||
.T({tristate_wire}),
|
||||
.I({iwire})
|
||||
);'''.format(**p),
|
||||
file=connects)
|
||||
elif p['type'] == 'IOBUF_INTERMDISABLE':
|
||||
print(
|
||||
'''
|
||||
|
|
|
|||
Loading…
Reference in New Issue