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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-10-02 09:20:32 +02:00
parent 205bc5c1df
commit a4250c1487
1 changed files with 17 additions and 6 deletions
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23
fuzzers/034-cmt-pll-pips/top.py
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@ -113,14 +113,25 @@ module top();
endpoints = {}
pins = [
# ('CLKIN1', 'up'),
# ('CLKIN2', 'up'),
# Enabling random manual routing for CLKINx breaks solution for
# tags:
# - CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT
# - CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT
#('CLKIN1', 'up'),
#('CLKIN2', 'up'),
# This works:
('CLKFBIN', 'up'),
('CLKFBOUT', 'down'),
# ('CLKOUT0', 'down'),
# ('CLKOUT1', 'down'),
# ('CLKOUT2', 'down'),
# ('CLKOUT3', 'down'),
# Sometimes manually randomized route for CLKOUTx conflicts with
# the verilog design. Need to fix that in the future.
#('CLKOUT0', 'down'),
#('CLKOUT1', 'down'),
#('CLKOUT2', 'down'),
#('CLKOUT3', 'down'),
]
occupied_wires = set()