mirror of https://github.com/openXC7/prjxray.git
038-cfg: Add fuzzer for the CFG tile
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This commit is contained in:
Tomasz Michalak
parent
e8fdac9f70
commit
f5ba30a81c
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@ -0,0 +1,17 @@
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N = 24
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include ../fuzzer.mk
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database: build/segbits_cfg.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_cfg.rdb \
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--seg-fn-out build/segbits_cfg.db
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build/segbits_cfg.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -c 15 -o build/segbits_cfg.rdb $$(find -name segdata_cfg_center_mid.txt)
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pushdb:
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${XRAY_MERGEDB} cfg_center_mid build/segbits_cfg.db
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.PHONY: database pushdb
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@ -0,0 +1,4 @@
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This fuzzer solves some of the bits in the CFG_CENTER_MID tile
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The tile contains sites of the following types: BSCAN, USR_ACCESS, CAPTURE, STARTUP, FRAME_ECC, DCIRESET and ICAP.
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DCIRESET and USR_ACCESS don't really have any parameters.
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The parameters on CAPTURE and FRAME_ECC don't toggle any bits in the bitstream.
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@ -0,0 +1,56 @@
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#!/usr/bin/env python3
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import json
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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from prjxray import segmaker
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def bitfilter(frame, word):
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if frame < 26:
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return False
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return True
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def run():
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segmk = Segmaker("design.bits")
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print("Loading tags")
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f = open('params.jl', 'r')
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design = json.load(f)
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for p in design:
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ps = p["params"]
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if p["site_type"] in "ICAP":
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param = verilog.unquote(ps["ICAP_WIDTH"])
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segmaker.add_site_group_zero(
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segmk, p["site"], "ICAP_WIDTH_", ["X32", "X8", "X16"], "X32",
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param)
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elif p["site_type"] in "BSCAN":
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param = str(ps["JTAG_CHAIN"])
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segmaker.add_site_group_zero(
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segmk, p["site"], "JTAG_CHAIN_", ["1", "2", "3", "4"], param,
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param)
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elif p["site_type"] in "CAPTURE":
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param = verilog.unquote(ps["ONESHOT"])
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segmk.add_site_tag(
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p["site"], "ONESHOT", True if param in "TRUE" else False)
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elif p["site_type"] in "STARTUP":
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param = verilog.unquote(ps["PROG_USR"])
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segmk.add_site_tag(
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p["site"], "PROG_USR", True if param in "TRUE" else False)
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elif p["site_type"] in "FRAME_ECC":
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param = verilog.unquote(ps["FARSRC"])
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segmaker.add_site_group_zero(
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segmk, p["site"], "FARSRC_", ["FAR", "EFAR"], param, param)
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elif p["site_type"] in ["USR_ACCESS", "DCIRESET"]:
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feature = "ENABLED"
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segmk.add_site_tag(
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p["site"], feature, True if ps["ENABLED"] else False)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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run()
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@ -0,0 +1,5 @@
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#!/bin/bash
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set -ex
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source ${XRAY_DIR}/utils/top_generate.sh
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@ -0,0 +1,35 @@
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create_project -force -part $::env(XRAY_PART) design design
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#read_verilog $::env(FUZDIR)/top.v
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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set_property IS_ENABLED 0 [get_drc_checks {DRC NDRV-1}]
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# Disable MMCM frequency etc sanity checks
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#set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
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#set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
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#set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
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#set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
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#set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
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# PLL
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#set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,307 @@
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import json
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import io
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import os
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import random
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import re
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import lut_maker
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from prjxray import verilog
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from prjxray.db import Database
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def gen_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['BSCAN', 'CAPTURE', 'ICAP', 'USR_ACCESS',
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'STARTUP', 'FRAME_ECC', 'DCIRESET']:
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if site_name not in 'ICAP_X0Y0':
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yield site_name, site_type
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def write_csv_params(params):
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pinstr = 'tile,site,\n'
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for vals in params:
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pinstr += ','.join(map(str, vals)) + '\n'
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open('params.csv', 'w').write(pinstr)
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def generate_params():
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bscan_already_on = False
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icap_already_on = False
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tile_params = []
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for loci, (site, site_type) in enumerate(sorted(gen_sites())):
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p = {}
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if site_type in "ICAP" and not icap_already_on:
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p["ICAP_WIDTH"] = verilog.quote(
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random.choice(["X32", "X8", "X16"]))
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elif site_type in "BSCAN" and not bscan_already_on:
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p["JTAG_CHAIN"] = random.randint(1, 4)
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bscan_already_on = True
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elif site_type in "CAPTURE":
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p["ONESHOT"] = verilog.quote(random.choice(["TRUE", "FALSE"]))
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elif site_type in "STARTUP":
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p["PROG_USR"] = verilog.quote(random.choice(["TRUE", "FALSE"]))
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elif site_type in "FRAME_ECC":
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p["FARSRC"] = verilog.quote(random.choice(["FAR", "EFAR"]))
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elif site_type in [
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"DCIRESET", "USR_ACCESS"
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]: #The primitives from these sites have no parameters
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p["ENABLED"] = random.randint(0, 1)
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else:
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continue
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p["LOC"] = verilog.quote(site)
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tile_params.append(
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{
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"site": site,
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"site_type": site_type,
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"module": "mod_{}".format(site_type),
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"params": p
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})
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return tile_params
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def generate_netlist(params):
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DUTN = len(params)
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DIN_N = DUTN * 32
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DOUT_N = DUTN * 32
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string_output = io.StringIO()
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any_bscan = False
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any_icap = False
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usr_access_on = False
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capture_on = False
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startup_on = False
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frame_ecc_on = False
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dcireset_on = False
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luts = lut_maker.LutMaker()
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verilog.top_harness(DIN_N, DOUT_N)
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print(
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'''
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module roi(input clk, input [%d:0] din, output [%d:0] dout);''' %
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(DIN_N - 1, DOUT_N - 1))
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for loci, param in enumerate(params):
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ports = {
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'din': 'din[{} +: 8]'.format(8 * loci),
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'dout': 'dout[{} +: 8]'.format(8 * loci),
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'clk': 'clk'
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}
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if param["site_type"] in "BSCAN":
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ports = {
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'din':
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'{{din[{} +: 7],{}}}'.format(
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8 * loci + 1, luts.get_next_output_net()),
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'dout':
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'{{dout[{} +: 7],{}}}'.format(
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8 * loci + 1, luts.get_next_input_net()),
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'clk':
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'clk'
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}
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any_bscan = True
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elif param["site_type"] in ["ICAP"]:
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any_icap = True
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elif param["site_type"] in ["CAPTURE"]:
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capture_on = True
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elif param["site_type"] in ["STARTUP"]:
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startup_on = True
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elif param["site_type"] in ["FRAME_ECC"]:
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frame_ecc_on = True
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elif param["site_type"] in ["USR_ACCESS", "DCIRESET"]:
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if not param["params"]["ENABLED"]:
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continue
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if param["site_type"] in ["DCIRESET"]:
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dcireset_on = True
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else:
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usr_access_on = True
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else:
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continue
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verilog.instance(
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param["module"],
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"inst_{}".format(param["site"]),
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ports,
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param["params"],
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string_buffer=string_output)
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#Generate LUTs
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for l in luts.create_wires_and_luts():
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print(l)
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print(string_output.getvalue())
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print(
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'''
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endmodule
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// ---------------------------------------------------------------------''')
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if any_icap:
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print(
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'''
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module mod_ICAP (input [7:0] din, output [7:0] dout, input clk);
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parameter ICAP_WIDTH = "X32";
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parameter LOC = "ICAP_X0Y0";
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wire [23:0] icap_out;
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(* KEEP, DONT_TOUCH, LOC=LOC *)
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ICAPE2 #(
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.ICAP_WIDTH(ICAP_WIDTH),
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.SIM_CFG_FILE_NAME("NONE")
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)
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ICAPE2_inst (
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.O({icap_out, dout}),
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.CLK(clk),
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.CSIB(),
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.I({24'd0, din}),
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.RDWRB()
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);
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endmodule
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''')
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if capture_on:
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print(
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'''
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module mod_CAPTURE (input [7:0] din, output [7:0] dout, input clk);
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parameter ONESHOT ="TRUE";
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parameter LOC = "ICAP_X0Y0";
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(* KEEP, DONT_TOUCH, LOC=LOC *)
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CAPTUREE2 #(
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.ONESHOT(ONESHOT) // Specifies the procedure for performing single readback per CAP trigger.
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)
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CAPTUREE2_inst (
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.CAP(1'b0),
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.CLK(clk)
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);
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endmodule
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''')
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if usr_access_on:
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print(
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'''
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module mod_USR_ACCESS (input [7:0] din, output [7:0] dout, input clk);
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parameter ENABLED = 1;
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parameter LOC = "USR_ACCESS_X0Y0";
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wire [23:0] usr_access_wire;
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(* KEEP, DONT_TOUCH, LOC=LOC *)
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USR_ACCESSE2 USR_ACCESSE2_inst (
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.CFGCLK(),
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.DATA({usr_access_wire, dout}),
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.DATAVALID()
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);
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endmodule
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''')
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if any_bscan:
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print(
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'''
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module mod_BSCAN (input [7:0] din, output [7:0] dout, input clk);
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parameter JTAG_CHAIN = 1;
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parameter LOC = "BSCAN_X0Y0";
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(* KEEP, DONT_TOUCH, LOC=LOC *)
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BSCANE2 #(
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.JTAG_CHAIN(JTAG_CHAIN)
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)
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dut (
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.CAPTURE(),
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.DRCK(),
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.RESET(),
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.RUNTEST(),
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.SEL(),
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.SHIFT(),
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.TCK(),
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.TDI(dout[0]),
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.TMS(),
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.UPDATE(),
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.TDO(din[0])
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);
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endmodule
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''')
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if startup_on:
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print(
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'''
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module mod_STARTUP (input [7:0] din, output [7:0] dout, input clk);
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parameter LOC = "STARTUP_X0Y0";
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parameter PROG_USR = "FALSE";
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(* KEEP, DONT_TOUCH, LOC=LOC *)
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STARTUPE2 #(
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.PROG_USR(PROG_USR), // Activate program event security feature. Requires encrypted bitstreams.
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.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.
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)
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STARTUPE2_inst (
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.CFGCLK(),
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.CFGMCLK(),
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.EOS(),
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.PREQ(dout[0]),
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.CLK(clk),
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.GSR(),
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.GTS(),
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.KEYCLEARB(),
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.PACK(),
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.USRCCLKO(),
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.USRCCLKTS(),
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.USRDONEO(),
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.USRDONETS()
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);
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endmodule
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''')
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if frame_ecc_on:
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print(
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'''
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module mod_FRAME_ECC (input [7:0] din, output [7:0] dout, input clk);
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parameter LOC = "FRAME_ECC_X0Y0";
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parameter FARSRC = "EFAR";
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wire [25:0] far_wire;
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assign dout[7:0] = far_wire[7:0];
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(* KEEP, DONT_TOUCH, LOC=LOC *)
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FRAME_ECCE2 #(
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.FARSRC(FARSRC),
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.FRAME_RBT_IN_FILENAME("NONE")
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)
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FRAME_ECCE2_inst (
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.CRCERROR(),
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.ECCERROR(),
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.ECCERRORSINGLE(),
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.FAR(far_wire),
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.SYNBIT(),
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.SYNDROME(),
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.SYNDROMEVALID(),
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.SYNWORD()
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);
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endmodule
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''')
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if dcireset_on:
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print(
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'''
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module mod_DCIRESET (input [7:0] din, output [7:0] dout, input clk);
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parameter LOC = "FRAME_ECC_X0Y0";
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parameter ENABLED = 1;
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(* KEEP, DONT_TOUCH, LOC=LOC *)
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DCIRESET DCIRESET_inst (
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.LOCKED(dout[0]),
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.RST(dout[1])
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);
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endmodule
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''')
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def run():
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params = generate_params()
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generate_netlist(params)
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with open('params.jl', 'w') as f:
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json.dump(params, f, indent=2)
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if __name__ == '__main__':
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run()
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@ -87,6 +87,7 @@ $(eval $(call fuzzer,032-cmt-pll,005-tilegrid))
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$(eval $(call fuzzer,034-cmt-pll-pips,005-tilegrid))
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$(eval $(call fuzzer,035-iob-ilogic,005-tilegrid))
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$(eval $(call fuzzer,036-iob-ologic,005-tilegrid))
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$(eval $(call fuzzer,038-cfg,005-tilegrid))
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$(eval $(call fuzzer,040-clk-hrow-config,005-tilegrid))
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$(eval $(call fuzzer,041-clk-hrow-pips,005-tilegrid))
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$(eval $(call fuzzer,042-clk-bufg-config,005-tilegrid))
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@ -120,6 +120,9 @@ case "$1" in
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cmt_top_l_upper_t)
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sed < "$2" > "$tmp1" -e 's/^CMT_UPPER_T\./CMT_TOP_L_UPPER_T./' ;;
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cfg_center_mid)
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cp "$2" "$tmp1" ;;
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mask_*)
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db=$XRAY_DATABASE_DIR/$XRAY_DATABASE/$1.db
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ismask=true
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